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drm/amdgpu: save and restore gc hub regs

Save and restore gfxhub regs as they will be reset during mode 2

Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Victor Zhao and committed by
Alex Deucher
bfaced6e 5bd8d53f

+110 -1
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
··· 35 35 void (*init)(struct amdgpu_device *adev); 36 36 int (*get_xgmi_info)(struct amdgpu_device *adev); 37 37 void (*utcl2_harvest)(struct amdgpu_device *adev); 38 + void (*mode2_save_regs)(struct amdgpu_device *adev); 39 + void (*mode2_restore_regs)(struct amdgpu_device *adev); 38 40 }; 39 41 40 42 struct amdgpu_gfxhub {
+26
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
··· 264 264 u64 mall_size; 265 265 /* number of UMC instances */ 266 266 int num_umc; 267 + /* mode2 save restore */ 268 + u64 VM_L2_CNTL; 269 + u64 VM_L2_CNTL2; 270 + u64 VM_DUMMY_PAGE_FAULT_CNTL; 271 + u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 272 + u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 273 + u64 VM_L2_PROTECTION_FAULT_CNTL; 274 + u64 VM_L2_PROTECTION_FAULT_CNTL2; 275 + u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 276 + u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 277 + u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 278 + u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 279 + u64 VM_DEBUG; 280 + u64 VM_L2_MM_GROUP_RT_CLASSES; 281 + u64 VM_L2_BANK_SELECT_RESERVED_CID; 282 + u64 VM_L2_BANK_SELECT_RESERVED_CID2; 283 + u64 VM_L2_CACHE_PARITY_CNTL; 284 + u64 VM_L2_IH_LOG_CNTL; 285 + u64 VM_CONTEXT_CNTL[16]; 286 + u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 287 + u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 288 + u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 289 + u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 290 + u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 291 + u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 292 + u64 MC_VM_MX_L1_TLB_CNTL; 267 293 }; 268 294 269 295 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
+72
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
··· 576 576 } 577 577 } 578 578 579 + static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev) 580 + { 581 + int i; 582 + adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 583 + adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 584 + adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL); 585 + adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32); 586 + adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32); 587 + adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 588 + adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2); 589 + adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3); 590 + adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4); 591 + adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32); 592 + adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32); 593 + adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG); 594 + adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES); 595 + adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID); 596 + adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2); 597 + adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL); 598 + adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL); 599 + 600 + for (i = 0; i <= 15; i++) { 601 + adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i); 602 + adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2); 603 + adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2); 604 + adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2); 605 + adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2); 606 + adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2); 607 + adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2); 608 + } 609 + 610 + adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 611 + } 612 + 613 + static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev) 614 + { 615 + int i; 616 + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL); 617 + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2); 618 + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL, adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL); 619 + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32); 620 + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32); 621 + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL); 622 + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2); 623 + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3); 624 + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4); 625 + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32); 626 + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32); 627 + WREG32_SOC15(GC, 0, mmGCVM_DEBUG, adev->gmc.VM_DEBUG); 628 + WREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES, adev->gmc.VM_L2_MM_GROUP_RT_CLASSES); 629 + WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID); 630 + WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2); 631 + WREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL, adev->gmc.VM_L2_CACHE_PARITY_CNTL); 632 + WREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL, adev->gmc.VM_L2_IH_LOG_CNTL); 633 + 634 + for (i = 0; i <= 15; i++) { 635 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, adev->gmc.VM_CONTEXT_CNTL[i]); 636 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i]); 637 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i]); 638 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i]); 639 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i]); 640 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i]); 641 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i]); 642 + } 643 + 644 + WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24); 645 + WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, adev->gmc.vram_end >> 24); 646 + WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL); 647 + } 648 + 579 649 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { 580 650 .get_fb_location = gfxhub_v2_1_get_fb_location, 581 651 .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, ··· 656 586 .init = gfxhub_v2_1_init, 657 587 .get_xgmi_info = gfxhub_v2_1_get_xgmi_info, 658 588 .utcl2_harvest = gfxhub_v2_1_utcl2_harvest, 589 + .mode2_save_regs = gfxhub_v2_1_save_regs, 590 + .mode2_restore_regs = gfxhub_v2_1_restore_regs, 659 591 };
+6 -1
drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
··· 94 94 int r = 0; 95 95 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 96 96 97 - if (!amdgpu_sriov_vf(adev)) 97 + if (!amdgpu_sriov_vf(adev)) { 98 + if (adev->gfxhub.funcs->mode2_save_regs) 99 + adev->gfxhub.funcs->mode2_save_regs(adev); 98 100 r = sienna_cichlid_mode2_suspend_ip(adev); 101 + } 99 102 100 103 return r; 101 104 } ··· 154 151 } 155 152 156 153 /* Reinit GFXHUB */ 154 + if (adev->gfxhub.funcs->mode2_restore_regs) 155 + adev->gfxhub.funcs->mode2_restore_regs(adev); 157 156 adev->gfxhub.funcs->init(adev); 158 157 r = adev->gfxhub.funcs->gart_enable(adev); 159 158 if (r) {
+4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
··· 3129 3129 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 3130 3130 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc 3131 3131 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 3132 + #define mmGCVM_DEBUG 0x15cd 3133 + #define mmGCVM_DEBUG_BASE_IDX 0 3132 3134 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce 3133 3135 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 3134 3136 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf ··· 3153 3151 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 3154 3152 #define mmGCVM_L2_CACHE_PARITY_CNTL 0x15d8 3155 3153 #define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 3154 + #define mmGCVM_L2_IH_LOG_CNTL 0x15d9 3155 + #define mmGCVM_L2_IH_LOG_CNTL_BASE_IDX 0 3156 3156 #define mmGCVM_L2_CNTL5 0x15dc 3157 3157 #define mmGCVM_L2_CNTL5_BASE_IDX 0 3158 3158 #define mmGCVM_L2_GCR_CNTL 0x15dd