+11 -2

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 1159 1159 uint32_t reg, uint32_t acc_flags); 1160 1160 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1161 1161 u64 reg_addr); 1162 1162 + uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1163 1163 + uint32_t reg, uint32_t acc_flags, 1164 1164 + uint32_t xcc_id); 1162 1165 void amdgpu_device_wreg(struct amdgpu_device *adev, 1163 1166 uint32_t reg, uint32_t v, 1164 1167 uint32_t acc_flags); 1165 1168 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1166 1169 u64 reg_addr, u32 reg_data); 1170 1170 + void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1171 1171 + uint32_t reg, uint32_t v, 1172 1172 + uint32_t acc_flags, 1173 1173 + uint32_t xcc_id); 1167 1174 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1168 1175 uint32_t reg, uint32_t v, uint32_t xcc_id); 1169 1176 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); ··· 1211 1204 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1212 1205 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1213 1206 1214 1214 - #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1215 1215 - #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1207 1207 + #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1208 1208 + #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1216 1209 1217 1210 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1218 1211 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) ··· 1222 1215 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1223 1216 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1224 1217 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1218 1218 + #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1219 1219 + #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1225 1220 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1226 1221 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1227 1222 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

reviewed

··· 1494 1494 if (adev->asic_type < CHIP_RAVEN) 1495 1495 return false; 1496 1496 1497 1497 + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 1498 1498 + return false; 1499 1499 + 1497 1500 /* 1498 1501 * If ACPI_FADT_LOW_POWER_S0 is not set in the FADT, it is generally 1499 1502 * risky to do any special firmware-related preparations for entering

+18 -22

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

reviewed

··· 300 300 hqd_end = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_AQL_DISPATCH_ID_HI); 301 301 302 302 for (reg = hqd_base; reg <= hqd_end; reg++) 303 303 - WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); 303 303 + WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst); 304 304 305 305 306 306 /* Activate doorbell logic before triggering WPTR poll. */ 307 307 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 308 308 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 309 309 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL), 310 310 - data); 309 309 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL, data); 311 310 312 311 if (wptr) { 313 312 /* Don't read wptr with get_user because the user ··· 335 336 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 336 337 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 337 338 338 338 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO), 339 339 - lower_32_bits(guessed_wptr)); 340 340 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI), 341 341 - upper_32_bits(guessed_wptr)); 342 342 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR), 343 343 - lower_32_bits((uintptr_t)wptr)); 344 344 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), 345 345 - regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 339 339 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, 340 340 + lower_32_bits(guessed_wptr)); 341 341 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, 342 342 + upper_32_bits(guessed_wptr)); 343 343 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, 344 344 + lower_32_bits((uintptr_t)wptr)); 345 345 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 346 346 upper_32_bits((uintptr_t)wptr)); 347 347 - WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1), 348 348 - (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, 349 349 - queue_id)); 347 347 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, 348 348 + (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id)); 350 349 } 351 350 352 351 /* Start the EOP fetcher */ 353 353 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR), 354 354 - REG_SET_FIELD(m->cp_hqd_eop_rptr, 355 355 - CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 352 352 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR, 353 353 + REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 356 354 357 355 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 358 358 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE), data); 356 356 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); 359 357 360 358 kgd_gfx_v9_release_queue(adev, inst); 361 359 ··· 490 494 VALID, 491 495 1); 492 496 493 493 - WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), 497 497 + WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), 494 498 regTCP_WATCH0_ADDR_H) + 495 499 (watch_id * TCP_WATCH_STRIDE)), 496 496 - watch_address_high); 500 500 + watch_address_high, inst); 497 501 498 498 - WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), 502 502 + WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), 499 503 regTCP_WATCH0_ADDR_L) + 500 504 (watch_id * TCP_WATCH_STRIDE)), 501 501 - watch_address_low); 505 505 + watch_address_low, inst); 502 506 503 507 return watch_address_cntl; 504 508 }

+20 -22

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

reviewed

··· 91 91 { 92 92 kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst); 93 93 94 94 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG), sh_mem_config); 95 95 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases); 94 94 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config); 95 95 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); 96 96 /* APE1 no longer exists on GFX9 */ 97 97 98 98 kgd_gfx_v9_unlock_srbm(adev, inst); ··· 239 239 240 240 for (reg = hqd_base; 241 241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) 242 242 - WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); 242 242 + WREG32_XCC(reg, mqd_hqd[reg - hqd_base], inst); 243 243 244 244 245 245 /* Activate doorbell logic before triggering WPTR poll. */ 246 246 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 247 247 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 248 248 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL), 249 249 - data); 248 248 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); 250 249 251 250 if (wptr) { 252 251 /* Don't read wptr with get_user because the user ··· 274 275 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 275 276 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 276 277 277 277 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO), 278 278 - lower_32_bits(guessed_wptr)); 279 279 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI), 280 280 - upper_32_bits(guessed_wptr)); 281 281 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR), 282 282 - lower_32_bits((uintptr_t)wptr)); 283 283 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 284 284 - upper_32_bits((uintptr_t)wptr)); 285 285 - WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, 286 286 - (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id)); 278 278 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO, 279 279 + lower_32_bits(guessed_wptr)); 280 280 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, 281 281 + upper_32_bits(guessed_wptr)); 282 282 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR, 283 283 + lower_32_bits((uintptr_t)wptr)); 284 284 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 285 285 + upper_32_bits((uintptr_t)wptr)); 286 286 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, 287 287 + (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id)); 287 288 } 288 289 289 290 /* Start the EOP fetcher */ 290 290 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR), 291 291 - REG_SET_FIELD(m->cp_hqd_eop_rptr, 292 292 - CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 291 291 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR, 292 292 + REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 293 293 294 294 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 295 295 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE), data); 295 295 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data); 296 296 297 297 kgd_gfx_v9_release_queue(adev, inst); 298 298 ··· 554 556 break; 555 557 } 556 558 557 557 - WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST), type); 559 559 + WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type); 558 560 559 561 end_jiffies = (utimeout * HZ / 1000) + jiffies; 560 562 while (true) { ··· 906 908 uint32_t inst) 907 909 908 910 { 909 909 - *wait_times = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), 910 910 - mmCP_IQ_WAIT_TIME2)); 911 911 + *wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst), 912 912 + mmCP_IQ_WAIT_TIME2); 911 913 } 912 914 913 915 void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

reviewed

··· 172 172 } 173 173 174 174 rcu_read_unlock(); 175 175 + *result = NULL; 175 176 return -ENOENT; 176 177 } 177 178

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

reviewed

··· 1415 1415 if (r == -ENOMEM) 1416 1416 DRM_ERROR("Not enough memory for command submission!\n"); 1417 1417 else if (r != -ERESTARTSYS && r != -EAGAIN) 1418 1418 - DRM_ERROR("Failed to process the buffer list %d!\n", r); 1418 1418 + DRM_DEBUG("Failed to process the buffer list %d!\n", r); 1419 1419 goto error_fini; 1420 1420 } 1421 1421

+105 -9

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 73 73 #include "amdgpu_pmu.h" 74 74 #include "amdgpu_fru_eeprom.h" 75 75 #include "amdgpu_reset.h" 76 76 + #include "amdgpu_virt.h" 76 77 77 78 #include <linux/suspend.h> 78 79 #include <drm/task_barrier.h> ··· 473 472 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && 474 473 amdgpu_sriov_runtime(adev) && 475 474 down_read_trylock(&adev->reset_domain->sem)) { 476 476 - ret = amdgpu_kiq_rreg(adev, reg); 475 475 + ret = amdgpu_kiq_rreg(adev, reg, 0); 477 476 up_read(&adev->reset_domain->sem); 478 477 } else { 479 478 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); ··· 508 507 if (offset < adev->rmmio_size) 509 508 return (readb(adev->rmmio + offset)); 510 509 BUG(); 510 510 + } 511 511 + 512 512 + 513 513 + /** 514 514 + * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC 515 515 + * 516 516 + * @adev: amdgpu_device pointer 517 517 + * @reg: dword aligned register offset 518 518 + * @acc_flags: access flags which require special behavior 519 519 + * @xcc_id: xcc accelerated compute core id 520 520 + * 521 521 + * Returns the 32 bit value from the offset specified. 522 522 + */ 523 523 + uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 524 524 + uint32_t reg, uint32_t acc_flags, 525 525 + uint32_t xcc_id) 526 526 + { 527 527 + uint32_t ret, rlcg_flag; 528 528 + 529 529 + if (amdgpu_device_skip_hw_access(adev)) 530 530 + return 0; 531 531 + 532 532 + if ((reg * 4) < adev->rmmio_size) { 533 533 + if (amdgpu_sriov_vf(adev) && 534 534 + !amdgpu_sriov_runtime(adev) && 535 535 + adev->gfx.rlc.rlcg_reg_access_supported && 536 536 + amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, 537 537 + GC_HWIP, false, 538 538 + &rlcg_flag)) { 539 539 + ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id); 540 540 + } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && 541 541 + amdgpu_sriov_runtime(adev) && 542 542 + down_read_trylock(&adev->reset_domain->sem)) { 543 543 + ret = amdgpu_kiq_rreg(adev, reg, xcc_id); 544 544 + up_read(&adev->reset_domain->sem); 545 545 + } else { 546 546 + ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); 547 547 + } 548 548 + } else { 549 549 + ret = adev->pcie_rreg(adev, reg * 4); 550 550 + } 551 551 + 552 552 + return ret; 511 553 } 512 554 513 555 /* ··· 600 556 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && 601 557 amdgpu_sriov_runtime(adev) && 602 558 down_read_trylock(&adev->reset_domain->sem)) { 603 603 - amdgpu_kiq_wreg(adev, reg, v); 559 559 + amdgpu_kiq_wreg(adev, reg, v, 0); 604 560 up_read(&adev->reset_domain->sem); 605 561 } else { 606 562 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); ··· 638 594 adev->pcie_wreg(adev, reg * 4, v); 639 595 } else { 640 596 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); 597 597 + } 598 598 + } 599 599 + 600 600 + /** 601 601 + * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC 602 602 + * 603 603 + * @adev: amdgpu_device pointer 604 604 + * @reg: dword aligned register offset 605 605 + * @v: 32 bit value to write to the register 606 606 + * @acc_flags: access flags which require special behavior 607 607 + * @xcc_id: xcc accelerated compute core id 608 608 + * 609 609 + * Writes the value specified to the offset specified. 610 610 + */ 611 611 + void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 612 612 + uint32_t reg, uint32_t v, 613 613 + uint32_t acc_flags, uint32_t xcc_id) 614 614 + { 615 615 + uint32_t rlcg_flag; 616 616 + 617 617 + if (amdgpu_device_skip_hw_access(adev)) 618 618 + return; 619 619 + 620 620 + if ((reg * 4) < adev->rmmio_size) { 621 621 + if (amdgpu_sriov_vf(adev) && 622 622 + !amdgpu_sriov_runtime(adev) && 623 623 + adev->gfx.rlc.rlcg_reg_access_supported && 624 624 + amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, 625 625 + GC_HWIP, true, 626 626 + &rlcg_flag)) { 627 627 + amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id); 628 628 + } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && 629 629 + amdgpu_sriov_runtime(adev) && 630 630 + down_read_trylock(&adev->reset_domain->sem)) { 631 631 + amdgpu_kiq_wreg(adev, reg, v, xcc_id); 632 632 + up_read(&adev->reset_domain->sem); 633 633 + } else { 634 634 + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); 635 635 + } 636 636 + } else { 637 637 + adev->pcie_wreg(adev, reg * 4, v); 641 638 } 642 639 } 643 640 ··· 2581 2496 adev->dev); 2582 2497 if (r) { 2583 2498 DRM_ERROR("Failed to create scheduler on ring %s.\n", 2499 2499 + ring->name); 2500 2500 + return r; 2501 2501 + } 2502 2502 + r = amdgpu_uvd_entity_init(adev, ring); 2503 2503 + if (r) { 2504 2504 + DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n", 2505 2505 + ring->name); 2506 2506 + return r; 2507 2507 + } 2508 2508 + r = amdgpu_vce_entity_init(adev, ring); 2509 2509 + if (r) { 2510 2510 + DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n", 2584 2511 ring->name); 2585 2512 return r; 2586 2513 } ··· 4583 4486 } 4584 4487 amdgpu_fence_driver_hw_init(adev); 4585 4488 4586 4586 - r = amdgpu_device_ip_late_init(adev); 4587 4587 - if (r) 4588 4588 - goto exit; 4589 4589 - 4590 4590 - queue_delayed_work(system_wq, &adev->delayed_init_work, 4591 4591 - msecs_to_jiffies(AMDGPU_RESUME_MS)); 4592 4592 - 4593 4489 if (!adev->in_s0ix) { 4594 4490 r = amdgpu_amdkfd_resume(adev, adev->in_runpm); 4595 4491 if (r) 4596 4492 goto exit; 4597 4493 } 4598 4494 4495 4495 + r = amdgpu_device_ip_late_init(adev); 4496 4496 + if (r) 4497 4497 + goto exit; 4498 4498 + 4499 4499 + queue_delayed_work(system_wq, &adev->delayed_init_work, 4500 4500 + msecs_to_jiffies(AMDGPU_RESUME_MS)); 4599 4501 exit: 4600 4502 if (amdgpu_sriov_vf(adev)) { 4601 4503 amdgpu_virt_init_data_exchange(adev);

+4 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

reviewed

··· 931 931 func(adev, ras_error_status, i); 932 932 } 933 933 934 934 - uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) 934 934 + uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id) 935 935 { 936 936 signed long r, cnt = 0; 937 937 unsigned long flags; 938 938 uint32_t seq, reg_val_offs = 0, value = 0; 939 939 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 939 939 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 940 940 struct amdgpu_ring *ring = &kiq->ring; 941 941 942 942 if (amdgpu_device_skip_hw_access(adev)) ··· 999 999 return ~0; 1000 1000 } 1001 1001 1002 1002 - void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 1002 1002 + void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id) 1003 1003 { 1004 1004 signed long r, cnt = 0; 1005 1005 unsigned long flags; 1006 1006 uint32_t seq; 1007 1007 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1007 1007 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 1008 1008 struct amdgpu_ring *ring = &kiq->ring; 1009 1009 1010 1010 BUG_ON(!ring->funcs->emit_wreg);

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

reviewed

··· 521 521 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 522 522 struct amdgpu_irq_src *source, 523 523 struct amdgpu_iv_entry *entry); 524 524 - uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 525 525 - void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 524 524 + uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); 525 525 + void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); 526 526 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 527 527 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 528 528

+4 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

reviewed

··· 826 826 gc_ver == IP_VERSION(9, 4, 3) || 827 827 gc_ver >= IP_VERSION(10, 3, 0)); 828 828 829 829 - gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 829 829 + if (!amdgpu_sriov_xnack_support(adev)) 830 830 + gmc->noretry = 1; 831 831 + else 832 832 + gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 830 833 } 831 834 832 835 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,

+174 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c

reviewed

··· 143 143 return 0; 144 144 } 145 145 146 146 + void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set) 147 147 + { 148 148 + if (!mca_set) 149 149 + return; 150 150 + 151 151 + memset(mca_set, 0, sizeof(*mca_set)); 152 152 + INIT_LIST_HEAD(&mca_set->list); 153 153 + } 154 154 + 155 155 + int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry) 156 156 + { 157 157 + struct mca_bank_node *node; 158 158 + 159 159 + if (!entry) 160 160 + return -EINVAL; 161 161 + 162 162 + node = kvzalloc(sizeof(*node), GFP_KERNEL); 163 163 + if (!node) 164 164 + return -ENOMEM; 165 165 + 166 166 + memcpy(&node->entry, entry, sizeof(*entry)); 167 167 + 168 168 + INIT_LIST_HEAD(&node->node); 169 169 + list_add_tail(&node->node, &mca_set->list); 170 170 + 171 171 + mca_set->nr_entries++; 172 172 + 173 173 + return 0; 174 174 + } 175 175 + 176 176 + void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set) 177 177 + { 178 178 + struct mca_bank_node *node, *tmp; 179 179 + 180 180 + list_for_each_entry_safe(node, tmp, &mca_set->list, node) { 181 181 + list_del(&node->node); 182 182 + kvfree(node); 183 183 + } 184 184 + } 185 185 + 146 186 void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs) 147 187 { 148 188 struct amdgpu_mca *mca = &adev->mca; ··· 200 160 return -EOPNOTSUPP; 201 161 } 202 162 163 163 + static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry) 164 164 + { 165 165 + dev_info(adev->dev, "[Hardware error] Accelerator Check Architecture events logged\n"); 166 166 + dev_info(adev->dev, "[Hardware error] aca entry[%02d].STATUS=0x%016llx\n", 167 167 + idx, entry->regs[MCA_REG_IDX_STATUS]); 168 168 + dev_info(adev->dev, "[Hardware error] aca entry[%02d].ADDR=0x%016llx\n", 169 169 + idx, entry->regs[MCA_REG_IDX_ADDR]); 170 170 + dev_info(adev->dev, "[Hardware error] aca entry[%02d].MISC0=0x%016llx\n", 171 171 + idx, entry->regs[MCA_REG_IDX_MISC0]); 172 172 + dev_info(adev->dev, "[Hardware error] aca entry[%02d].IPID=0x%016llx\n", 173 173 + idx, entry->regs[MCA_REG_IDX_IPID]); 174 174 + dev_info(adev->dev, "[Hardware error] aca entry[%02d].SYND=0x%016llx\n", 175 175 + idx, entry->regs[MCA_REG_IDX_SYND]); 176 176 + } 177 177 + 178 178 + int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data) 179 179 + { 180 180 + struct amdgpu_smuio_mcm_config_info mcm_info; 181 181 + struct mca_bank_set mca_set; 182 182 + struct mca_bank_node *node; 183 183 + struct mca_bank_entry *entry; 184 184 + uint32_t count; 185 185 + int ret, i = 0; 186 186 + 187 187 + amdgpu_mca_bank_set_init(&mca_set); 188 188 + 189 189 + ret = amdgpu_mca_smu_get_mca_set(adev, blk, type, &mca_set); 190 190 + if (ret) 191 191 + goto out_mca_release; 192 192 + 193 193 + list_for_each_entry(node, &mca_set.list, node) { 194 194 + entry = &node->entry; 195 195 + 196 196 + amdgpu_mca_smu_mca_bank_dump(adev, i++, entry); 197 197 + 198 198 + count = 0; 199 199 + ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &count); 200 200 + if (ret) 201 201 + goto out_mca_release; 202 202 + 203 203 + if (!count) 204 204 + continue; 205 205 + 206 206 + mcm_info.socket_id = entry->info.socket_id; 207 207 + mcm_info.die_id = entry->info.aid; 208 208 + 209 209 + if (type == AMDGPU_MCA_ERROR_TYPE_UE) 210 210 + amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, (uint64_t)count); 211 211 + else 212 212 + amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, (uint64_t)count); 213 213 + } 214 214 + 215 215 + out_mca_release: 216 216 + amdgpu_mca_bank_set_release(&mca_set); 217 217 + 218 218 + return ret; 219 219 + } 220 220 + 221 221 + 203 222 int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count) 204 223 { 205 224 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; ··· 272 173 return -EOPNOTSUPP; 273 174 } 274 175 275 275 - int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 276 276 - enum amdgpu_mca_error_type type, uint32_t *count) 176 176 + int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 177 177 + enum amdgpu_mca_error_type type, uint32_t *total) 277 178 { 278 179 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 279 279 - if (!count) 180 180 + struct mca_bank_set mca_set; 181 181 + struct mca_bank_node *node; 182 182 + struct mca_bank_entry *entry; 183 183 + uint32_t count; 184 184 + int ret; 185 185 + 186 186 + if (!total) 280 187 return -EINVAL; 281 188 282 282 - if (mca_funcs && mca_funcs->mca_get_error_count) 283 283 - return mca_funcs->mca_get_error_count(adev, blk, type, count); 189 189 + if (!mca_funcs) 190 190 + return -EOPNOTSUPP; 284 191 285 285 - return -EOPNOTSUPP; 192 192 + if (!mca_funcs->mca_get_ras_mca_set || !mca_funcs->mca_get_valid_mca_count) 193 193 + return -EOPNOTSUPP; 194 194 + 195 195 + amdgpu_mca_bank_set_init(&mca_set); 196 196 + 197 197 + ret = mca_funcs->mca_get_ras_mca_set(adev, blk, type, &mca_set); 198 198 + if (ret) 199 199 + goto err_mca_set_release; 200 200 + 201 201 + *total = 0; 202 202 + list_for_each_entry(node, &mca_set.list, node) { 203 203 + entry = &node->entry; 204 204 + 205 205 + count = 0; 206 206 + ret = mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, &count); 207 207 + if (ret) 208 208 + goto err_mca_set_release; 209 209 + 210 210 + *total += count; 211 211 + } 212 212 + 213 213 + err_mca_set_release: 214 214 + amdgpu_mca_bank_set_release(&mca_set); 215 215 + 216 216 + return ret; 217 217 + } 218 218 + 219 219 + int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 220 220 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count) 221 221 + { 222 222 + const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 223 223 + if (!count || !entry) 224 224 + return -EINVAL; 225 225 + 226 226 + if (!mca_funcs || !mca_funcs->mca_parse_mca_error_count) 227 227 + return -EOPNOTSUPP; 228 228 + 229 229 + 230 230 + return mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, count); 231 231 + } 232 232 + 233 233 + int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 234 234 + enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set) 235 235 + { 236 236 + const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 237 237 + 238 238 + if (!mca_set) 239 239 + return -EINVAL; 240 240 + 241 241 + if (!mca_funcs || !mca_funcs->mca_get_ras_mca_set) 242 242 + return -EOPNOTSUPP; 243 243 + 244 244 + WARN_ON(!list_empty(&mca_set->list)); 245 245 + 246 246 + return mca_funcs->mca_get_ras_mca_set(adev, blk, type, mca_set); 286 247 } 287 248 288 249 int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, ··· 389 230 static void mca_dump_entry(struct seq_file *m, struct mca_bank_entry *entry) 390 231 { 391 232 int i, idx = entry->idx; 233 233 + int reg_idx_array[] = { 234 234 + MCA_REG_IDX_STATUS, 235 235 + MCA_REG_IDX_ADDR, 236 236 + MCA_REG_IDX_MISC0, 237 237 + MCA_REG_IDX_IPID, 238 238 + MCA_REG_IDX_SYND, 239 239 + }; 392 240 393 241 seq_printf(m, "mca entry[%d].type: %s\n", idx, entry->type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE"); 394 242 seq_printf(m, "mca entry[%d].ip: %d\n", idx, entry->ip); 395 243 seq_printf(m, "mca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n", 396 244 idx, entry->info.socket_id, entry->info.aid, entry->info.hwid, entry->info.mcatype); 397 245 398 398 - for (i = 0; i < ARRAY_SIZE(entry->regs); i++) 399 399 - seq_printf(m, "mca entry[%d].regs[%d]: 0x%016llx\n", idx, i, entry->regs[i]); 246 246 + for (i = 0; i < ARRAY_SIZE(reg_idx_array); i++) 247 247 + seq_printf(m, "mca entry[%d].regs[%d]: 0x%016llx\n", idx, reg_idx_array[i], entry->regs[reg_idx_array[i]]); 400 248 } 401 249 402 250 static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)

+56 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h

reviewed

··· 25 25 26 26 #define MCA_MAX_REGS_COUNT (16) 27 27 28 28 + #define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l) 29 29 + #define MCA_REG__STATUS__VAL(x) MCA_REG_FIELD(x, 63, 63) 30 30 + #define MCA_REG__STATUS__OVERFLOW(x) MCA_REG_FIELD(x, 62, 62) 31 31 + #define MCA_REG__STATUS__UC(x) MCA_REG_FIELD(x, 61, 61) 32 32 + #define MCA_REG__STATUS__EN(x) MCA_REG_FIELD(x, 60, 60) 33 33 + #define MCA_REG__STATUS__MISCV(x) MCA_REG_FIELD(x, 59, 59) 34 34 + #define MCA_REG__STATUS__ADDRV(x) MCA_REG_FIELD(x, 58, 58) 35 35 + #define MCA_REG__STATUS__PCC(x) MCA_REG_FIELD(x, 57, 57) 36 36 + #define MCA_REG__STATUS__ERRCOREIDVAL(x) MCA_REG_FIELD(x, 56, 56) 37 37 + #define MCA_REG__STATUS__TCC(x) MCA_REG_FIELD(x, 55, 55) 38 38 + #define MCA_REG__STATUS__SYNDV(x) MCA_REG_FIELD(x, 53, 53) 39 39 + #define MCA_REG__STATUS__CECC(x) MCA_REG_FIELD(x, 46, 46) 40 40 + #define MCA_REG__STATUS__UECC(x) MCA_REG_FIELD(x, 45, 45) 41 41 + #define MCA_REG__STATUS__DEFERRED(x) MCA_REG_FIELD(x, 44, 44) 42 42 + #define MCA_REG__STATUS__POISON(x) MCA_REG_FIELD(x, 43, 43) 43 43 + #define MCA_REG__STATUS__SCRUB(x) MCA_REG_FIELD(x, 40, 40) 44 44 + #define MCA_REG__STATUS__ERRCOREID(x) MCA_REG_FIELD(x, 37, 32) 45 45 + #define MCA_REG__STATUS__ADDRLSB(x) MCA_REG_FIELD(x, 29, 24) 46 46 + #define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16) 47 47 + #define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0) 48 48 + 28 49 enum amdgpu_mca_ip { 29 50 AMDGPU_MCA_IP_UNKNOW = -1, 30 51 AMDGPU_MCA_IP_PSP = 0, ··· 54 33 AMDGPU_MCA_IP_SMU, 55 34 AMDGPU_MCA_IP_MP5, 56 35 AMDGPU_MCA_IP_UMC, 36 36 + AMDGPU_MCA_IP_PCS_XGMI, 57 37 AMDGPU_MCA_IP_COUNT, 58 38 }; 59 39 ··· 79 57 const struct amdgpu_mca_smu_funcs *mca_funcs; 80 58 }; 81 59 60 60 + enum mca_reg_idx { 61 61 + MCA_REG_IDX_STATUS = 1, 62 62 + MCA_REG_IDX_ADDR = 2, 63 63 + MCA_REG_IDX_MISC0 = 3, 64 64 + MCA_REG_IDX_IPID = 5, 65 65 + MCA_REG_IDX_SYND = 6, 66 66 + MCA_REG_IDX_COUNT = 16, 67 67 + }; 68 68 + 82 69 struct mca_bank_info { 83 70 int socket_id; 84 71 int aid; ··· 103 72 uint64_t regs[MCA_MAX_REGS_COUNT]; 104 73 }; 105 74 75 75 + struct mca_bank_node { 76 76 + struct mca_bank_entry entry; 77 77 + struct list_head node; 78 78 + }; 79 79 + 80 80 + struct mca_bank_set { 81 81 + int nr_entries; 82 82 + struct list_head list; 83 83 + }; 84 84 + 106 85 struct amdgpu_mca_smu_funcs { 107 86 int max_ue_count; 108 87 int max_ce_count; 109 88 int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable); 110 110 - int (*mca_get_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 111 111 - enum amdgpu_mca_error_type type, uint32_t *count); 89 89 + int (*mca_get_ras_mca_set)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, 90 90 + struct mca_bank_set *mca_set); 91 91 + int (*mca_parse_mca_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, 92 92 + struct mca_bank_entry *entry, uint32_t *count); 112 93 int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 113 94 uint32_t *count); 114 95 int (*mca_get_mca_entry)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 115 96 int idx, struct mca_bank_entry *entry); 116 116 - int (*mca_get_ras_mca_idx_array)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 117 117 - enum amdgpu_mca_error_type type, int *idx_array, int *idx_array_size); 118 97 }; 119 98 120 99 void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, ··· 148 107 void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs); 149 108 int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable); 150 109 int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count); 110 110 + int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 111 111 + enum amdgpu_mca_error_type type, uint32_t *total); 151 112 int amdgpu_mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 152 113 enum amdgpu_mca_error_type type, uint32_t *count); 114 114 + int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 115 115 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count); 116 116 + int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 117 117 + enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set); 153 118 int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 154 119 int idx, struct mca_bank_entry *entry); 155 120 156 121 void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root); 122 122 + 123 123 + void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set); 124 124 + int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry); 125 125 + void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set); 126 126 + int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data); 157 127 158 128 #endif

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

reviewed

··· 1062 1062 */ 1063 1063 int amdgpu_bo_init(struct amdgpu_device *adev) 1064 1064 { 1065 1065 - /* set the default AGP aperture state */ 1066 1066 - amdgpu_gmc_set_agp_default(adev, &adev->gmc); 1067 1067 - 1068 1065 /* On A+A platform, VRAM can be mapped as WB */ 1069 1066 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 1070 1067 /* reserve PAT memory space to WC for VRAM */

+76 -26

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

reviewed

··· 1165 1165 } 1166 1166 } 1167 1167 1168 1168 - /* query/inject/cure begin */ 1169 1169 - int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 1170 1170 - struct ras_query_if *info) 1168 1168 + static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, 1169 1169 + struct ras_query_if *info, 1170 1170 + struct ras_err_data *err_data, 1171 1171 + unsigned int error_query_mode) 1171 1172 { 1173 1173 + enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT; 1172 1174 struct amdgpu_ras_block_object *block_obj = NULL; 1175 1175 + 1176 1176 + if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY) 1177 1177 + return -EINVAL; 1178 1178 + 1179 1179 + if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { 1180 1180 + if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { 1181 1181 + amdgpu_ras_get_ecc_info(adev, err_data); 1182 1182 + } else { 1183 1183 + block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); 1184 1184 + if (!block_obj || !block_obj->hw_ops) { 1185 1185 + dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1186 1186 + get_ras_block_str(&info->head)); 1187 1187 + return -EINVAL; 1188 1188 + } 1189 1189 + 1190 1190 + if (block_obj->hw_ops->query_ras_error_count) 1191 1191 + block_obj->hw_ops->query_ras_error_count(adev, &err_data); 1192 1192 + 1193 1193 + if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || 1194 1194 + (info->head.block == AMDGPU_RAS_BLOCK__GFX) || 1195 1195 + (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { 1196 1196 + if (block_obj->hw_ops->query_ras_error_status) 1197 1197 + block_obj->hw_ops->query_ras_error_status(adev); 1198 1198 + } 1199 1199 + } 1200 1200 + } else { 1201 1201 + /* FIXME: add code to check return value later */ 1202 1202 + amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data); 1203 1203 + amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data); 1204 1204 + } 1205 1205 + 1206 1206 + return 0; 1207 1207 + } 1208 1208 + 1209 1209 + /* query/inject/cure begin */ 1210 1210 + int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info) 1211 1211 + { 1173 1212 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); 1174 1213 struct ras_err_data err_data; 1214 1214 + unsigned int error_query_mode; 1175 1215 int ret; 1176 1216 1177 1217 if (!obj) ··· 1221 1181 if (ret) 1222 1182 return ret; 1223 1183 1224 1224 - if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { 1225 1225 - amdgpu_ras_get_ecc_info(adev, &err_data); 1226 1226 - } else { 1227 1227 - block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); 1228 1228 - if (!block_obj || !block_obj->hw_ops) { 1229 1229 - dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1230 1230 - get_ras_block_str(&info->head)); 1231 1231 - ret = -EINVAL; 1232 1232 - goto out_fini_err_data; 1233 1233 - } 1184 1184 + if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode)) 1185 1185 + return -EINVAL; 1234 1186 1235 1235 - if (block_obj->hw_ops->query_ras_error_count) 1236 1236 - block_obj->hw_ops->query_ras_error_count(adev, &err_data); 1237 1237 - 1238 1238 - if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || 1239 1239 - (info->head.block == AMDGPU_RAS_BLOCK__GFX) || 1240 1240 - (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { 1241 1241 - if (block_obj->hw_ops->query_ras_error_status) 1242 1242 - block_obj->hw_ops->query_ras_error_status(adev); 1243 1243 - } 1244 1244 - } 1187 1187 + ret = amdgpu_ras_query_error_status_helper(adev, info, 1188 1188 + &err_data, 1189 1189 + error_query_mode); 1190 1190 + if (ret) 1191 1191 + goto out_fini_err_data; 1245 1192 1246 1193 amdgpu_rasmgr_error_data_statistic_update(obj, &err_data); 1247 1194 ··· 1564 1537 { 1565 1538 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1566 1539 1567 1567 - sysfs_remove_file_from_group(&adev->dev->kobj, 1540 1540 + if (adev->dev->kobj.sd) 1541 1541 + sysfs_remove_file_from_group(&adev->dev->kobj, 1568 1542 &con->badpages_attr.attr, 1569 1543 RAS_FS_NAME); 1570 1544 } ··· 1584 1556 .attrs = attrs, 1585 1557 }; 1586 1558 1587 1587 - sysfs_remove_group(&adev->dev->kobj, &group); 1559 1559 + if (adev->dev->kobj.sd) 1560 1560 + sysfs_remove_group(&adev->dev->kobj, &group); 1588 1561 1589 1562 return 0; 1590 1563 } ··· 1632 1603 if (!obj || !obj->attr_inuse) 1633 1604 return -EINVAL; 1634 1605 1635 1635 - sysfs_remove_file_from_group(&adev->dev->kobj, 1606 1606 + if (adev->dev->kobj.sd) 1607 1607 + sysfs_remove_file_from_group(&adev->dev->kobj, 1636 1608 &obj->sysfs_attr.attr, 1637 1609 RAS_FS_NAME); 1638 1610 obj->attr_inuse = 0; ··· 3425 3395 return con->is_mca_debug_mode; 3426 3396 else 3427 3397 return true; 3398 3398 + } 3399 3399 + 3400 3400 + bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 3401 3401 + unsigned int *error_query_mode) 3402 3402 + { 3403 3403 + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3404 3404 + const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; 3405 3405 + 3406 3406 + if (!con) { 3407 3407 + *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY; 3408 3408 + return false; 3409 3409 + } 3410 3410 + 3411 3411 + if (mca_funcs && mca_funcs->mca_set_debug_mode) 3412 3412 + *error_query_mode = 3413 3413 + (con->is_mca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY; 3414 3414 + else 3415 3415 + *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY; 3416 3416 + 3417 3417 + return true; 3428 3418 } 3429 3419 3430 3420 /* Register each ip ras block into amdgpu ras */

+8

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

reviewed

··· 320 320 AMDGPU_RAS_PT, 321 321 }; 322 322 323 323 + enum amdgpu_ras_error_query_mode { 324 324 + AMDGPU_RAS_INVALID_ERROR_QUERY = 0, 325 325 + AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, 326 326 + AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, 327 327 + }; 328 328 + 323 329 /* ras error status reisger fields */ 324 330 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 325 331 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L ··· 775 769 776 770 void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable); 777 771 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev); 772 772 + bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, 773 773 + unsigned int *mode); 778 774 779 775 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 780 776 struct amdgpu_ras_block_object *ras_block_obj);

+11 -11

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

reviewed

··· 399 399 * 400 400 * @adev: amdgpu_device pointer 401 401 * 402 402 + * Initialize the entity used for handle management in the kernel driver. 402 403 */ 403 403 - int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 404 404 + int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 404 405 { 405 405 - struct amdgpu_ring *ring; 406 406 - struct drm_gpu_scheduler *sched; 407 407 - int r; 406 406 + if (ring == &adev->uvd.inst[0].ring) { 407 407 + struct drm_gpu_scheduler *sched = &ring->sched; 408 408 + int r; 408 409 409 409 - ring = &adev->uvd.inst[0].ring; 410 410 - sched = &ring->sched; 411 411 - r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 412 412 - &sched, 1, NULL); 413 413 - if (r) { 414 414 - DRM_ERROR("Failed setting up UVD kernel entity.\n"); 415 415 - return r; 410 410 + r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 411 411 + &sched, 1, NULL); 412 412 + if (r) { 413 413 + DRM_ERROR("Failed setting up UVD kernel entity.\n"); 414 414 + return r; 415 415 + } 416 416 } 417 417 418 418 return 0;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h

reviewed

··· 73 73 74 74 int amdgpu_uvd_sw_init(struct amdgpu_device *adev); 75 75 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); 76 76 - int amdgpu_uvd_entity_init(struct amdgpu_device *adev); 76 76 + int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring); 77 77 int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev); 78 78 int amdgpu_uvd_suspend(struct amdgpu_device *adev); 79 79 int amdgpu_uvd_resume(struct amdgpu_device *adev);

+11 -11

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

reviewed

··· 231 231 * 232 232 * @adev: amdgpu_device pointer 233 233 * 234 234 + * Initialize the entity used for handle management in the kernel driver. 234 235 */ 235 235 - int amdgpu_vce_entity_init(struct amdgpu_device *adev) 236 236 + int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) 236 237 { 237 237 - struct amdgpu_ring *ring; 238 238 - struct drm_gpu_scheduler *sched; 239 239 - int r; 238 238 + if (ring == &adev->vce.ring[0]) { 239 239 + struct drm_gpu_scheduler *sched = &ring->sched; 240 240 + int r; 240 241 241 241 - ring = &adev->vce.ring[0]; 242 242 - sched = &ring->sched; 243 243 - r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL, 244 244 - &sched, 1, NULL); 245 245 - if (r != 0) { 246 246 - DRM_ERROR("Failed setting up VCE run queue.\n"); 247 247 - return r; 242 242 + r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL, 243 243 + &sched, 1, NULL); 244 244 + if (r != 0) { 245 245 + DRM_ERROR("Failed setting up VCE run queue.\n"); 246 246 + return r; 247 247 + } 248 248 } 249 249 250 250 return 0;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h

reviewed

··· 55 55 56 56 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); 57 57 int amdgpu_vce_sw_fini(struct amdgpu_device *adev); 58 58 - int amdgpu_vce_entity_init(struct amdgpu_device *adev); 58 58 + int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring); 59 59 int amdgpu_vce_suspend(struct amdgpu_device *adev); 60 60 int amdgpu_vce_resume(struct amdgpu_device *adev); 61 61 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);

+15 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

reviewed

··· 73 73 74 74 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 75 75 uint32_t reg0, uint32_t reg1, 76 76 - uint32_t ref, uint32_t mask) 76 76 + uint32_t ref, uint32_t mask, 77 77 + uint32_t xcc_inst) 77 78 { 78 78 - struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 79 79 + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst]; 79 80 struct amdgpu_ring *ring = &kiq->ring; 80 81 signed long r, cnt = 0; 81 82 unsigned long flags; ··· 943 942 } 944 943 } 945 944 946 946 - static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 945 945 + bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 947 946 u32 acc_flags, u32 hwip, 948 947 bool write, u32 *rlcg_flag) 949 948 { ··· 976 975 return ret; 977 976 } 978 977 979 979 - static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 978 978 + u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) 980 979 { 981 980 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 982 981 uint32_t timeout = 50000; ··· 1093 1092 return RREG32_NO_KIQ(offset); 1094 1093 else 1095 1094 return RREG32(offset); 1095 1095 + } 1096 1096 + 1097 1097 + bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 1098 1098 + { 1099 1099 + bool xnack_mode = true; 1100 1100 + 1101 1101 + if (amdgpu_sriov_vf(adev) && adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1102 1102 + xnack_mode = false; 1103 1103 + 1104 1104 + return xnack_mode; 1096 1105 }

+7 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

reviewed

··· 334 334 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 335 335 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 336 336 uint32_t reg0, uint32_t rreg1, 337 337 - uint32_t ref, uint32_t mask); 337 337 + uint32_t ref, uint32_t mask, 338 338 + uint32_t xcc_inst); 338 339 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 339 340 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 340 341 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); ··· 366 365 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 367 366 uint32_t ucode_id); 368 367 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 368 368 + bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 369 369 + bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 370 370 + u32 acc_flags, u32 hwip, 371 371 + bool write, u32 *rlcg_flag); 372 372 + u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 369 373 #endif

+19 -18

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

reviewed

··· 1098 1098 bo = gem_to_amdgpu_bo(gobj); 1099 1099 } 1100 1100 mem = bo->tbo.resource; 1101 1101 - if (mem->mem_type == TTM_PL_TT || 1102 1102 - mem->mem_type == AMDGPU_PL_PREEMPT) 1101 1101 + if (mem && (mem->mem_type == TTM_PL_TT || 1102 1102 + mem->mem_type == AMDGPU_PL_PREEMPT)) 1103 1103 pages_addr = bo->tbo.ttm->dma_address; 1104 1104 } 1105 1105 ··· 2139 2139 * Returns: 2140 2140 * 0 for success, error for failure. 2141 2141 */ 2142 2142 - int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) 2142 2142 + int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 2143 2143 + int32_t xcp_id) 2143 2144 { 2144 2145 struct amdgpu_bo *root_bo; 2145 2146 struct amdgpu_bo_vm *root; ··· 2159 2158 INIT_LIST_HEAD(&vm->done); 2160 2159 INIT_LIST_HEAD(&vm->pt_freed); 2161 2160 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work); 2161 2161 + INIT_KFIFO(vm->faults); 2162 2162 2163 2163 r = amdgpu_vm_init_entities(adev, vm); 2164 2164 if (r) ··· 2194 2192 false, &root, xcp_id); 2195 2193 if (r) 2196 2194 goto error_free_delayed; 2197 2197 - root_bo = &root->bo; 2195 2195 + 2196 2196 + root_bo = amdgpu_bo_ref(&root->bo); 2198 2197 r = amdgpu_bo_reserve(root_bo, true); 2198 2198 + if (r) { 2199 2199 + amdgpu_bo_unref(&root->shadow); 2200 2200 + amdgpu_bo_unref(&root_bo); 2201 2201 + goto error_free_delayed; 2202 2202 + } 2203 2203 + 2204 2204 + amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); 2205 2205 + r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); 2199 2206 if (r) 2200 2207 goto error_free_root; 2201 2208 2202 2202 - r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); 2203 2203 - if (r) 2204 2204 - goto error_unreserve; 2205 2205 - 2206 2206 - amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); 2207 2207 - 2208 2209 r = amdgpu_vm_pt_clear(adev, vm, root, false); 2209 2210 if (r) 2210 2210 - goto error_unreserve; 2211 2211 + goto error_free_root; 2211 2212 2212 2213 amdgpu_bo_unreserve(vm->root.bo); 2213 2213 - 2214 2214 - INIT_KFIFO(vm->faults); 2214 2214 + amdgpu_bo_unref(&root_bo); 2215 2215 2216 2216 return 0; 2217 2217 2218 2218 - error_unreserve: 2219 2219 - amdgpu_bo_unreserve(vm->root.bo); 2220 2220 - 2221 2218 error_free_root: 2222 2222 - amdgpu_bo_unref(&root->shadow); 2219 2219 + amdgpu_vm_pt_free_root(adev, vm); 2220 2220 + amdgpu_bo_unreserve(vm->root.bo); 2223 2221 amdgpu_bo_unref(&root_bo); 2224 2224 - vm->root.bo = NULL; 2225 2222 2226 2223 error_free_delayed: 2227 2224 dma_fence_put(vm->last_tlb_flush);

+206 -12

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

reviewed

··· 103 103 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000 104 104 }; 105 105 106 106 + static const int xgmi3x16_pcs_err_status_reg_v6_4[] = { 107 107 + smnPCS_XGMI3X16_PCS_ERROR_STATUS, 108 108 + smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000 109 109 + }; 110 110 + 111 111 + static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[] = { 112 112 + smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK, 113 113 + smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000 114 114 + }; 115 115 + 116 116 + static const u64 xgmi_v6_4_0_mca_base_array[] = { 117 117 + 0x11a09200, 118 118 + 0x11b09200, 119 119 + }; 120 120 + 121 121 + static const char *xgmi_v6_4_0_ras_error_code_ext[32] = { 122 122 + [0x00] = "XGMI PCS DataLossErr", 123 123 + [0x01] = "XGMI PCS TrainingErr", 124 124 + [0x02] = "XGMI PCS FlowCtrlAckErr", 125 125 + [0x03] = "XGMI PCS RxFifoUnderflowErr", 126 126 + [0x04] = "XGMI PCS RxFifoOverflowErr", 127 127 + [0x05] = "XGMI PCS CRCErr", 128 128 + [0x06] = "XGMI PCS BERExceededErr", 129 129 + [0x07] = "XGMI PCS TxMetaDataErr", 130 130 + [0x08] = "XGMI PCS ReplayBufParityErr", 131 131 + [0x09] = "XGMI PCS DataParityErr", 132 132 + [0x0a] = "XGMI PCS ReplayFifoOverflowErr", 133 133 + [0x0b] = "XGMI PCS ReplayFifoUnderflowErr", 134 134 + [0x0c] = "XGMI PCS ElasticFifoOverflowErr", 135 135 + [0x0d] = "XGMI PCS DeskewErr", 136 136 + [0x0e] = "XGMI PCS FlowCtrlCRCErr", 137 137 + [0x0f] = "XGMI PCS DataStartupLimitErr", 138 138 + [0x10] = "XGMI PCS FCInitTimeoutErr", 139 139 + [0x11] = "XGMI PCS RecoveryTimeoutErr", 140 140 + [0x12] = "XGMI PCS ReadySerialTimeoutErr", 141 141 + [0x13] = "XGMI PCS ReadySerialAttemptErr", 142 142 + [0x14] = "XGMI PCS RecoveryAttemptErr", 143 143 + [0x15] = "XGMI PCS RecoveryRelockAttemptErr", 144 144 + [0x16] = "XGMI PCS ReplayAttemptErr", 145 145 + [0x17] = "XGMI PCS SyncHdrErr", 146 146 + [0x18] = "XGMI PCS TxReplayTimeoutErr", 147 147 + [0x19] = "XGMI PCS RxReplayTimeoutErr", 148 148 + [0x1a] = "XGMI PCS LinkSubTxTimeoutErr", 149 149 + [0x1b] = "XGMI PCS LinkSubRxTimeoutErr", 150 150 + [0x1c] = "XGMI PCS RxCMDPktErr", 151 151 + }; 152 152 + 106 153 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 107 154 {"XGMI PCS DataLossErr", 108 155 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, ··· 973 926 WREG32_PCIE(pcs_status_reg, 0); 974 927 } 975 928 976 976 - static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 929 929 + static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev) 977 930 { 978 931 uint32_t i; 979 932 ··· 999 952 default: 1000 953 break; 1001 954 } 955 955 + 956 956 + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 957 957 + case IP_VERSION(6, 4, 0): 958 958 + for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) 959 959 + pcs_clear_status(adev, 960 960 + xgmi3x16_pcs_err_status_reg_v6_4[i]); 961 961 + break; 962 962 + default: 963 963 + break; 964 964 + } 965 965 + } 966 966 + 967 967 + static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base) 968 968 + { 969 969 + WREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS, 0ULL); 970 970 + } 971 971 + 972 972 + static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst) 973 973 + { 974 974 + int i; 975 975 + 976 976 + for (i = 0; i < ARRAY_SIZE(xgmi_v6_4_0_mca_base_array); i++) 977 977 + __xgmi_v6_4_0_reset_error_count(adev, xgmi_inst, xgmi_v6_4_0_mca_base_array[i]); 978 978 + } 979 979 + 980 980 + static void xgmi_v6_4_0_reset_ras_error_count(struct amdgpu_device *adev) 981 981 + { 982 982 + int i; 983 983 + 984 984 + for_each_inst(i, adev->aid_mask) 985 985 + xgmi_v6_4_0_reset_error_count(adev, i); 986 986 + } 987 987 + 988 988 + static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 989 989 + { 990 990 + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 991 991 + case IP_VERSION(6, 4, 0): 992 992 + xgmi_v6_4_0_reset_ras_error_count(adev); 993 993 + break; 994 994 + default: 995 995 + amdgpu_xgmi_legacy_reset_ras_error_count(adev); 996 996 + break; 997 997 + } 1002 998 } 1003 999 1004 1000 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, ··· 1059 969 1060 970 if (is_xgmi_pcs) { 1061 971 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == 1062 1062 - IP_VERSION(6, 1, 0)) { 972 972 + IP_VERSION(6, 1, 0) || 973 973 + amdgpu_ip_version(adev, XGMI_HWIP, 0) == 974 974 + IP_VERSION(6, 4, 0)) { 1063 975 pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0]; 1064 976 field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields); 1065 977 } else { ··· 1095 1003 return 0; 1096 1004 } 1097 1005 1098 1098 - static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 1099 1099 - void *ras_error_status) 1006 1006 + static void amdgpu_xgmi_legacy_query_ras_error_count(struct amdgpu_device *adev, 1007 1007 + void *ras_error_status) 1100 1008 { 1101 1009 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1102 1102 - int i; 1010 1010 + int i, supported = 1; 1103 1011 uint32_t data, mask_data = 0; 1104 1012 uint32_t ue_cnt = 0, ce_cnt = 0; 1105 1013 ··· 1163 1071 } 1164 1072 break; 1165 1073 default: 1166 1166 - dev_warn(adev->dev, "XGMI RAS error query not supported"); 1074 1074 + supported = 0; 1075 1075 + break; 1076 1076 + } 1077 1077 + 1078 1078 + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1079 1079 + case IP_VERSION(6, 4, 0): 1080 1080 + /* check xgmi3x16 pcs error */ 1081 1081 + for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_v6_4); i++) { 1082 1082 + data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]); 1083 1083 + mask_data = 1084 1084 + RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[i]); 1085 1085 + if (data) 1086 1086 + amdgpu_xgmi_query_pcs_error_status(adev, data, 1087 1087 + mask_data, &ue_cnt, &ce_cnt, true, true); 1088 1088 + } 1089 1089 + break; 1090 1090 + default: 1091 1091 + if (!supported) 1092 1092 + dev_warn(adev->dev, "XGMI RAS error query not supported"); 1167 1093 break; 1168 1094 } 1169 1095 ··· 1191 1081 err_data->ce_count += ce_cnt; 1192 1082 } 1193 1083 1084 1084 + static enum amdgpu_mca_error_type xgmi_v6_4_0_pcs_mca_get_error_type(struct amdgpu_device *adev, u64 status) 1085 1085 + { 1086 1086 + const char *error_str; 1087 1087 + int ext_error_code; 1088 1088 + 1089 1089 + ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status); 1090 1090 + 1091 1091 + error_str = ext_error_code < ARRAY_SIZE(xgmi_v6_4_0_ras_error_code_ext) ? 1092 1092 + xgmi_v6_4_0_ras_error_code_ext[ext_error_code] : NULL; 1093 1093 + if (error_str) 1094 1094 + dev_info(adev->dev, "%s detected\n", error_str); 1095 1095 + 1096 1096 + switch (ext_error_code) { 1097 1097 + case 0: 1098 1098 + return AMDGPU_MCA_ERROR_TYPE_UE; 1099 1099 + case 6: 1100 1100 + return AMDGPU_MCA_ERROR_TYPE_CE; 1101 1101 + default: 1102 1102 + return -EINVAL; 1103 1103 + } 1104 1104 + 1105 1105 + return -EINVAL; 1106 1106 + } 1107 1107 + 1108 1108 + static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct amdgpu_smuio_mcm_config_info *mcm_info, 1109 1109 + u64 mca_base, struct ras_err_data *err_data) 1110 1110 + { 1111 1111 + int xgmi_inst = mcm_info->die_id; 1112 1112 + u64 status = 0; 1113 1113 + 1114 1114 + status = RREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS); 1115 1115 + if (!MCA_REG__STATUS__VAL(status)) 1116 1116 + return; 1117 1117 + 1118 1118 + switch (xgmi_v6_4_0_pcs_mca_get_error_type(adev, status)) { 1119 1119 + case AMDGPU_MCA_ERROR_TYPE_UE: 1120 1120 + amdgpu_ras_error_statistic_ue_count(err_data, mcm_info, 1ULL); 1121 1121 + break; 1122 1122 + case AMDGPU_MCA_ERROR_TYPE_CE: 1123 1123 + amdgpu_ras_error_statistic_ce_count(err_data, mcm_info, 1ULL); 1124 1124 + break; 1125 1125 + default: 1126 1126 + break; 1127 1127 + } 1128 1128 + 1129 1129 + WREG64_MCA(xgmi_inst, mca_base, MCA_REG_IDX_STATUS, 0ULL); 1130 1130 + } 1131 1131 + 1132 1132 + static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data) 1133 1133 + { 1134 1134 + struct amdgpu_smuio_mcm_config_info mcm_info = { 1135 1135 + .socket_id = adev->smuio.funcs->get_socket_id(adev), 1136 1136 + .die_id = xgmi_inst, 1137 1137 + }; 1138 1138 + int i; 1139 1139 + 1140 1140 + for (i = 0; i < ARRAY_SIZE(xgmi_v6_4_0_mca_base_array); i++) 1141 1141 + __xgmi_v6_4_0_query_error_count(adev, &mcm_info, xgmi_v6_4_0_mca_base_array[i], err_data); 1142 1142 + } 1143 1143 + 1144 1144 + static void xgmi_v6_4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) 1145 1145 + { 1146 1146 + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1147 1147 + int i; 1148 1148 + 1149 1149 + for_each_inst(i, adev->aid_mask) 1150 1150 + xgmi_v6_4_0_query_error_count(adev, i, err_data); 1151 1151 + } 1152 1152 + 1153 1153 + static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 1154 1154 + void *ras_error_status) 1155 1155 + { 1156 1156 + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { 1157 1157 + case IP_VERSION(6, 4, 0): 1158 1158 + xgmi_v6_4_0_query_ras_error_count(adev, ras_error_status); 1159 1159 + break; 1160 1160 + default: 1161 1161 + amdgpu_xgmi_legacy_query_ras_error_count(adev, ras_error_status); 1162 1162 + break; 1163 1163 + } 1164 1164 + } 1165 1165 + 1194 1166 /* Trigger XGMI/WAFL error */ 1195 1167 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, 1196 1168 void *inject_if, uint32_t instance_mask) 1197 1169 { 1198 1198 - int ret = 0; 1170 1170 + int ret1, ret2; 1199 1171 struct ta_ras_trigger_error_input *block_info = 1200 1172 (struct ta_ras_trigger_error_input *)inject_if; 1201 1173 1202 1174 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) 1203 1175 dev_warn(adev->dev, "Failed to disallow df cstate"); 1204 1176 1205 1205 - if (amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DISALLOW)) 1177 1177 + ret1 = amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DISALLOW); 1178 1178 + if (ret1 && ret1 != -EOPNOTSUPP) 1206 1179 dev_warn(adev->dev, "Failed to disallow XGMI power down"); 1207 1180 1208 1208 - ret = psp_ras_trigger_error(&adev->psp, block_info, instance_mask); 1181 1181 + ret2 = psp_ras_trigger_error(&adev->psp, block_info, instance_mask); 1209 1182 1210 1183 if (amdgpu_ras_intr_triggered()) 1211 1211 - return ret; 1184 1184 + return ret2; 1212 1185 1213 1213 - if (amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DEFAULT)) 1186 1186 + ret1 = amdgpu_dpm_set_xgmi_plpd_mode(adev, XGMI_PLPD_DEFAULT); 1187 1187 + if (ret1 && ret1 != -EOPNOTSUPP) 1214 1188 dev_warn(adev->dev, "Failed to allow XGMI power down"); 1215 1189 1216 1190 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) 1217 1191 dev_warn(adev->dev, "Failed to allow df cstate"); 1218 1192 1219 1219 - return ret; 1193 1193 + return ret2; 1220 1194 } 1221 1195 1222 1196 struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = {

+44 -5

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

reviewed

··· 1102 1102 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1103 1103 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1104 1104 } 1105 1105 + adev->gfx.rlc.rlcg_reg_access_supported = true; 1105 1106 } 1106 1107 1107 1108 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) ··· 2739 2738 2740 2739 switch (state) { 2741 2740 case AMDGPU_IRQ_STATE_DISABLE: 2742 2742 - mec_int_cntl = RREG32(mec_int_cntl_reg); 2741 2741 + mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2743 2742 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2744 2743 TIME_STAMP_INT_ENABLE, 0); 2745 2745 - WREG32(mec_int_cntl_reg, mec_int_cntl); 2744 2744 + WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2746 2745 break; 2747 2746 case AMDGPU_IRQ_STATE_ENABLE: 2748 2748 - mec_int_cntl = RREG32(mec_int_cntl_reg); 2747 2747 + mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2749 2748 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2750 2749 TIME_STAMP_INT_ENABLE, 1); 2751 2751 - WREG32(mec_int_cntl_reg, mec_int_cntl); 2750 2750 + WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2752 2751 break; 2753 2752 default: 2754 2753 break; ··· 3800 3799 } 3801 3800 } 3802 3801 3802 3802 + /* handle extra register entries of UE */ 3803 3803 + for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3804 3804 + for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3805 3805 + for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3806 3806 + /* no need to select if instance number is 1 */ 3807 3807 + if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3808 3808 + gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3809 3809 + gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3810 3810 + 3811 3811 + amdgpu_ras_inst_query_ras_error_count(adev, 3812 3812 + &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3813 3813 + 1, 3814 3814 + gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3815 3815 + gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3816 3816 + GET_INST(GC, xcc_id), 3817 3817 + AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3818 3818 + &ue_count); 3819 3819 + } 3820 3820 + } 3821 3821 + } 3822 3822 + 3803 3823 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3804 3824 xcc_id); 3805 3825 mutex_unlock(&adev->grbm_idx_mutex); ··· 3851 3829 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3852 3830 1, 3853 3831 GET_INST(GC, xcc_id)); 3832 3832 + 3833 3833 + amdgpu_ras_inst_reset_ras_error_count(adev, 3834 3834 + &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3835 3835 + 1, 3836 3836 + GET_INST(GC, xcc_id)); 3837 3837 + } 3838 3838 + } 3839 3839 + } 3840 3840 + 3841 3841 + /* handle extra register entries of UE */ 3842 3842 + for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3843 3843 + for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3844 3844 + for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3845 3845 + /* no need to select if instance number is 1 */ 3846 3846 + if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3847 3847 + gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3848 3848 + gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3854 3849 3855 3850 amdgpu_ras_inst_reset_ras_error_count(adev, 3856 3851 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), ··· 4339 4300 .type = AMD_IP_BLOCK_TYPE_GFX, 4340 4301 .major = 9, 4341 4302 .minor = 4, 4342 4342 - .rev = 0, 4303 4303 + .rev = 3, 4343 4304 .funcs = &gfx_v9_4_3_ip_funcs, 4344 4305 }; 4345 4306

+2 -1

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

reviewed

··· 268 268 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 269 269 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 270 270 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 271 271 - 1 << vmid); 271 271 + 1 << vmid, GET_INST(GC, 0)); 272 272 return; 273 273 } 274 274 ··· 672 672 /* add the xgmi offset of the physical node */ 673 673 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 674 674 675 675 + amdgpu_gmc_set_agp_default(adev, mc); 675 676 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 676 677 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 677 678 if (!amdgpu_sriov_vf(adev))

+2 -1

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

reviewed

··· 229 229 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 230 230 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 231 231 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 232 232 - 1 << vmid); 232 232 + 1 << vmid, GET_INST(GC, 0)); 233 233 return; 234 234 } 235 235 ··· 637 637 638 638 base = adev->mmhub.funcs->get_fb_location(adev); 639 639 640 640 + amdgpu_gmc_set_agp_default(adev, mc); 640 641 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 641 642 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); 642 643 if (!amdgpu_sriov_vf(adev) ||

+1

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

reviewed

··· 211 211 212 212 base <<= 24; 213 213 214 214 + amdgpu_gmc_set_agp_default(adev, mc); 214 215 amdgpu_gmc_vram_location(adev, mc, base); 215 216 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 216 217 }

+1

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

reviewed

··· 239 239 240 240 base <<= 24; 241 241 242 242 + amdgpu_gmc_set_agp_default(adev, mc); 242 243 amdgpu_gmc_vram_location(adev, mc, base); 243 244 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 244 245 }

+1

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

reviewed

··· 413 413 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 414 414 base <<= 24; 415 415 416 416 + amdgpu_gmc_set_agp_default(adev, mc); 416 417 amdgpu_gmc_vram_location(adev, mc, base); 417 418 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 418 419 }

+22 -13

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

reviewed

··· 817 817 uint32_t vmhub, uint32_t flush_type) 818 818 { 819 819 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 820 820 - u32 j, inv_req, tmp, sem, req, ack; 820 820 + u32 j, inv_req, tmp, sem, req, ack, inst; 821 821 const unsigned int eng = 17; 822 822 struct amdgpu_vmhub *hub; 823 823 ··· 832 832 /* This is necessary for a HW workaround under SRIOV as well 833 833 * as GFXOFF under bare metal 834 834 */ 835 835 - if (adev->gfx.kiq[0].ring.sched.ready && 835 835 + if (vmhub >= AMDGPU_MMHUB0(0)) 836 836 + inst = GET_INST(GC, 0); 837 837 + else 838 838 + inst = vmhub; 839 839 + if (adev->gfx.kiq[inst].ring.sched.ready && 836 840 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 837 841 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 838 842 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 839 843 840 844 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 841 841 - 1 << vmid); 845 845 + 1 << vmid, inst); 842 846 return; 843 847 } 844 848 ··· 860 856 for (j = 0; j < adev->usec_timeout; j++) { 861 857 /* a read return value of 1 means semaphore acquire */ 862 858 if (vmhub >= AMDGPU_MMHUB0(0)) 863 863 - tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem); 859 859 + tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst); 864 860 else 865 865 - tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem); 861 861 + tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst); 866 862 if (tmp & 0x1) 867 863 break; 868 864 udelay(1); ··· 873 869 } 874 870 875 871 if (vmhub >= AMDGPU_MMHUB0(0)) 876 876 - WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req); 872 872 + WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst); 877 873 else 878 878 - WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req); 874 874 + WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst); 879 875 880 876 /* 881 877 * Issue a dummy read to wait for the ACK register to ··· 888 884 889 885 for (j = 0; j < adev->usec_timeout; j++) { 890 886 if (vmhub >= AMDGPU_MMHUB0(0)) 891 891 - tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack); 887 887 + tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst); 892 888 else 893 893 - tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack); 889 889 + tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst); 894 890 if (tmp & (1 << vmid)) 895 891 break; 896 892 udelay(1); ··· 903 899 * write with 0 means semaphore release 904 900 */ 905 901 if (vmhub >= AMDGPU_MMHUB0(0)) 906 906 - WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0); 902 902 + WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst); 907 903 else 908 908 - WREG32_SOC15_IP_NO_KIQ(GC, sem, 0); 904 904 + WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst); 909 905 } 910 906 911 907 spin_unlock(&adev->gmc.invalidate_lock); ··· 1180 1176 if (uncached) { 1181 1177 mtype = MTYPE_UC; 1182 1178 } else if (ext_coherent) { 1183 1183 - mtype = is_local ? MTYPE_CC : MTYPE_UC; 1179 1179 + if (adev->rev_id) 1180 1180 + mtype = is_local ? MTYPE_CC : MTYPE_UC; 1181 1181 + else 1182 1182 + mtype = MTYPE_UC; 1184 1183 } else if (adev->flags & AMD_IS_APU) { 1185 1184 mtype = is_local ? mtype_local : MTYPE_NC; 1186 1185 } else { ··· 1304 1297 1305 1298 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1306 1299 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1307 1307 - } else { 1300 1300 + } else if (adev->rev_id) { 1308 1301 /* MTYPE_UC case */ 1309 1302 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1310 1303 AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); ··· 1620 1613 struct amdgpu_gmc *mc) 1621 1614 { 1622 1615 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1616 1616 + 1617 1617 + amdgpu_gmc_set_agp_default(adev, mc); 1623 1618 1624 1619 /* add the xgmi offset of the physical node */ 1625 1620 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;

+4

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

reviewed

··· 145 145 break; 146 146 } 147 147 148 148 + /* Do not program registers if VF */ 149 149 + if (amdgpu_sriov_vf(adev)) 150 150 + return; 151 151 + 148 152 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 149 153 150 154 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0))

+10 -6

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

reviewed

··· 654 654 */ 655 655 static void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 656 656 { 657 657 - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 658 658 - 0, 0, PACKETJ_TYPE0)); 659 659 - amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 657 657 + if (!amdgpu_sriov_vf(ring->adev)) { 658 658 + amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 659 659 + 0, 0, PACKETJ_TYPE0)); 660 660 + amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 661 661 + } 660 662 661 663 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 662 664 0, 0, PACKETJ_TYPE0)); ··· 674 672 */ 675 673 static void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 676 674 { 677 677 - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 678 678 - 0, 0, PACKETJ_TYPE0)); 679 679 - amdgpu_ring_write(ring, 0x62a04); 675 675 + if (!amdgpu_sriov_vf(ring->adev)) { 676 676 + amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 677 677 + 0, 0, PACKETJ_TYPE0)); 678 678 + amdgpu_ring_write(ring, 0x62a04); 679 679 + } 680 680 681 681 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 682 682 0, 0, PACKETJ_TYPE0));

+20 -7

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

reviewed

··· 427 427 uint32_t inst_mask) 428 428 { 429 429 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES]; 430 430 + u32 doorbell_offset, doorbell; 430 431 u32 rb_cntl, ib_cntl; 431 432 int i, unset = 0; 432 433 ··· 445 444 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL); 446 445 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0); 447 446 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl); 447 447 + 448 448 + if (sdma[i]->use_doorbell) { 449 449 + doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 450 450 + doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); 451 451 + 452 452 + doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0); 453 453 + doorbell_offset = REG_SET_FIELD(doorbell_offset, 454 454 + SDMA_GFX_DOORBELL_OFFSET, 455 455 + OFFSET, 0); 456 456 + WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell); 457 457 + WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset); 458 458 + } 448 459 } 449 460 } 450 461 ··· 644 631 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); 645 632 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); 646 633 647 647 - /* Initialize the ring buffer's read and write pointers */ 648 648 - WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 649 649 - WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 650 650 - WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 651 651 - WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 652 652 - 653 634 /* set the wb address whether it's enabled or not */ 654 635 WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI, 655 636 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); ··· 660 653 661 654 /* before programing wptr to a less value, need set minor_ptr_update first */ 662 655 WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1); 656 656 + 657 657 + /* Initialize the ring buffer's read and write pointers */ 658 658 + WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0); 659 659 + WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0); 660 660 + WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0); 661 661 + WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0); 663 662 664 663 doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL); 665 664 doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET); ··· 2061 2048 .type = AMD_IP_BLOCK_TYPE_SDMA, 2062 2049 .major = 4, 2063 2050 .minor = 4, 2064 2064 - .rev = 0, 2051 2051 + .rev = 2, 2065 2052 .funcs = &sdma_v4_4_2_ip_funcs, 2066 2053 }; 2067 2054

+10 -4

drivers/gpu/drm/amd/amdgpu/soc15_common.h

reviewed

··· 69 69 70 70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) 71 71 72 72 - #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0) 72 72 + #define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst) 73 73 74 74 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ 75 75 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ ··· 86 86 #define WREG32_SOC15_IP(ip, reg, value) \ 87 87 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0) 88 88 89 89 - #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \ 90 90 - __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0) 89 89 + #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \ 90 90 + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst) 91 91 92 92 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ 93 93 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ ··· 140 140 141 141 /* for GC only */ 142 142 #define RREG32_RLC(reg) \ 143 143 - __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP) 143 143 + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0) 144 144 145 145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ 146 146 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0) ··· 203 203 WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ 204 204 + adev->asic_funcs->encode_ext_smn_addressing(ext), \ 205 205 value) \ 206 206 + 207 207 + #define RREG64_MCA(ext, mca_base, idx) \ 208 208 + RREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8)) 209 209 + 210 210 + #define WREG64_MCA(ext, mca_base, idx, val) \ 211 211 + WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val) 206 212 207 213 #endif

+1

drivers/gpu/drm/amd/amdgpu/soc21.c

reviewed

··· 381 381 return AMD_RESET_METHOD_MODE1; 382 382 case IP_VERSION(13, 0, 4): 383 383 case IP_VERSION(13, 0, 11): 384 384 + case IP_VERSION(14, 0, 0): 384 385 return AMD_RESET_METHOD_MODE2; 385 386 default: 386 387 if (amdgpu_dpm_is_baco_supported(adev))

+2 -2

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

reviewed

··· 88 88 umc_v12_0_reset_error_count_per_channel, NULL); 89 89 } 90 90 91 91 - static bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status) 91 91 + bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status) 92 92 { 93 93 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 94 94 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || ··· 96 96 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 97 97 } 98 98 99 99 - static bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status) 99 99 + bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status) 100 100 { 101 101 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 102 102 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 ||

+3

drivers/gpu/drm/amd/amdgpu/umc_v12_0.h

reviewed

··· 117 117 (pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) << UMC_V12_0_PA_CH6_BIT); \ 118 118 } while (0) 119 119 120 120 + bool umc_v12_0_is_uncorrectable_error(uint64_t mc_umc_status); 121 121 + bool umc_v12_0_is_correctable_error(uint64_t mc_umc_status); 122 122 + 120 123 extern const uint32_t 121 124 umc_v12_0_channel_idx_tbl[] 122 125 [UMC_V12_0_UMC_INSTANCE_NUM]

-2

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

reviewed

··· 577 577 ptr += ucode_len; 578 578 memcpy(&adev->uvd.keyselect, ptr, 4); 579 579 580 580 - r = amdgpu_uvd_entity_init(adev); 581 581 - 582 580 return r; 583 581 } 584 582

-2

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

reviewed

··· 127 127 if (r) 128 128 return r; 129 129 130 130 - r = amdgpu_uvd_entity_init(adev); 131 131 - 132 130 return r; 133 131 } 134 132

-2

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

reviewed

··· 125 125 if (r) 126 126 return r; 127 127 128 128 - r = amdgpu_uvd_entity_init(adev); 129 129 - 130 128 return r; 131 129 } 132 130

-2

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

reviewed

··· 432 432 } 433 433 } 434 434 435 435 - r = amdgpu_uvd_entity_init(adev); 436 436 - 437 435 return r; 438 436 } 439 437

-4

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

reviewed

··· 480 480 if (r) 481 481 return r; 482 482 483 483 - r = amdgpu_uvd_entity_init(adev); 484 484 - if (r) 485 485 - return r; 486 486 - 487 483 r = amdgpu_virt_alloc_mm_table(adev); 488 484 if (r) 489 485 return r;

-2

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

reviewed

··· 441 441 return r; 442 442 } 443 443 444 444 - r = amdgpu_vce_entity_init(adev); 445 445 - 446 444 return r; 447 445 } 448 446

-2

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

reviewed

··· 450 450 return r; 451 451 } 452 452 453 453 - r = amdgpu_vce_entity_init(adev); 454 454 - 455 453 return r; 456 454 } 457 455

-5

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

reviewed

··· 486 486 return r; 487 487 } 488 488 489 489 - 490 490 - r = amdgpu_vce_entity_init(adev); 491 491 - if (r) 492 492 - return r; 493 493 - 494 489 r = amdgpu_virt_alloc_mm_table(adev); 495 490 if (r) 496 491 return r;

+6 -1

drivers/gpu/drm/amd/amdkfd/kfd_process.c

reviewed

··· 1416 1416 * per-process XNACK mode selection. But let the dev->noretry 1417 1417 * setting still influence the default XNACK mode. 1418 1418 */ 1419 1419 - if (supported && KFD_SUPPORT_XNACK_PER_PROCESS(dev)) 1419 1419 + if (supported && KFD_SUPPORT_XNACK_PER_PROCESS(dev)) { 1420 1420 + if (!amdgpu_sriov_xnack_support(dev->kfd->adev)) { 1421 1421 + pr_debug("SRIOV platform xnack not supported\n"); 1422 1422 + return false; 1423 1423 + } 1420 1424 continue; 1425 1425 + } 1421 1426 1422 1427 /* GFXv10 and later GPUs do not support shader preemption 1423 1428 * during page faults. This can lead to poor QoS for queue

+5 -3

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

reviewed

··· 1255 1255 } 1256 1256 break; 1257 1257 case IP_VERSION(9, 4, 3): 1258 1258 - mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : 1259 1259 - (amdgpu_mtype_local == 2 || ext_coherent ? 1260 1260 - AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW); 1258 1258 + if (ext_coherent) 1259 1259 + mtype_local = node->adev->rev_id ? AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_UC; 1260 1260 + else 1261 1261 + mtype_local = amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : 1262 1262 + amdgpu_mtype_local == 2 ? AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW; 1261 1263 snoop = true; 1262 1264 if (uncached) { 1263 1265 mapping_flags |= AMDGPU_VM_MTYPE_UC;

+3

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

reviewed

··· 1216 1216 1217 1217 } 1218 1218 1219 1219 + pipe_ctx->stream->test_pattern.type = test_pattern; 1220 1220 + pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space; 1221 1221 + 1219 1222 dc_link_dp_set_test_pattern( 1220 1223 (struct dc_link *) link, 1221 1224 test_pattern,

+1 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h

reviewed

··· 37 37 #include <drm/drm_framebuffer.h> 38 38 #include <drm/drm_encoder.h> 39 39 #include <drm/drm_atomic.h> 40 40 - #include "dcn10/dcn10_optc.h" 40 40 + #include "dc/inc/hw/optc.h" 41 41 42 42 #include "dc/inc/core_types.h" 43 43

+13 -8

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

reviewed

··· 111 111 return display_count; 112 112 } 113 113 114 114 - static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) 114 114 + static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, 115 115 + bool safe_to_lower, bool disable) 115 116 { 116 117 struct dc *dc = clk_mgr_base->ctx->dc; 117 118 int i; 118 119 119 120 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 120 120 - struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 121 121 + struct pipe_ctx *pipe = safe_to_lower 122 122 + ? &context->res_ctx.pipe_ctx[i] 123 123 + : &dc->current_state->res_ctx.pipe_ctx[i]; 121 124 122 125 if (pipe->top_pipe || pipe->prev_odm_pipe) 123 126 continue; 124 124 - if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { 127 127 + if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || 128 128 + !pipe->stream->link_enc)) { 125 129 struct stream_encoder *stream_enc = pipe->stream_res.stream_enc; 126 130 127 131 if (disable) { ··· 305 301 } 306 302 307 303 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 308 308 - dcn35_disable_otg_wa(clk_mgr_base, context, true); 304 304 + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); 309 305 310 306 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 311 307 dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 312 312 - dcn35_disable_otg_wa(clk_mgr_base, context, false); 308 308 + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); 313 309 314 310 update_dispclk = true; 315 311 } ··· 818 814 struct dc *dc = clk_mgr_base->ctx->dc; 819 815 uint32_t val = dcn35_smu_read_ips_scratch(clk_mgr); 820 816 821 821 - if (dc->config.disable_ips == 0) { 817 817 + if (dc->config.disable_ips == DMUB_IPS_ENABLE || 818 818 + dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) { 822 819 val |= DMUB_IPS1_ALLOW_MASK; 823 820 val |= DMUB_IPS2_ALLOW_MASK; 824 821 } else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) { ··· 1119 1114 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 1120 1115 smu_dpm_clks.dpm_clks); 1121 1116 1122 1122 - if (ctx->dc->config.disable_ips == 0) { 1117 1117 + if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) { 1123 1118 bool ips_support = false; 1124 1119 1125 1120 /*avoid call pmfw at init*/ ··· 1132 1127 ctx->dc->debug.disable_hpo_power_gate = false; 1133 1128 } else { 1134 1129 /*let's reset the config control flag*/ 1135 1135 - ctx->dc->config.disable_ips = 1; /*pmfw not support it, disable it all*/ 1130 1130 + ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/ 1136 1131 } 1137 1132 } 1138 1133 }

+25 -2

drivers/gpu/drm/amd/display/dc/core/dc.c

reviewed

··· 2582 2582 if (u->gamut_remap_matrix) 2583 2583 update_flags->bits.gamut_remap_change = 1; 2584 2584 2585 2585 + if (u->blend_tf) 2586 2586 + update_flags->bits.gamma_change = 1; 2587 2587 + 2585 2588 if (u->gamma) { 2586 2589 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN; 2587 2590 ··· 4116 4113 bool success = false; 4117 4114 struct dc_state *minimal_transition_context; 4118 4115 struct pipe_split_policy_backup policy; 4116 4116 + struct mall_temp_config mall_temp_config; 4119 4117 4120 4118 /* commit based on new context */ 4119 4119 + /* Since all phantom pipes are removed in full validation, 4120 4120 + * we have to save and restore the subvp/mall config when 4121 4121 + * we do a minimal transition since the flags marking the 4122 4122 + * pipe as subvp/phantom will be cleared (dc copy constructor 4123 4123 + * creates a shallow copy). 4124 4124 + */ 4125 4125 + if (dc->res_pool->funcs->save_mall_state) 4126 4126 + dc->res_pool->funcs->save_mall_state(dc, context, &mall_temp_config); 4121 4127 minimal_transition_context = create_minimal_transition_state(dc, 4122 4128 context, &policy); 4123 4129 if (minimal_transition_context) { ··· 4135 4123 dc->hwss.is_pipe_topology_transition_seamless( 4136 4124 dc, minimal_transition_context, context)) { 4137 4125 DC_LOG_DC("%s base = new state\n", __func__); 4126 4126 + 4138 4127 success = dc_commit_state_no_check(dc, minimal_transition_context) == DC_OK; 4139 4128 } 4140 4129 release_minimal_transition_state(dc, minimal_transition_context, &policy); 4130 4130 + if (dc->res_pool->funcs->restore_mall_state) 4131 4131 + dc->res_pool->funcs->restore_mall_state(dc, context, &mall_temp_config); 4132 4132 + /* If we do a minimal transition with plane removal and the context 4133 4133 + * has subvp we also have to retain back the phantom stream / planes 4134 4134 + * since the refcount is decremented as part of the min transition 4135 4135 + * (we commit a state with no subvp, so the phantom streams / planes 4136 4136 + * had to be removed). 4137 4137 + */ 4138 4138 + if (dc->res_pool->funcs->retain_phantom_pipes) 4139 4139 + dc->res_pool->funcs->retain_phantom_pipes(dc, context); 4141 4140 } 4142 4141 4143 4142 if (!success) { ··· 4907 4884 if (dc->debug.disable_idle_power_optimizations) 4908 4885 return; 4909 4886 4910 4910 - if (dc->caps.ips_support && dc->config.disable_ips) 4887 4887 + if (dc->caps.ips_support && (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL)) 4911 4888 return; 4912 4889 4913 4890 if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present) ··· 4928 4905 if (dc->debug.disable_idle_power_optimizations) 4929 4906 return false; 4930 4907 4931 4931 - if (!dc->caps.ips_support || dc->config.disable_ips) 4908 4908 + if (!dc->caps.ips_support || (dc->config.disable_ips == DMUB_IPS_DISABLE_ALL)) 4932 4909 return false; 4933 4910 4934 4911 if (dc->hwss.get_idle_state)

+1 -1

drivers/gpu/drm/amd/display/dc/dc.h

reviewed

··· 49 49 struct set_config_cmd_payload; 50 50 struct dmub_notification; 51 51 52 52 - #define DC_VER "3.2.256" 52 52 + #define DC_VER "3.2.259" 53 53 54 54 #define MAX_SURFACES 3 55 55 #define MAX_PLANES 6

+74

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

reviewed

··· 120 120 } 121 121 } 122 122 123 123 + bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 124 124 + unsigned int count, 125 125 + union dmub_rb_cmd *cmd_list) 126 126 + { 127 127 + struct dc_context *dc_ctx = dc_dmub_srv->ctx; 128 128 + struct dmub_srv *dmub; 129 129 + enum dmub_status status; 130 130 + int i; 131 131 + 132 132 + if (!dc_dmub_srv || !dc_dmub_srv->dmub) 133 133 + return false; 134 134 + 135 135 + dmub = dc_dmub_srv->dmub; 136 136 + 137 137 + for (i = 0 ; i < count; i++) { 138 138 + // Queue command 139 139 + status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 140 140 + 141 141 + if (status == DMUB_STATUS_QUEUE_FULL) { 142 142 + /* Execute and wait for queue to become empty again. */ 143 143 + dmub_srv_cmd_execute(dmub); 144 144 + dmub_srv_wait_for_idle(dmub, 100000); 145 145 + 146 146 + /* Requeue the command. */ 147 147 + status = dmub_srv_cmd_queue(dmub, &cmd_list[i]); 148 148 + } 149 149 + 150 150 + if (status != DMUB_STATUS_OK) { 151 151 + DC_ERROR("Error queueing DMUB command: status=%d\n", status); 152 152 + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 153 153 + return false; 154 154 + } 155 155 + } 156 156 + 157 157 + status = dmub_srv_cmd_execute(dmub); 158 158 + if (status != DMUB_STATUS_OK) { 159 159 + DC_ERROR("Error starting DMUB execution: status=%d\n", status); 160 160 + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 161 161 + return false; 162 162 + } 163 163 + 164 164 + return true; 165 165 + } 166 166 + 167 167 + bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, 168 168 + enum dm_dmub_wait_type wait_type, 169 169 + union dmub_rb_cmd *cmd_list) 170 170 + { 171 171 + struct dmub_srv *dmub; 172 172 + enum dmub_status status; 173 173 + 174 174 + if (!dc_dmub_srv || !dc_dmub_srv->dmub) 175 175 + return false; 176 176 + 177 177 + dmub = dc_dmub_srv->dmub; 178 178 + 179 179 + // Wait for DMUB to process command 180 180 + if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { 181 181 + status = dmub_srv_wait_for_idle(dmub, 100000); 182 182 + 183 183 + if (status != DMUB_STATUS_OK) { 184 184 + DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status); 185 185 + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); 186 186 + return false; 187 187 + } 188 188 + 189 189 + // Copy data back from ring buffer into command 190 190 + if (wait_type == DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) 191 191 + dmub_rb_get_return_data(&dmub->inbox1_rb, cmd_list); 192 192 + } 193 193 + 194 194 + return true; 195 195 + } 196 196 + 123 197 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 124 198 { 125 199 return dc_dmub_srv_cmd_run_list(dc_dmub_srv, 1, cmd, wait_type);

+8

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

reviewed

··· 56 56 57 57 bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv); 58 58 59 59 + bool dc_dmub_srv_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srv, 60 60 + unsigned int count, 61 61 + union dmub_rb_cmd *cmd_list); 62 62 + 63 63 + bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, 64 64 + enum dm_dmub_wait_type wait_type, 65 65 + union dmub_rb_cmd *cmd_list); 66 66 + 59 67 bool dc_dmub_srv_cmd_run(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 60 68 61 69 bool dc_dmub_srv_cmd_run_list(struct dc_dmub_srv *dc_dmub_srv, unsigned int count, union dmub_rb_cmd *cmd_list, enum dm_dmub_wait_type wait_type);

+2 -1

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

reviewed

··· 142 142 DP_TEST_LINK_RATE_HBR3 = 0x1E, 143 143 DP_TEST_LINK_RATE_UHBR10 = 0x01, 144 144 DP_TEST_LINK_RATE_UHBR20 = 0x02, 145 145 - DP_TEST_LINK_RATE_UHBR13_5 = 0x03, 145 145 + DP_TEST_LINK_RATE_UHBR13_5_LEGACY = 0x03, /* For backward compatibility*/ 146 146 + DP_TEST_LINK_RATE_UHBR13_5 = 0x04, 146 147 }; 147 148 148 149 struct dc_link_settings {

+3 -1

drivers/gpu/drm/amd/display/dc/dc_types.h

reviewed

··· 1037 1037 bool replay_smu_opt_supported; // SMU optimization is supported 1038 1038 unsigned int replay_enable_option; // Replay enablement option 1039 1039 uint32_t debug_flags; // Replay debug flags 1040 1040 - bool replay_timing_sync_supported; // Replay desync is supported 1040 1040 + bool replay_timing_sync_supported; // Replay desync is supported 1041 1041 + bool force_disable_desync_error_check; // Replay desync is supported 1042 1042 + bool received_desync_error_hpd; //Replay Received Desync Error HPD. 1041 1043 union replay_error_status replay_error_status; // Replay error status 1042 1044 }; 1043 1045

-15

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

reviewed

··· 128 128 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 129 129 NBIO_SR(BIOS_SCRATCH_2) 130 130 131 131 - #define ABM_DCN32_REG_LIST(id)\ 132 132 - SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 133 133 - SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 134 134 - SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 135 135 - SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 136 136 - SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 137 137 - SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 138 138 - SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 139 139 - SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 140 140 - SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 141 141 - SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 142 142 - SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ 143 143 - SRI(DC_ABM1_ACE_THRES_12, ABM, id), \ 144 144 - NBIO_SR(BIOS_SCRATCH_2) 145 145 - 146 131 #define ABM_SF(reg_name, field_name, post_fix)\ 147 132 .field_name = reg_name ## __ ## field_name ## post_fix 148 133

+1 -185

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

reviewed

··· 26 26 #ifndef __DC_TIMING_GENERATOR_DCN10_H__ 27 27 #define __DC_TIMING_GENERATOR_DCN10_H__ 28 28 29 29 - #include "timing_generator.h" 29 29 + #include "optc.h" 30 30 31 31 #define DCN10TG_FROM_TG(tg)\ 32 32 container_of(tg, struct optc, base) ··· 594 594 TG_REG_FIELD_LIST_DCN3_5(uint32_t) 595 595 }; 596 596 597 597 - struct optc { 598 598 - struct timing_generator base; 599 599 - 600 600 - const struct dcn_optc_registers *tg_regs; 601 601 - const struct dcn_optc_shift *tg_shift; 602 602 - const struct dcn_optc_mask *tg_mask; 603 603 - 604 604 - int opp_count; 605 605 - 606 606 - uint32_t max_h_total; 607 607 - uint32_t max_v_total; 608 608 - 609 609 - uint32_t min_h_blank; 610 610 - 611 611 - uint32_t min_h_sync_width; 612 612 - uint32_t min_v_sync_width; 613 613 - uint32_t min_v_blank; 614 614 - uint32_t min_v_blank_interlace; 615 615 - 616 616 - int vstartup_start; 617 617 - int vupdate_offset; 618 618 - int vupdate_width; 619 619 - int vready_offset; 620 620 - struct dc_crtc_timing orginal_patched_timing; 621 621 - enum signal_type signal; 622 622 - }; 623 623 - 624 597 void dcn10_timing_generator_init(struct optc *optc); 625 625 - 626 626 - struct dcn_otg_state { 627 627 - uint32_t v_blank_start; 628 628 - uint32_t v_blank_end; 629 629 - uint32_t v_sync_a_pol; 630 630 - uint32_t v_total; 631 631 - uint32_t v_total_max; 632 632 - uint32_t v_total_min; 633 633 - uint32_t v_total_min_sel; 634 634 - uint32_t v_total_max_sel; 635 635 - uint32_t v_sync_a_start; 636 636 - uint32_t v_sync_a_end; 637 637 - uint32_t h_blank_start; 638 638 - uint32_t h_blank_end; 639 639 - uint32_t h_sync_a_start; 640 640 - uint32_t h_sync_a_end; 641 641 - uint32_t h_sync_a_pol; 642 642 - uint32_t h_total; 643 643 - uint32_t underflow_occurred_status; 644 644 - uint32_t otg_enabled; 645 645 - uint32_t blank_enabled; 646 646 - uint32_t vertical_interrupt1_en; 647 647 - uint32_t vertical_interrupt1_line; 648 648 - uint32_t vertical_interrupt2_en; 649 649 - uint32_t vertical_interrupt2_line; 650 650 - }; 651 651 - 652 652 - void optc1_read_otg_state(struct optc *optc1, 653 653 - struct dcn_otg_state *s); 654 654 - 655 655 - bool optc1_get_hw_timing(struct timing_generator *tg, 656 656 - struct dc_crtc_timing *hw_crtc_timing); 657 657 - 658 658 - bool optc1_validate_timing( 659 659 - struct timing_generator *optc, 660 660 - const struct dc_crtc_timing *timing); 661 661 - 662 662 - void optc1_program_timing( 663 663 - struct timing_generator *optc, 664 664 - const struct dc_crtc_timing *dc_crtc_timing, 665 665 - int vready_offset, 666 666 - int vstartup_start, 667 667 - int vupdate_offset, 668 668 - int vupdate_width, 669 669 - const enum signal_type signal, 670 670 - bool use_vbios); 671 671 - 672 672 - void optc1_setup_vertical_interrupt0( 673 673 - struct timing_generator *optc, 674 674 - uint32_t start_line, 675 675 - uint32_t end_line); 676 676 - void optc1_setup_vertical_interrupt1( 677 677 - struct timing_generator *optc, 678 678 - uint32_t start_line); 679 679 - void optc1_setup_vertical_interrupt2( 680 680 - struct timing_generator *optc, 681 681 - uint32_t start_line); 682 682 - 683 683 - void optc1_program_global_sync( 684 684 - struct timing_generator *optc, 685 685 - int vready_offset, 686 686 - int vstartup_start, 687 687 - int vupdate_offset, 688 688 - int vupdate_width); 689 689 - 690 690 - bool optc1_disable_crtc(struct timing_generator *optc); 691 691 - 692 692 - bool optc1_is_counter_moving(struct timing_generator *optc); 693 693 - 694 694 - void optc1_get_position(struct timing_generator *optc, 695 695 - struct crtc_position *position); 696 696 - 697 697 - uint32_t optc1_get_vblank_counter(struct timing_generator *optc); 698 698 - 699 699 - void optc1_get_crtc_scanoutpos( 700 700 - struct timing_generator *optc, 701 701 - uint32_t *v_blank_start, 702 702 - uint32_t *v_blank_end, 703 703 - uint32_t *h_position, 704 704 - uint32_t *v_position); 705 705 - 706 706 - void optc1_set_early_control( 707 707 - struct timing_generator *optc, 708 708 - uint32_t early_cntl); 709 709 - 710 710 - void optc1_wait_for_state(struct timing_generator *optc, 711 711 - enum crtc_state state); 712 712 - 713 713 - void optc1_set_blank(struct timing_generator *optc, 714 714 - bool enable_blanking); 715 715 - 716 716 - bool optc1_is_blanked(struct timing_generator *optc); 717 717 - 718 718 - void optc1_program_blank_color( 719 719 - struct timing_generator *optc, 720 720 - const struct tg_color *black_color); 721 721 - 722 722 - bool optc1_did_triggered_reset_occur( 723 723 - struct timing_generator *optc); 724 724 - 725 725 - void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); 726 726 - 727 727 - void optc1_disable_reset_trigger(struct timing_generator *optc); 728 728 - 729 729 - void optc1_lock(struct timing_generator *optc); 730 730 - 731 731 - void optc1_unlock(struct timing_generator *optc); 732 732 - 733 733 - void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); 734 734 - 735 735 - void optc1_set_drr( 736 736 - struct timing_generator *optc, 737 737 - const struct drr_params *params); 738 738 - 739 739 - void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); 740 740 - 741 741 - void optc1_set_static_screen_control( 742 742 - struct timing_generator *optc, 743 743 - uint32_t event_triggers, 744 744 - uint32_t num_frames); 745 745 - 746 746 - void optc1_program_stereo(struct timing_generator *optc, 747 747 - const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 748 748 - 749 749 - bool optc1_is_stereo_left_eye(struct timing_generator *optc); 750 750 - 751 751 - void optc1_clear_optc_underflow(struct timing_generator *optc); 752 752 - 753 753 - void optc1_tg_init(struct timing_generator *optc); 754 754 - 755 755 - bool optc1_is_tg_enabled(struct timing_generator *optc); 756 756 - 757 757 - bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); 758 758 - 759 759 - void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); 760 760 - 761 761 - void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable); 762 762 - 763 763 - bool optc1_get_otg_active_size(struct timing_generator *optc, 764 764 - uint32_t *otg_active_width, 765 765 - uint32_t *otg_active_height); 766 766 - 767 767 - void optc1_enable_crtc_reset( 768 768 - struct timing_generator *optc, 769 769 - int source_tg_inst, 770 770 - struct crtc_trigger_info *crtc_tp); 771 771 - 772 772 - bool optc1_configure_crc(struct timing_generator *optc, 773 773 - const struct crc_params *params); 774 774 - 775 775 - bool optc1_get_crc(struct timing_generator *optc, 776 776 - uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 777 777 - 778 778 - bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); 779 779 - 780 780 - void optc1_set_vtg_params(struct timing_generator *optc, 781 781 - const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 782 598 783 599 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */

+9 -1

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c

reviewed

··· 137 137 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 138 138 } 139 139 140 140 - // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 140 140 + /* For pixel clock bigger than a single-pipe limit needing four engines ODM 4:1, which then quardruples our 141 141 + * throughput and number of slices 142 142 + */ 143 143 + if (pixel_clock_100Hz > DCN20_MAX_PIXEL_CLOCK_Mhz*10000*2) { 144 144 + dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1; 145 145 + dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1; 146 146 + dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4; 147 147 + } 148 148 + 141 149 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 142 150 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 143 151 }

+41 -32

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c

reviewed

··· 325 325 } 326 326 } 327 327 328 328 + static void dccg35_set_physymclk_root_clock_gating( 329 329 + struct dccg *dccg, 330 330 + int phy_inst, 331 331 + bool enable) 332 332 + { 333 333 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 334 334 + 335 335 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 336 336 + return; 337 337 + 338 338 + switch (phy_inst) { 339 339 + case 0: 340 340 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 341 341 + PHYASYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); 342 342 + break; 343 343 + case 1: 344 344 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 345 345 + PHYBSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); 346 346 + break; 347 347 + case 2: 348 348 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 349 349 + PHYCSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); 350 350 + break; 351 351 + case 3: 352 352 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 353 353 + PHYDSYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); 354 354 + break; 355 355 + case 4: 356 356 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 357 357 + PHYESYMCLK_ROOT_GATE_DISABLE, enable ? 1 : 0); 358 358 + break; 359 359 + default: 360 360 + BREAK_TO_DEBUGGER(); 361 361 + return; 362 362 + } 363 363 + } 364 364 + 328 365 static void dccg35_set_physymclk( 329 366 struct dccg *dccg, 330 367 int phy_inst, ··· 377 340 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, 378 341 PHYASYMCLK_EN, 1, 379 342 PHYASYMCLK_SRC_SEL, clk_src); 380 380 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 381 381 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 382 382 - PHYASYMCLK_ROOT_GATE_DISABLE, 1); 383 343 } else { 384 344 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, 385 345 PHYASYMCLK_EN, 0, 386 346 PHYASYMCLK_SRC_SEL, 0); 387 387 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 388 388 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 389 389 - PHYASYMCLK_ROOT_GATE_DISABLE, 0); 390 347 } 391 348 break; 392 349 case 1: ··· 388 357 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, 389 358 PHYBSYMCLK_EN, 1, 390 359 PHYBSYMCLK_SRC_SEL, clk_src); 391 391 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 392 392 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 393 393 - PHYBSYMCLK_ROOT_GATE_DISABLE, 1); 394 360 } else { 395 361 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, 396 362 PHYBSYMCLK_EN, 0, 397 363 PHYBSYMCLK_SRC_SEL, 0); 398 398 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 399 399 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 400 400 - PHYBSYMCLK_ROOT_GATE_DISABLE, 0); 401 364 } 402 365 break; 403 366 case 2: ··· 399 374 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, 400 375 PHYCSYMCLK_EN, 1, 401 376 PHYCSYMCLK_SRC_SEL, clk_src); 402 402 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 403 403 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 404 404 - PHYCSYMCLK_ROOT_GATE_DISABLE, 1); 405 377 } else { 406 378 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, 407 379 PHYCSYMCLK_EN, 0, 408 380 PHYCSYMCLK_SRC_SEL, 0); 409 409 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 410 410 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 411 411 - PHYCSYMCLK_ROOT_GATE_DISABLE, 0); 412 381 } 413 382 break; 414 383 case 3: ··· 410 391 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, 411 392 PHYDSYMCLK_EN, 1, 412 393 PHYDSYMCLK_SRC_SEL, clk_src); 413 413 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 414 414 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 415 415 - PHYDSYMCLK_ROOT_GATE_DISABLE, 1); 416 394 } else { 417 395 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, 418 396 PHYDSYMCLK_EN, 0, 419 397 PHYDSYMCLK_SRC_SEL, 0); 420 420 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 421 421 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 422 422 - PHYDSYMCLK_ROOT_GATE_DISABLE, 0); 423 398 } 424 399 break; 425 400 case 4: ··· 421 408 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, 422 409 PHYESYMCLK_EN, 1, 423 410 PHYESYMCLK_SRC_SEL, clk_src); 424 424 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 425 425 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 426 426 - PHYESYMCLK_ROOT_GATE_DISABLE, 1); 427 411 } else { 428 412 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, 429 413 PHYESYMCLK_EN, 0, 430 414 PHYESYMCLK_SRC_SEL, 0); 431 431 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 432 432 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 433 433 - PHYESYMCLK_ROOT_GATE_DISABLE, 0); 434 415 } 435 416 break; 436 417 default: ··· 497 490 498 491 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 499 492 for (otg_inst = 0; otg_inst < 5; otg_inst++) 500 500 - dccg35_set_physymclk(dccg, otg_inst, 501 501 - PHYSYMCLK_FORCE_SRC_SYMCLK, false); 493 493 + dccg35_set_physymclk_root_clock_gating(dccg, otg_inst, 494 494 + false); 502 495 /* 503 496 dccg35_enable_global_fgcg_rep( 504 497 dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits ··· 761 754 .disable_symclk32_se = dccg31_disable_symclk32_se, 762 755 .enable_symclk32_le = dccg31_enable_symclk32_le, 763 756 .disable_symclk32_le = dccg31_disable_symclk32_le, 757 757 + .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating, 764 758 .set_physymclk = dccg35_set_physymclk, 759 759 + .set_physymclk_root_clock_gating = dccg35_set_physymclk_root_clock_gating, 765 760 .set_dtbclk_dto = dccg35_set_dtbclk_dto, 766 761 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, 767 762 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,

+9 -1

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c

reviewed

··· 332 332 pg_cntl->pg_res_enable[PG_DCIO] = power_on; 333 333 } 334 334 335 335 + void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on) 336 336 + { 337 337 + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); 338 338 + 339 339 + REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, power_on ? 1 : 0); 340 340 + } 341 341 + 335 342 static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl) 336 343 { 337 344 struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); ··· 508 501 .mpcc_pg_control = pg_cntl35_mpcc_pg_control, 509 502 .opp_pg_control = pg_cntl35_opp_pg_control, 510 503 .optc_pg_control = pg_cntl35_optc_pg_control, 511 511 - .dwb_pg_control = pg_cntl35_dwb_pg_control 504 504 + .dwb_pg_control = pg_cntl35_dwb_pg_control, 505 505 + .set_force_poweron_domain22 = pg_cntl35_set_force_poweron_domain22 512 506 }; 513 507 514 508 struct pg_cntl *pg_cntl35_create(

+1

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h

reviewed

··· 183 183 unsigned int optc_inst, bool power_on); 184 184 void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on); 185 185 void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl); 186 186 + void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on); 186 187 187 188 struct pg_cntl *pg_cntl35_create( 188 189 struct dc_context *ctx,

+26 -11

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

reviewed

··· 610 610 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ 611 611 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ 612 612 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ 613 613 - HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh) 613 613 + HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ 614 614 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ 615 615 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ 616 616 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ 617 617 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ 618 618 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ 619 619 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ 620 620 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ 621 621 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ 622 622 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ 623 623 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ 624 624 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ 625 625 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 626 626 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 627 627 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 628 628 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ 629 629 + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh) 614 630 615 631 static const struct dce_hwseq_shift hwseq_shift = { 616 632 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT) ··· 724 708 .i2c = true, 725 709 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 726 710 .dscl = true, 727 727 - .cm = true, 711 711 + .cm = false, 728 712 .mpc = true, 729 713 .optc = true, 730 714 .vpg = true, ··· 735 719 .bits = { 736 720 .dpp = true, 737 721 .dsc = true,/*dscclk and dsc pg*/ 738 738 - .hdmistream = false, 739 739 - .hdmichar = false, 740 740 - .dpstream = false, 741 741 - .symclk32_se = false, 742 742 - .symclk32_le = false, 743 743 - .symclk_fe = false, 744 744 - .physymclk = false, 745 745 - .dpiasymclk = false, 722 722 + .hdmistream = true, 723 723 + .hdmichar = true, 724 724 + .dpstream = true, 725 725 + .symclk32_se = true, 726 726 + .symclk32_le = true, 727 727 + .symclk_fe = true, 728 728 + .physymclk = true, 729 729 + .dpiasymclk = true, 746 730 } 747 731 }, 748 732 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, ··· 757 741 .disable_boot_optimizations = false, 758 742 .disable_unbounded_requesting = false, 759 743 .disable_mem_low_power = false, 760 760 - .enable_hpo_pg_support = false, 761 744 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 762 745 .enable_double_buffered_dsc_pg_support = true, 763 746 .enable_dp_dig_pixel_rate_div_policy = 1,

+1 -1

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

reviewed

··· 5128 5128 ViewportExceedsSurface = true; 5129 5129 5130 5130 if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16 5131 5131 - && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8 && v->SourcePixelFormat[k] != dm_rgbe) { 5131 5131 + && v->SourcePixelFormat[k] != dm_444_8 && v->SourcePixelFormat[k] != dm_rgbe) { 5132 5132 if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k] || v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) { 5133 5133 ViewportExceedsSurface = true; 5134 5134 }

+30 -31

drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c

reviewed

··· 55 55 struct dc_plane_pipe_pool pipe_pool; 56 56 }; 57 57 58 58 - static bool get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, 59 59 - unsigned int stream_id, unsigned int *plane_id) 58 58 + static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane, 59 59 + unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) 60 60 { 61 61 int i, j; 62 62 + bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists; 62 63 63 64 if (!plane_id) 64 65 return false; ··· 67 66 for (i = 0; i < state->stream_count; i++) { 68 67 if (state->streams[i]->stream_id == stream_id) { 69 68 for (j = 0; j < state->stream_status[i].plane_count; j++) { 70 70 - if (state->stream_status[i].plane_states[j] == plane) { 69 69 + if (state->stream_status[i].plane_states[j] == plane && 70 70 + (!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) { 71 71 *plane_id = (i << 16) | j; 72 72 return true; 73 73 } ··· 125 123 unsigned int plane_id_assigned_to_pipe; 126 124 127 125 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { 128 128 - if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(state, state->res_ctx.pipe_ctx[i].plane_state, 129 129 - state->res_ctx.pipe_ctx[i].stream->stream_id, &plane_id_assigned_to_pipe)) { 126 126 + if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state, 127 127 + state->res_ctx.pipe_ctx[i].stream->stream_id, 128 128 + ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) { 130 129 if (plane_id_assigned_to_pipe == plane_id) 131 130 return &state->res_ctx.pipe_ctx[i]; 132 131 } ··· 144 141 unsigned int plane_id_assigned_to_pipe; 145 142 146 143 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { 147 147 - if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(state, state->res_ctx.pipe_ctx[i].plane_state, 148 148 - state->res_ctx.pipe_ctx[i].stream->stream_id, &plane_id_assigned_to_pipe)) { 144 144 + if (state->res_ctx.pipe_ctx[i].plane_state && get_plane_id(ctx, state, state->res_ctx.pipe_ctx[i].plane_state, 145 145 + state->res_ctx.pipe_ctx[i].stream->stream_id, 146 146 + ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id_assigned_to_pipe)) { 149 147 if (plane_id_assigned_to_pipe == plane_id) 150 148 pipes[num_found++] = i; 151 149 } ··· 613 609 const struct dc_plane_state *plane, 614 610 int odm_factor, 615 611 int mpc_factor, 612 612 + int plane_index, 616 613 struct dc_plane_pipe_pool *pipe_pool, 617 614 const struct dc_state *existing_state) 618 615 { ··· 625 620 unsigned int next_pipe_to_assign; 626 621 int odm_slice, mpc_slice; 627 622 628 628 - if (!get_plane_id(state, plane, stream->stream_id, &plane_id)) { 623 623 + if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) { 629 624 ASSERT(false); 630 625 return master_pipe; 631 626 } ··· 672 667 } 673 668 674 669 static void free_unused_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state, 675 675 - const struct dc_plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id) 670 670 + const struct dc_plane_state *plane, const struct dc_plane_pipe_pool *pool, unsigned int stream_id, int plane_index) 676 671 { 677 672 int i; 673 673 + bool is_plane_duplicate = ctx->v20.scratch.plane_duplicate_exists; 674 674 + 678 675 for (i = 0; i < ctx->config.dcn_pipe_count; i++) { 679 676 if (state->res_ctx.pipe_ctx[i].plane_state == plane && 680 677 state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id && 678 678 + (!is_plane_duplicate || (is_plane_duplicate && 679 679 + ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[state->res_ctx.pipe_ctx[i].pipe_idx] == plane_index)) && 681 680 !is_pipe_used(pool, state->res_ctx.pipe_ctx[i].pipe_idx)) { 682 681 free_pipe(&state->res_ctx.pipe_ctx[i]); 683 682 } ··· 726 717 } 727 718 728 719 static void map_pipes_for_plane(struct dml2_context *ctx, struct dc_state *state, const struct dc_stream_state *stream, const struct dc_plane_state *plane, 729 729 - struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state) 720 720 + int plane_index, struct dc_pipe_mapping_scratch *scratch, const struct dc_state *existing_state) 730 721 { 731 722 int odm_slice_index; 732 723 unsigned int plane_id; 733 724 struct pipe_ctx *master_pipe = NULL; 734 725 int i; 735 726 736 736 - if (!get_plane_id(state, plane, stream->stream_id, &plane_id)) { 727 727 + if (!get_plane_id(ctx, state, plane, stream->stream_id, plane_index, &plane_id)) { 737 728 ASSERT(false); 738 729 return; 739 730 } 740 731 741 741 - master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor, scratch->mpc_info.mpc_factor, &scratch->pipe_pool, existing_state); 732 732 + master_pipe = assign_pipes_to_plane(ctx, state, stream, plane, scratch->odm_info.odm_factor, 733 733 + scratch->mpc_info.mpc_factor, plane_index, &scratch->pipe_pool, existing_state); 742 734 sort_pipes_for_splitting(&scratch->pipe_pool); 743 735 744 736 for (odm_slice_index = 0; odm_slice_index < scratch->odm_info.odm_factor; odm_slice_index++) { ··· 765 755 } 766 756 } 767 757 768 768 - free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id); 758 758 + free_unused_pipes_for_plane(ctx, state, plane, &scratch->pipe_pool, stream->stream_id, plane_index); 769 759 } 770 760 771 761 static unsigned int get_mpc_factor(struct dml2_context *ctx, ··· 778 768 unsigned int plane_id; 779 769 unsigned int cfg_idx; 780 770 781 781 - get_plane_id(state, status->plane_states[plane_idx], stream_id, &plane_id); 771 771 + get_plane_id(ctx, state, status->plane_states[plane_idx], stream_id, plane_idx, &plane_id); 782 772 cfg_idx = find_disp_cfg_idx_by_plane_id(mapping, plane_id); 783 773 if (ctx->architecture == dml2_architecture_20) 784 774 return (unsigned int)disp_cfg->hw.DPPPerSurface[cfg_idx]; ··· 921 911 unsigned int stream_id; 922 912 923 913 const unsigned int *ODMMode, *DPPPerSurface; 924 924 - unsigned int odm_mode_array[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}, dpp_per_surface_array[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; 925 914 struct dc_pipe_mapping_scratch scratch; 926 915 927 916 if (ctx->config.map_dc_pipes_with_callbacks) 928 917 return map_dc_pipes_with_callbacks( 929 918 ctx, state, disp_cfg, mapping, existing_state); 930 919 931 931 - if (ctx->architecture == dml2_architecture_21) { 932 932 - /* 933 933 - * Extract ODM and DPP outputs from DML2.1 and map them in an array as required for pipe mapping in dml2_map_dc_pipes. 934 934 - * As data cannot be directly extracted in const pointers, assign these arrays to const pointers before proceeding to 935 935 - * maximize the reuse of existing code. Const pointers are required because dml2.0 dml_display_cfg_st is const. 936 936 - * 937 937 - */ 938 938 - ODMMode = (const unsigned int *)odm_mode_array; 939 939 - DPPPerSurface = (const unsigned int *)dpp_per_surface_array; 940 940 - } else { 941 941 - ODMMode = (unsigned int *)disp_cfg->hw.ODMMode; 942 942 - DPPPerSurface = disp_cfg->hw.DPPPerSurface; 943 943 - } 920 920 + ODMMode = (unsigned int *)disp_cfg->hw.ODMMode; 921 921 + DPPPerSurface = disp_cfg->hw.DPPPerSurface; 944 922 945 923 for (stream_index = 0; stream_index < state->stream_count; stream_index++) { 946 924 memset(&scratch, 0, sizeof(struct dc_pipe_mapping_scratch)); ··· 956 958 957 959 for (plane_index = 0; plane_index < state->stream_status[stream_index].plane_count; plane_index++) { 958 960 // Planes are ordered top to bottom. 959 959 - if (get_plane_id(state, state->stream_status[stream_index].plane_states[plane_index], 960 960 - stream_id, &plane_id)) { 961 961 + if (get_plane_id(ctx, state, state->stream_status[stream_index].plane_states[plane_index], 962 962 + stream_id, plane_index, &plane_id)) { 961 963 plane_disp_cfg_index = find_disp_cfg_idx_by_plane_id(mapping, plane_id); 962 964 963 965 // Setup mpc_info for this plane ··· 981 983 // Clear the pool assignment scratch (which is per plane) 982 984 memset(&scratch.pipe_pool, 0, sizeof(struct dc_plane_pipe_pool)); 983 985 984 984 - map_pipes_for_plane(ctx, state, state->streams[stream_index], state->stream_status[stream_index].plane_states[plane_index], &scratch, existing_state); 986 986 + map_pipes_for_plane(ctx, state, state->streams[stream_index], 987 987 + state->stream_status[stream_index].plane_states[plane_index], plane_index, &scratch, existing_state); 985 988 } else { 986 989 // Plane ID cannot be generated, therefore no DML mapping can be performed. 987 990 ASSERT(false);

+3 -1

drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h

reviewed

··· 75 75 bool dml_pipe_idx_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 76 76 unsigned int dml_pipe_idx_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 77 77 bool dml_pipe_idx_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 78 78 + unsigned int dml_pipe_idx_to_plane_index[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 79 79 + bool dml_pipe_idx_to_plane_index_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; 78 80 }; 79 81 80 82 struct dml2_wrapper_scratch { ··· 98 96 99 97 struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping; 100 98 bool enable_flexible_pipe_mapping; 99 99 + bool plane_duplicate_exists; 101 100 }; 102 101 103 102 struct dml2_helper_det_policy_scratch { ··· 107 104 108 105 enum dml2_architecture { 109 106 dml2_architecture_20, 110 110 - dml2_architecture_21 111 107 }; 112 108 113 109 struct dml2_context {

+47 -8

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

reviewed

··· 231 231 out->num_chans = 4; 232 232 out->round_trip_ping_latency_dcfclk_cycles = 106; 233 233 out->smn_latency_us = 2; 234 234 + out->dispclk_dppclk_vco_speed_mhz = 3600; 234 235 break; 235 236 236 237 case dml_project_dcn351: ··· 931 930 return location; 932 931 } 933 932 934 934 - static bool get_plane_id(const struct dc_state *context, const struct dc_plane_state *plane, 935 935 - unsigned int stream_id, unsigned int *plane_id) 933 933 + static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane, 934 934 + unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) 936 935 { 937 936 int i, j; 937 937 + bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists; 938 938 939 939 if (!plane_id) 940 940 return false; ··· 943 941 for (i = 0; i < context->stream_count; i++) { 944 942 if (context->streams[i]->stream_id == stream_id) { 945 943 for (j = 0; j < context->stream_status[i].plane_count; j++) { 946 946 - if (context->stream_status[i].plane_states[j] == plane) { 944 944 + if (context->stream_status[i].plane_states[j] == plane && 945 945 + (!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) { 947 946 *plane_id = (i << 16) | j; 948 947 return true; 949 948 } ··· 956 953 } 957 954 958 955 static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane, 959 959 - const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id) 956 956 + const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index) 960 957 { 961 958 unsigned int plane_id; 962 959 int i = 0; 963 960 int location = -1; 964 961 965 965 - if (!get_plane_id(context, plane, stream_id, &plane_id)) { 962 962 + if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { 966 963 ASSERT(false); 967 964 return -1; 968 965 } ··· 993 990 } 994 991 } 995 992 996 996 - void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg) 993 993 + static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state) 994 994 + { 995 995 + unsigned int i; 996 996 + unsigned int pipe_index = 0; 997 997 + unsigned int plane_index = 0; 998 998 + struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping; 999 999 + 1000 1000 + for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 1001 1001 + dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false; 1002 1002 + dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[i] = 0; 1003 1003 + } 1004 1004 + 1005 1005 + for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 1006 1006 + struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; 1007 1007 + 1008 1008 + if (!pipe || !pipe->stream || !pipe->plane_state) 1009 1009 + continue; 1010 1010 + 1011 1011 + while (pipe) { 1012 1012 + pipe_index = pipe->pipe_idx; 1013 1013 + 1014 1014 + if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) { 1015 1015 + dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index; 1016 1016 + plane_index++; 1017 1017 + dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true; 1018 1018 + } 1019 1019 + 1020 1020 + pipe = pipe->bottom_pipe; 1021 1021 + } 1022 1022 + 1023 1023 + plane_index = 0; 1024 1024 + } 1025 1025 + } 1026 1026 + 1027 1027 + void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg) 997 1028 { 998 1029 int i = 0, j = 0; 999 1030 int disp_cfg_stream_location, disp_cfg_plane_location; ··· 1043 1006 dml_dispcfg->plane.GPUVMEnable = true; 1044 1007 dml_dispcfg->plane.GPUVMMaxPageTableLevels = 4; 1045 1008 dml_dispcfg->plane.HostVMEnable = false; 1009 1009 + 1010 1010 + dml2_populate_pipe_to_plane_index_mapping(dml2, context); 1046 1011 1047 1012 for (i = 0; i < context->stream_count; i++) { 1048 1013 disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg); ··· 1082 1043 } else { 1083 1044 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1084 1045 disp_cfg_plane_location = map_plane_to_dml_display_cfg(dml2, 1085 1085 - context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id); 1046 1046 + context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j); 1086 1047 1087 1048 if (disp_cfg_plane_location < 0) 1088 1049 disp_cfg_plane_location = dml_dispcfg->num_surfaces++; ··· 1106 1067 1107 1068 dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location; 1108 1069 1109 1109 - if (get_plane_id(context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, 1070 1070 + if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j, 1110 1071 &dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location])) 1111 1072 dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true; 1112 1073

+1 -1

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h

reviewed

··· 34 34 void dml2_translate_ip_params(const struct dc *in_dc, struct ip_params_st *out); 35 35 void dml2_translate_socbb_params(const struct dc *in_dc, struct soc_bounding_box_st *out); 36 36 void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states); 37 37 - void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, const struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg); 37 37 + void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg); 38 38 void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out); 39 39 bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe); 40 40

+11 -7

drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c

reviewed

··· 209 209 return -1; 210 210 } 211 211 212 212 - static bool get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, 213 213 - unsigned int stream_id, unsigned int *plane_id) 212 212 + static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane, 213 213 + unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) 214 214 { 215 215 int i, j; 216 216 + bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists; 216 217 217 218 if (!plane_id) 218 219 return false; ··· 221 220 for (i = 0; i < state->stream_count; i++) { 222 221 if (state->streams[i]->stream_id == stream_id) { 223 222 for (j = 0; j < state->stream_status[i].plane_count; j++) { 224 224 - if (state->stream_status[i].plane_states[j] == plane) { 223 223 + if (state->stream_status[i].plane_states[j] == plane && 224 224 + (!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) { 225 225 *plane_id = (i << 16) | j; 226 226 return true; 227 227 } ··· 306 304 * there is a need to know which DML pipe index maps to which DC pipe. The code below 307 305 * finds a dml_pipe_index from the plane id if a plane is valid. If a plane is not valid then 308 306 * it finds a dml_pipe_index from the stream id. */ 309 309 - if (get_plane_id(context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state, 310 310 - context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id, &plane_id)) { 307 307 + if (get_plane_id(in_ctx, context, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state, 308 308 + context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id, 309 309 + in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], &plane_id)) { 311 310 dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id); 312 311 } else { 313 312 dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id); ··· 448 445 for (i = 0; i < MAX_PIPES; i++) { 449 446 if (!display_state->res_ctx.pipe_ctx[i].stream) 450 447 continue; 451 451 - if (get_plane_id(display_state, display_state->res_ctx.pipe_ctx[i].plane_state, 452 452 - display_state->res_ctx.pipe_ctx[i].stream->stream_id, &plane_id)) 448 448 + if (get_plane_id(in_ctx, display_state, display_state->res_ctx.pipe_ctx[i].plane_state, 449 449 + display_state->res_ctx.pipe_ctx[i].stream->stream_id, 450 450 + in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], &plane_id)) 453 451 dml_pipe_idx = find_dml_pipe_idx_by_plane_id(in_ctx, plane_id); 454 452 else 455 453 dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(in_ctx, display_state->res_ctx.pipe_ctx[i].stream->stream_id);

+1 -1

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c

reviewed

··· 639 639 return result; 640 640 } 641 641 642 642 - static bool dml2_validate_only(const struct dc_state *context) 642 642 + static bool dml2_validate_only(struct dc_state *context) 643 643 { 644 644 struct dml2_context *dml2 = context->bw_ctx.dml2; 645 645 unsigned int result = 0;

+11

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

reviewed

··· 512 512 dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4; 513 513 dsc_common_caps->slice_caps.bits.NUM_SLICES_8 = 514 514 dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8; 515 515 + dsc_common_caps->slice_caps.bits.NUM_SLICES_12 = 516 516 + dsc_sink_caps->slice_caps1.bits.NUM_SLICES_12 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_12; 517 517 + dsc_common_caps->slice_caps.bits.NUM_SLICES_16 = 518 518 + dsc_sink_caps->slice_caps2.bits.NUM_SLICES_16 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_16; 519 519 + 515 520 if (!dsc_common_caps->slice_caps.raw) 516 521 return false; 517 522 ··· 707 702 708 703 if (slice_caps.bits.NUM_SLICES_8) 709 704 available_slices[idx++] = 8; 705 705 + 706 706 + if (slice_caps.bits.NUM_SLICES_12) 707 707 + available_slices[idx++] = 12; 708 708 + 709 709 + if (slice_caps.bits.NUM_SLICES_16) 710 710 + available_slices[idx++] = 16; 710 711 711 712 return idx; 712 713 }

+17 -1

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

reviewed

··· 1183 1183 type LONO_FGCG_REP_DIS;\ 1184 1184 type LONO_DISPCLK_GATE_DISABLE;\ 1185 1185 type LONO_SOCCLK_GATE_DISABLE;\ 1186 1186 - type LONO_DMCUBCLK_GATE_DISABLE; 1186 1186 + type LONO_DMCUBCLK_GATE_DISABLE;\ 1187 1187 + type SYMCLKA_FE_GATE_DISABLE;\ 1188 1188 + type SYMCLKB_FE_GATE_DISABLE;\ 1189 1189 + type SYMCLKC_FE_GATE_DISABLE;\ 1190 1190 + type SYMCLKD_FE_GATE_DISABLE;\ 1191 1191 + type SYMCLKE_FE_GATE_DISABLE;\ 1192 1192 + type HDMICHARCLK0_GATE_DISABLE;\ 1193 1193 + type SYMCLKA_GATE_DISABLE;\ 1194 1194 + type SYMCLKB_GATE_DISABLE;\ 1195 1195 + type SYMCLKC_GATE_DISABLE;\ 1196 1196 + type SYMCLKD_GATE_DISABLE;\ 1197 1197 + type SYMCLKE_GATE_DISABLE;\ 1198 1198 + type PHYASYMCLK_ROOT_GATE_DISABLE;\ 1199 1199 + type PHYBSYMCLK_ROOT_GATE_DISABLE;\ 1200 1200 + type PHYCSYMCLK_ROOT_GATE_DISABLE;\ 1201 1201 + type PHYDSYMCLK_ROOT_GATE_DISABLE;\ 1202 1202 + type PHYESYMCLK_ROOT_GATE_DISABLE; 1187 1203 1188 1204 struct dce_hwseq_shift { 1189 1205 HWSEQ_REG_FIELD_LIST(uint8_t)

+2 -15

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

reviewed

··· 615 615 pipe->stream->fpo_in_use)) { 616 616 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 617 617 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); 618 618 - } 619 619 - 620 620 - /* Today only FPO uses cursor P-State force. Only clear cursor P-State force 621 621 - * if it's not FPO. 622 622 - */ 623 623 - if (!pipe->stream || !pipe->stream->fpo_in_use) { 624 618 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 625 619 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false); 626 620 } ··· 626 632 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 627 633 struct hubp *hubp = pipe->plane_res.hubp; 628 634 629 629 - if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 635 635 + if (pipe->stream && (pipe->stream->mall_stream_config.type == SUBVP_MAIN || 636 636 + pipe->stream->fpo_in_use)) { 630 637 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 631 638 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 632 632 - } 633 633 - 634 634 - if (pipe->stream && pipe->stream->fpo_in_use) { 635 635 - if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) 636 636 - hubp->funcs->hubp_update_force_pstate_disallow(hubp, true); 637 637 - /* For now only force cursor p-state disallow for FPO 638 638 - * Needs to be added for subvp once FW side gets updated 639 639 - */ 640 639 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow) 641 640 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true); 642 641 }

+29 -5

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

reviewed

··· 138 138 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 139 139 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 140 140 141 141 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 142 142 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0x3F000000); 143 143 - REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf); 144 144 - 145 141 //dcn35_set_dmu_fgcg(hws, dc->debug.enable_fine_grain_clock_gating.bits.dmu); 146 142 147 143 if (!dcb->funcs->is_accelerated_mode(dcb)) { 148 144 /*this calls into dmubfw to do the init*/ 149 145 hws->funcs.bios_golden_init(dc); 150 146 } 147 147 + 148 148 + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 149 149 + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 150 150 + 151 151 + /* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */ 152 152 + REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1, 153 153 + PHYBSYMCLK_ROOT_GATE_DISABLE, 1, 154 154 + PHYCSYMCLK_ROOT_GATE_DISABLE, 1, 155 155 + PHYDSYMCLK_ROOT_GATE_DISABLE, 1, 156 156 + PHYESYMCLK_ROOT_GATE_DISABLE, 1); 157 157 + 158 158 + REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf); 159 159 + 151 160 // Initialize the dccg 152 161 if (res_pool->dccg->funcs->dccg_init) 153 162 res_pool->dccg->funcs->dccg_init(res_pool->dccg); ··· 283 274 if (!dc->debug.disable_clock_gate) { 284 275 /* enable all DCN clock gating */ 285 276 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 286 286 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 277 277 + 278 278 + REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0, 279 279 + SYMCLKB_FE_GATE_DISABLE, 0, 280 280 + SYMCLKC_FE_GATE_DISABLE, 0, 281 281 + SYMCLKD_FE_GATE_DISABLE, 0, 282 282 + SYMCLKE_FE_GATE_DISABLE, 0); 283 283 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0); 284 284 + REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0, 285 285 + SYMCLKB_GATE_DISABLE, 0, 286 286 + SYMCLKC_GATE_DISABLE, 0, 287 287 + SYMCLKD_GATE_DISABLE, 0, 288 288 + SYMCLKE_GATE_DISABLE, 0); 289 289 + 287 290 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 288 291 } 289 292 ··· 332 311 if (dc->res_pool->pg_cntl) { 333 312 if (dc->res_pool->pg_cntl->funcs->init_pg_status) 334 313 dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl); 314 314 + 315 315 + if (dc->res_pool->pg_cntl->funcs->set_force_poweron_domain22) 316 316 + dc->res_pool->pg_cntl->funcs->set_force_poweron_domain22(dc->res_pool->pg_cntl, false); 335 317 } 336 318 } 337 319

+5

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

reviewed

··· 141 141 enum physymclk_clock_source clk_src, 142 142 bool force_enable); 143 143 144 144 + void (*set_physymclk_root_clock_gating)( 145 145 + struct dccg *dccg, 146 146 + int phy_inst, 147 147 + bool enable); 148 148 + 144 149 void (*set_dtbclk_dto)( 145 150 struct dccg *dccg, 146 151 const struct dtbclk_dto_params *params);

+2

drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h

reviewed

··· 76 76 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */ 77 77 uint8_t NUM_SLICES_4 : 1; 78 78 uint8_t NUM_SLICES_8 : 1; 79 79 + uint8_t NUM_SLICES_12 : 1; 80 80 + uint8_t NUM_SLICES_16 : 1; 79 81 } bits; 80 82 uint8_t raw; 81 83 };

+219

drivers/gpu/drm/amd/display/dc/inc/hw/optc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* 3 3 + * Copyright 2023 Advanced Micro Devices, Inc. 4 4 + * 5 5 + * Permission is hereby granted, free of charge, to any person obtaining a 6 6 + * copy of this software and associated documentation files (the "Software"), 7 7 + * to deal in the Software without restriction, including without limitation 8 8 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 9 + * and/or sell copies of the Software, and to permit persons to whom the 10 10 + * Software is furnished to do so, subject to the following conditions: 11 11 + * 12 12 + * The above copyright notice and this permission notice shall be included in 13 13 + * all copies or substantial portions of the Software. 14 14 + * 15 15 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 16 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 17 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 18 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 19 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 20 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 21 + * OTHER DEALINGS IN THE SOFTWARE. 22 22 + * 23 23 + * Authors: AMD 24 24 + * 25 25 + */ 26 26 + 27 27 + /** 28 28 + * DOC: overview 29 29 + * 30 30 + * Output Pipe Timing Combiner (OPTC) includes two major functional blocks: 31 31 + * Output Data Mapper (ODM) and Output Timing Generator (OTG). 32 32 + * 33 33 + * - ODM: It is Output Data Mapping block. It can combine input data from 34 34 + * multiple OPP data pipes into one single data stream or split data from one 35 35 + * OPP data pipe into multiple data streams or just bypass OPP data to DIO. 36 36 + * - OTG: It is Output Timing Generator. It generates display timing signals to 37 37 + * drive the display output. 38 38 + */ 39 39 + 40 40 + #ifndef __DC_OPTC_H__ 41 41 + #define __DC_OPTC_H__ 42 42 + 43 43 + #include "timing_generator.h" 44 44 + 45 45 + struct optc { 46 46 + struct timing_generator base; 47 47 + 48 48 + const struct dcn_optc_registers *tg_regs; 49 49 + const struct dcn_optc_shift *tg_shift; 50 50 + const struct dcn_optc_mask *tg_mask; 51 51 + 52 52 + int opp_count; 53 53 + 54 54 + uint32_t max_h_total; 55 55 + uint32_t max_v_total; 56 56 + 57 57 + uint32_t min_h_blank; 58 58 + 59 59 + uint32_t min_h_sync_width; 60 60 + uint32_t min_v_sync_width; 61 61 + uint32_t min_v_blank; 62 62 + uint32_t min_v_blank_interlace; 63 63 + 64 64 + int vstartup_start; 65 65 + int vupdate_offset; 66 66 + int vupdate_width; 67 67 + int vready_offset; 68 68 + struct dc_crtc_timing orginal_patched_timing; 69 69 + enum signal_type signal; 70 70 + }; 71 71 + 72 72 + struct dcn_otg_state { 73 73 + uint32_t v_blank_start; 74 74 + uint32_t v_blank_end; 75 75 + uint32_t v_sync_a_pol; 76 76 + uint32_t v_total; 77 77 + uint32_t v_total_max; 78 78 + uint32_t v_total_min; 79 79 + uint32_t v_total_min_sel; 80 80 + uint32_t v_total_max_sel; 81 81 + uint32_t v_sync_a_start; 82 82 + uint32_t v_sync_a_end; 83 83 + uint32_t h_blank_start; 84 84 + uint32_t h_blank_end; 85 85 + uint32_t h_sync_a_start; 86 86 + uint32_t h_sync_a_end; 87 87 + uint32_t h_sync_a_pol; 88 88 + uint32_t h_total; 89 89 + uint32_t underflow_occurred_status; 90 90 + uint32_t otg_enabled; 91 91 + uint32_t blank_enabled; 92 92 + uint32_t vertical_interrupt1_en; 93 93 + uint32_t vertical_interrupt1_line; 94 94 + uint32_t vertical_interrupt2_en; 95 95 + uint32_t vertical_interrupt2_line; 96 96 + }; 97 97 + 98 98 + void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s); 99 99 + 100 100 + bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing); 101 101 + 102 102 + bool optc1_validate_timing(struct timing_generator *optc, 103 103 + const struct dc_crtc_timing *timing); 104 104 + 105 105 + void optc1_program_timing(struct timing_generator *optc, 106 106 + const struct dc_crtc_timing *dc_crtc_timing, 107 107 + int vready_offset, 108 108 + int vstartup_start, 109 109 + int vupdate_offset, 110 110 + int vupdate_width, 111 111 + const enum signal_type signal, 112 112 + bool use_vbios); 113 113 + 114 114 + void optc1_setup_vertical_interrupt0(struct timing_generator *optc, 115 115 + uint32_t start_line, 116 116 + uint32_t end_line); 117 117 + 118 118 + void optc1_setup_vertical_interrupt1(struct timing_generator *optc, 119 119 + uint32_t start_line); 120 120 + 121 121 + void optc1_setup_vertical_interrupt2(struct timing_generator *optc, 122 122 + uint32_t start_line); 123 123 + 124 124 + void optc1_program_global_sync(struct timing_generator *optc, 125 125 + int vready_offset, 126 126 + int vstartup_start, 127 127 + int vupdate_offset, 128 128 + int vupdate_width); 129 129 + 130 130 + bool optc1_disable_crtc(struct timing_generator *optc); 131 131 + 132 132 + bool optc1_is_counter_moving(struct timing_generator *optc); 133 133 + 134 134 + void optc1_get_position(struct timing_generator *optc, 135 135 + struct crtc_position *position); 136 136 + 137 137 + uint32_t optc1_get_vblank_counter(struct timing_generator *optc); 138 138 + 139 139 + void optc1_get_crtc_scanoutpos(struct timing_generator *optc, 140 140 + uint32_t *v_blank_start, 141 141 + uint32_t *v_blank_end, 142 142 + uint32_t *h_position, 143 143 + uint32_t *v_position); 144 144 + 145 145 + void optc1_set_early_control(struct timing_generator *optc, 146 146 + uint32_t early_cntl); 147 147 + 148 148 + void optc1_wait_for_state(struct timing_generator *optc, 149 149 + enum crtc_state state); 150 150 + 151 151 + void optc1_set_blank(struct timing_generator *optc, 152 152 + bool enable_blanking); 153 153 + 154 154 + bool optc1_is_blanked(struct timing_generator *optc); 155 155 + 156 156 + void optc1_program_blank_color(struct timing_generator *optc, 157 157 + const struct tg_color *black_color); 158 158 + 159 159 + bool optc1_did_triggered_reset_occur(struct timing_generator *optc); 160 160 + 161 161 + void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); 162 162 + 163 163 + void optc1_disable_reset_trigger(struct timing_generator *optc); 164 164 + 165 165 + void optc1_lock(struct timing_generator *optc); 166 166 + 167 167 + void optc1_unlock(struct timing_generator *optc); 168 168 + 169 169 + void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); 170 170 + 171 171 + void optc1_set_drr(struct timing_generator *optc, 172 172 + const struct drr_params *params); 173 173 + 174 174 + void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); 175 175 + 176 176 + void optc1_set_static_screen_control(struct timing_generator *optc, 177 177 + uint32_t event_triggers, 178 178 + uint32_t num_frames); 179 179 + 180 180 + void optc1_program_stereo(struct timing_generator *optc, 181 181 + const struct dc_crtc_timing *timing, 182 182 + struct crtc_stereo_flags *flags); 183 183 + 184 184 + bool optc1_is_stereo_left_eye(struct timing_generator *optc); 185 185 + 186 186 + void optc1_clear_optc_underflow(struct timing_generator *optc); 187 187 + 188 188 + void optc1_tg_init(struct timing_generator *optc); 189 189 + 190 190 + bool optc1_is_tg_enabled(struct timing_generator *optc); 191 191 + 192 192 + bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); 193 193 + 194 194 + void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); 195 195 + 196 196 + void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable); 197 197 + 198 198 + bool optc1_get_otg_active_size(struct timing_generator *optc, 199 199 + uint32_t *otg_active_width, 200 200 + uint32_t *otg_active_height); 201 201 + 202 202 + void optc1_enable_crtc_reset(struct timing_generator *optc, 203 203 + int source_tg_inst, 204 204 + struct crtc_trigger_info *crtc_tp); 205 205 + 206 206 + bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params); 207 207 + 208 208 + bool optc1_get_crc(struct timing_generator *optc, 209 209 + uint32_t *r_cr, 210 210 + uint32_t *g_y, 211 211 + uint32_t *b_cb); 212 212 + 213 213 + bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); 214 214 + 215 215 + void optc1_set_vtg_params(struct timing_generator *optc, 216 216 + const struct dc_crtc_timing *dc_crtc_timing, 217 217 + bool program_fp2); 218 218 + 219 219 + #endif

+2

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

reviewed

··· 47 47 void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on); 48 48 void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on); 49 49 void (*init_pg_status)(struct pg_cntl *pg_cntl); 50 50 + 51 51 + void (*set_force_poweron_domain22)(struct pg_cntl *pg_cntl, bool power_on); 50 52 }; 51 53 52 54 #endif //__DC_PG_CNTL_H__

+11 -6

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

reviewed

··· 53 53 return LINK_RATE_UHBR10; 54 54 case DP_TEST_LINK_RATE_UHBR20: 55 55 return LINK_RATE_UHBR20; 56 56 + case DP_TEST_LINK_RATE_UHBR13_5_LEGACY: 56 57 case DP_TEST_LINK_RATE_UHBR13_5: 57 58 return LINK_RATE_UHBR13_5; 58 59 default: ··· 119 118 &test_rate, 120 119 1); 121 120 link_settings.link_rate = get_link_rate_from_test_link_rate(test_rate); 121 121 + 122 122 + if (link_settings.link_rate == LINK_RATE_UNKNOWN) { 123 123 + DC_LOG_ERROR("%s: Invalid test link rate.", __func__); 124 124 + ASSERT(0); 125 125 + } 122 126 123 127 /* Set preferred link settings */ 124 128 link->verified_link_cap.lane_count = link_settings.lane_count; ··· 463 457 controller_color_space = pipe_ctx->stream_res.test_pattern_params.color_space; 464 458 465 459 if (controller_color_space == CONTROLLER_DP_COLOR_SPACE_UDEFINED) { 466 466 - DC_LOG_WARNING("%s: Color space must be defined for test pattern", __func__); 460 460 + DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__); 467 461 ASSERT(0); 468 462 } 469 463 ··· 598 592 const unsigned char *p_custom_pattern, 599 593 unsigned int cust_pattern_size) 600 594 { 595 595 + const struct link_hwss *link_hwss; 601 596 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; 602 597 struct pipe_ctx *pipe_ctx = NULL; 603 598 unsigned int lane; ··· 835 828 836 829 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); 837 830 /* update MSA to requested color space */ 838 838 - pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc, 839 839 - &pipe_ctx->stream->timing, 840 840 - color_space, 841 841 - pipe_ctx->stream->use_vsc_sdp_for_colorimetry, 842 842 - link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP); 831 831 + link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 832 832 + pipe_ctx->stream->output_color_space = color_space; 833 833 + link_hwss->setup_stream_attribute(pipe_ctx); 843 834 844 835 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) { 845 836 if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)

+9 -6

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

reviewed

··· 184 184 return false; 185 185 } 186 186 187 187 - static bool handle_hpd_irq_replay_sink(struct dc_link *link) 187 187 + static void handle_hpd_irq_replay_sink(struct dc_link *link) 188 188 { 189 189 union dpcd_replay_configuration replay_configuration; 190 190 /*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR status.*/ 191 191 union psr_error_status replay_error_status; 192 192 193 193 + if (link->replay_settings.config.force_disable_desync_error_check) 194 194 + return; 195 195 + 193 196 if (!link->replay_settings.replay_feature_enabled) 194 194 - return false; 197 197 + return; 195 198 196 199 dm_helpers_dp_read_dpcd( 197 200 link->ctx, ··· 209 206 DP_PSR_ERROR_STATUS, 210 207 &replay_error_status.raw, 211 208 sizeof(replay_error_status.raw)); 209 209 + 210 210 + if (replay_configuration.bits.DESYNC_ERROR_STATUS) 211 211 + link->replay_settings.config.received_desync_error_hpd = 1; 212 212 213 213 link->replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR = 214 214 replay_error_status.bits.LINK_CRC_ERROR; ··· 249 243 edp_set_replay_allow_active(link, &allow_active, true, false, NULL); 250 244 } 251 245 } 252 252 - return true; 253 246 } 254 247 255 248 void dp_handle_link_loss(struct dc_link *link) ··· 429 424 /* PSR-related error was detected and handled */ 430 425 return true; 431 426 432 432 - if (handle_hpd_irq_replay_sink(link)) 433 433 - /* Replay-related error was detected and handled */ 434 434 - return true; 427 427 + handle_hpd_irq_replay_sink(link); 435 428 436 429 /* If PSR-related error handled, Main link may be off, 437 430 * so do not handle as a normal sink status change interrupt.

+13 -12

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

reviewed

··· 583 583 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 584 584 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 585 585 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 586 586 + uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 586 587 } bits; /**< status bits */ 587 588 uint32_t all; /**< 32-bit access to status bits */ 588 589 }; ··· 600 599 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 601 600 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 602 601 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 602 602 + DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 603 603 }; 604 604 605 605 /* Register bit definition for SCRATCH5 */ ··· 619 617 }; 620 618 621 619 enum dmub_ips_disable_type { 622 622 - DMUB_IPS_DISABLE_IPS1 = 1, 623 623 - DMUB_IPS_DISABLE_IPS2 = 2, 624 624 - DMUB_IPS_DISABLE_IPS2_Z10 = 3, 620 620 + DMUB_IPS_ENABLE = 0, 621 621 + DMUB_IPS_DISABLE_ALL = 1, 622 622 + DMUB_IPS_DISABLE_IPS1 = 2, 623 623 + DMUB_IPS_DISABLE_IPS2 = 3, 624 624 + DMUB_IPS_DISABLE_IPS2_Z10 = 4, 625 625 + DMUB_IPS_DISABLE_DYNAMIC = 5, 625 626 }; 626 627 627 628 #define DMUB_IPS1_ALLOW_MASK 0x00000001 ··· 658 653 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 659 654 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 660 655 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 661 661 - uint32_t ips_disable: 2; /* options to disable ips support*/ 662 662 - uint32_t reserved : 10; /**< reserved */ 656 656 + uint32_t ips_disable: 3; /* options to disable ips support*/ 657 657 + uint32_t reserved : 9; /**< reserved */ 663 658 } bits; /**< boot bits */ 664 659 uint32_t all; /**< 32-bit access to bits */ 665 660 }; ··· 2103 2098 /** 2104 2099 * PSR not supported. 2105 2100 */ 2106 2106 - PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 2101 2101 + PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2107 2102 }; 2108 2103 2109 2104 /** ··· 3625 3620 uint8_t pad[1]; 3626 3621 }; 3627 3622 3628 3628 - 3629 3623 /** 3630 3624 * Definition of a DMUB_CMD__ABM_PAUSE command. 3631 3625 */ ··· 4050 4046 * Definition of a DMUB_CMD__MALL command. 4051 4047 */ 4052 4048 struct dmub_rb_cmd_mall mall; 4049 4049 + 4053 4050 /** 4054 4051 * Definition of a DMUB_CMD__CAB command. 4055 4052 */ ··· 4072 4067 * Definition of DMUB_CMD__PANEL_CNTL commands. 4073 4068 */ 4074 4069 struct dmub_rb_cmd_panel_cntl panel_cntl; 4070 4070 + 4075 4071 /** 4076 4072 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4077 4073 */ ··· 4476 4470 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 4477 4471 uint8_t i; 4478 4472 4479 4479 - /* Don't remove this. 4480 4480 - * The contents need to actually be read from the ring buffer 4481 4481 - * for this function to be effective. 4482 4482 - */ 4483 4473 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4484 4474 (void)READ_ONCE(*data++); 4485 4475 ··· 4524 4522 //============================================================================== 4525 4523 //</DMUB_RB>==================================================================== 4526 4524 //============================================================================== 4527 4527 - 4528 4525 #endif /* _DMUB_CMD_H_ */

+6 -6

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

reviewed

··· 491 491 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) 492 492 { 493 493 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 494 494 - int ret = -EINVAL; 494 494 + int ret = -EOPNOTSUPP; 495 495 496 496 if (pp_funcs && pp_funcs->get_apu_thermal_limit) { 497 497 mutex_lock(&adev->pm.mutex); ··· 505 505 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) 506 506 { 507 507 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 508 508 - int ret = -EINVAL; 508 508 + int ret = -EOPNOTSUPP; 509 509 510 510 if (pp_funcs && pp_funcs->set_apu_thermal_limit) { 511 511 mutex_lock(&adev->pm.mutex); ··· 1182 1182 int ret = 0; 1183 1183 1184 1184 if (!pp_funcs->get_sclk_od) 1185 1185 - return 0; 1185 1185 + return -EOPNOTSUPP; 1186 1186 1187 1187 mutex_lock(&adev->pm.mutex); 1188 1188 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); ··· 1196 1196 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1197 1197 1198 1198 if (is_support_sw_smu(adev)) 1199 1199 - return 0; 1199 1199 + return -EOPNOTSUPP; 1200 1200 1201 1201 mutex_lock(&adev->pm.mutex); 1202 1202 if (pp_funcs->set_sclk_od) ··· 1219 1219 int ret = 0; 1220 1220 1221 1221 if (!pp_funcs->get_mclk_od) 1222 1222 - return 0; 1222 1222 + return -EOPNOTSUPP; 1223 1223 1224 1224 mutex_lock(&adev->pm.mutex); 1225 1225 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); ··· 1233 1233 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1234 1234 1235 1235 if (is_support_sw_smu(adev)) 1236 1236 - return 0; 1236 1236 + return -EOPNOTSUPP; 1237 1237 1238 1238 mutex_lock(&adev->pm.mutex); 1239 1239 if (pp_funcs->set_mclk_od)

+23 -6

drivers/gpu/drm/amd/pm/amdgpu_pm.c

reviewed

··· 989 989 * Reading back the files will show you the available power levels within 990 990 * the power state and the clock information for those levels. If deep sleep is 991 991 * applied to a clock, the level will be denoted by a special level 'S:' 992 992 - * E.g., 993 993 - * S: 19Mhz * 994 994 - * 0: 615Mhz 995 995 - * 1: 800Mhz 996 996 - * 2: 888Mhz 997 997 - * 3: 1000Mhz 992 992 + * E.g., :: 993 993 + * 994 994 + * S: 19Mhz * 995 995 + * 0: 615Mhz 996 996 + * 1: 800Mhz 997 997 + * 2: 888Mhz 998 998 + * 3: 1000Mhz 998 999 * 999 1000 * 1000 1001 * To manually adjust these states, first select manual using ··· 2197 2196 *states = ATTR_STATE_UNSUPPORTED; 2198 2197 } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) { 2199 2198 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE) 2199 2199 + *states = ATTR_STATE_UNSUPPORTED; 2200 2200 + } else if (DEVICE_ATTR_IS(pp_dpm_mclk_od)) { 2201 2201 + if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP) 2202 2202 + *states = ATTR_STATE_UNSUPPORTED; 2203 2203 + } else if (DEVICE_ATTR_IS(pp_dpm_sclk_od)) { 2204 2204 + if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP) 2205 2205 + *states = ATTR_STATE_UNSUPPORTED; 2206 2206 + } else if (DEVICE_ATTR_IS(apu_thermal_cap)) { 2207 2207 + u32 limit; 2208 2208 + 2209 2209 + if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) == 2210 2210 + -EOPNOTSUPP) 2211 2211 + *states = ATTR_STATE_UNSUPPORTED; 2212 2212 + } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { 2213 2213 + if (gc_ver == IP_VERSION(9, 4, 2) || 2214 2214 + gc_ver == IP_VERSION(9, 4, 3)) 2200 2215 *states = ATTR_STATE_UNSUPPORTED; 2201 2216 } 2202 2217

+3 -2

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

reviewed

··· 1711 1711 } 1712 1712 1713 1713 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 1714 1714 + !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 1714 1715 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1715 1716 adev->gfx.rlc.funcs->stop(adev); 1716 1717 ··· 2748 2747 2749 2748 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2750 2749 { 2751 2751 - int ret = -EINVAL; 2750 2750 + int ret = -EOPNOTSUPP; 2752 2751 struct smu_context *smu = handle; 2753 2752 2754 2753 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) ··· 2759 2758 2760 2759 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2761 2760 { 2762 2762 - int ret = -EINVAL; 2761 2761 + int ret = -EOPNOTSUPP; 2763 2762 struct smu_context *smu = handle; 2764 2763 2765 2764 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)

+159 -200

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

reviewed

··· 48 48 #include "smu_cmn.h" 49 49 #include "mp/mp_13_0_6_offset.h" 50 50 #include "mp/mp_13_0_6_sh_mask.h" 51 51 + #include "umc_v12_0.h" 51 52 52 53 #undef MP1_Public 53 54 #undef smnMP1_FIRMWARE_FLAGS ··· 95 94 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5 96 95 #define LINK_SPEED_MAX 4 97 96 98 98 - #define SMU_13_0_6_DSCLK_THRESHOLD 100 97 97 + #define SMU_13_0_6_DSCLK_THRESHOLD 140 99 98 100 99 #define MCA_BANK_IPID(_ip, _hwid, _type) \ 101 100 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, } 102 102 - 103 103 - enum mca_reg_idx { 104 104 - MCA_REG_IDX_CONTROL = 0, 105 105 - MCA_REG_IDX_STATUS = 1, 106 106 - MCA_REG_IDX_ADDR = 2, 107 107 - MCA_REG_IDX_MISC0 = 3, 108 108 - MCA_REG_IDX_CONFIG = 4, 109 109 - MCA_REG_IDX_IPID = 5, 110 110 - MCA_REG_IDX_SYND = 6, 111 111 - MCA_REG_IDX_COUNT = 16, 112 112 - }; 113 101 114 102 struct mca_bank_ipid { 115 103 enum amdgpu_mca_ip ip; ··· 112 122 int *err_code_array; 113 123 int err_code_count; 114 124 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 115 115 - enum amdgpu_mca_error_type type, int idx, uint32_t *count); 125 125 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count); 126 126 + bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 127 127 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry); 116 128 }; 117 129 118 130 #define P2S_TABLE_ID_A 0x50325341 ··· 2297 2305 struct amdgpu_device *adev = smu->adev; 2298 2306 2299 2307 if (!amdgpu_sriov_vf(adev) && adev->ras_enabled) 2300 2300 - return smu_v13_0_6_mca_set_debug_mode(smu, true); 2308 2308 + return smu_v13_0_6_mca_set_debug_mode(smu, false); 2301 2309 2302 2310 return 0; 2303 2311 } ··· 2379 2387 MCA_BANK_IPID(UMC, 0x96, 0x0), 2380 2388 MCA_BANK_IPID(SMU, 0x01, 0x1), 2381 2389 MCA_BANK_IPID(MP5, 0x01, 0x2), 2390 2390 + MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0), 2382 2391 }; 2383 2392 2384 2393 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info) ··· 2441 2448 return 0; 2442 2449 } 2443 2450 2444 2444 - static int mca_decode_mca_ipid(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, int idx, int *ip) 2451 2451 + static int mca_decode_ipid_to_hwip(uint64_t val) 2445 2452 { 2446 2453 const struct mca_bank_ipid *ipid; 2447 2447 - uint64_t val; 2448 2454 uint16_t hwid, mcatype; 2449 2449 - int i, ret; 2450 2450 - 2451 2451 - ret = mca_bank_read_reg(adev, type, idx, MCA_REG_IDX_IPID, &val); 2452 2452 - if (ret) 2453 2453 - return ret; 2455 2455 + int i; 2454 2456 2455 2457 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID); 2456 2458 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType); 2457 2459 2458 2458 - if (hwid) { 2459 2459 - for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) { 2460 2460 - ipid = &smu_v13_0_6_mca_ipid_table[i]; 2460 2460 + for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) { 2461 2461 + ipid = &smu_v13_0_6_mca_ipid_table[i]; 2461 2462 2462 2462 - if (!ipid->hwid) 2463 2463 - continue; 2463 2463 + if (!ipid->hwid) 2464 2464 + continue; 2464 2465 2465 2465 - if (ipid->hwid == hwid && ipid->mcatype == mcatype) { 2466 2466 - *ip = i; 2467 2467 - return 0; 2468 2468 - } 2469 2469 - } 2466 2466 + if (ipid->hwid == hwid && ipid->mcatype == mcatype) 2467 2467 + return i; 2470 2468 } 2471 2469 2472 2472 - *ip = AMDGPU_MCA_IP_UNKNOW; 2470 2470 + return AMDGPU_MCA_IP_UNKNOW; 2471 2471 + } 2472 2472 + 2473 2473 + static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2474 2474 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count) 2475 2475 + { 2476 2476 + uint64_t status0; 2477 2477 + 2478 2478 + status0 = entry->regs[MCA_REG_IDX_STATUS]; 2479 2479 + 2480 2480 + if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) { 2481 2481 + *count = 0; 2482 2482 + return 0; 2483 2483 + } 2484 2484 + 2485 2485 + if (type == AMDGPU_MCA_ERROR_TYPE_UE && umc_v12_0_is_uncorrectable_error(status0)) 2486 2486 + *count = 1; 2487 2487 + else if (type == AMDGPU_MCA_ERROR_TYPE_CE && umc_v12_0_is_correctable_error(status0)) 2488 2488 + *count = 1; 2473 2489 2474 2490 return 0; 2475 2491 } 2476 2492 2477 2477 - static int mca_normal_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2478 2478 - enum amdgpu_mca_error_type type, int idx, uint32_t *count) 2493 2493 + static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2494 2494 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, 2495 2495 + uint32_t *count) 2479 2496 { 2480 2480 - uint64_t status0; 2481 2481 - int ret; 2497 2497 + u32 ext_error_code; 2482 2498 2483 2483 - ret = mca_bank_read_reg(adev, type, idx, MCA_REG_IDX_STATUS, &status0); 2484 2484 - if (ret) 2485 2485 - return ret; 2499 2499 + ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]); 2486 2500 2487 2487 - if (REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) 2501 2501 + if (type == AMDGPU_MCA_ERROR_TYPE_UE && ext_error_code == 0) 2488 2502 *count = 1; 2489 2489 - else 2490 2490 - *count = 0; 2503 2503 + else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6) 2504 2504 + *count = 1; 2491 2505 2492 2506 return 0; 2493 2507 } ··· 2515 2515 return false; 2516 2516 } 2517 2517 2518 2518 - static int mca_mp5_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2519 2519 - enum amdgpu_mca_error_type type, int idx, uint32_t *count) 2518 2518 + static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2519 2519 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count) 2520 2520 { 2521 2521 - uint64_t status0 = 0, misc0 = 0; 2522 2522 - uint32_t errcode; 2523 2523 - int ret; 2521 2521 + uint64_t status0, misc0; 2524 2522 2525 2525 - if (mca_ras->ip != AMDGPU_MCA_IP_MP5) 2526 2526 - return -EINVAL; 2527 2527 - 2528 2528 - ret = mca_bank_read_reg(adev, type, idx, MCA_REG_IDX_STATUS, &status0); 2529 2529 - if (ret) 2530 2530 - return ret; 2531 2531 - 2523 2523 + status0 = entry->regs[MCA_REG_IDX_STATUS]; 2532 2524 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) { 2533 2525 *count = 0; 2534 2526 return 0; 2535 2527 } 2536 2528 2537 2537 - errcode = REG_GET_FIELD(status0, MCMP1_STATUST0, ErrorCode); 2538 2538 - if (!mca_smu_check_error_code(adev, mca_ras, errcode)) 2539 2539 - return 0; 2540 2540 - 2541 2529 if (type == AMDGPU_MCA_ERROR_TYPE_UE && 2542 2530 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 && 2543 2531 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) { 2544 2544 - if (count) 2545 2545 - *count = 1; 2532 2532 + *count = 1; 2546 2533 return 0; 2547 2547 - } 2548 2548 - 2549 2549 - ret = mca_bank_read_reg(adev, type, idx, MCA_REG_IDX_MISC0, &misc0); 2550 2550 - if (ret) 2551 2551 - return ret; 2552 2552 - 2553 2553 - if (count) 2534 2534 + } else { 2535 2535 + misc0 = entry->regs[MCA_REG_IDX_MISC0]; 2554 2536 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt); 2537 2537 + } 2555 2538 2556 2539 return 0; 2557 2540 } 2558 2541 2559 2542 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2560 2560 - enum amdgpu_mca_error_type type, int idx, uint32_t *count) 2543 2543 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count) 2561 2544 { 2562 2562 - uint64_t status0 = 0, misc0 = 0; 2563 2563 - uint32_t errcode; 2564 2564 - int ret; 2545 2545 + uint64_t status0, misc0; 2565 2546 2566 2566 - if (mca_ras->ip != AMDGPU_MCA_IP_SMU) 2567 2567 - return -EINVAL; 2568 2568 - 2569 2569 - ret = mca_bank_read_reg(adev, type, idx, MCA_REG_IDX_STATUS, &status0); 2570 2570 - if (ret) 2571 2571 - return ret; 2572 2572 - 2547 2547 + status0 = entry->regs[MCA_REG_IDX_STATUS]; 2573 2548 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) { 2574 2549 *count = 0; 2575 2550 return 0; 2576 2551 } 2577 2577 - 2578 2578 - errcode = REG_GET_FIELD(status0, MCMP1_STATUST0, ErrorCode); 2579 2579 - if (!mca_smu_check_error_code(adev, mca_ras, errcode)) 2580 2580 - return 0; 2581 2552 2582 2553 if (type == AMDGPU_MCA_ERROR_TYPE_UE && 2583 2554 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 && ··· 2558 2587 return 0; 2559 2588 } 2560 2589 2561 2561 - ret = mca_bank_read_reg(adev, type, idx, MCA_REG_IDX_MISC0, &misc0); 2562 2562 - if (ret) 2563 2563 - return ret; 2564 2564 - 2565 2565 - if (count) 2566 2566 - *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt); 2590 2590 + misc0 = entry->regs[MCA_REG_IDX_MISC0]; 2591 2591 + *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt); 2567 2592 2568 2593 return 0; 2594 2594 + } 2595 2595 + 2596 2596 + static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2597 2597 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry) 2598 2598 + { 2599 2599 + uint32_t instlo; 2600 2600 + 2601 2601 + instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo); 2602 2602 + switch (instlo) { 2603 2603 + case 0x36430400: /* SMNAID XCD 0 */ 2604 2604 + case 0x38430400: /* SMNAID XCD 1 */ 2605 2605 + case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */ 2606 2606 + return true; 2607 2607 + default: 2608 2608 + return false; 2609 2609 + } 2610 2610 + 2611 2611 + return false; 2612 2612 + }; 2613 2613 + 2614 2614 + static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev, 2615 2615 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry) 2616 2616 + { 2617 2617 + uint32_t errcode, instlo; 2618 2618 + 2619 2619 + instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo); 2620 2620 + if (instlo != 0x03b30400) 2621 2621 + return false; 2622 2622 + 2623 2623 + errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode); 2624 2624 + return mca_smu_check_error_code(adev, mca_ras, errcode); 2569 2625 } 2570 2626 2571 2627 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 }; ··· 2606 2608 { 2607 2609 .blkid = AMDGPU_RAS_BLOCK__UMC, 2608 2610 .ip = AMDGPU_MCA_IP_UMC, 2609 2609 - .get_err_count = mca_normal_mca_get_err_count, 2611 2611 + .get_err_count = mca_umc_mca_get_err_count, 2610 2612 }, { 2611 2613 .blkid = AMDGPU_RAS_BLOCK__GFX, 2612 2612 - .ip = AMDGPU_MCA_IP_MP5, 2613 2613 - .get_err_count = mca_mp5_mca_get_err_count, 2614 2614 + .ip = AMDGPU_MCA_IP_SMU, 2615 2615 + .get_err_count = mca_gfx_mca_get_err_count, 2616 2616 + .bank_is_valid = mca_gfx_smu_bank_is_valid, 2614 2617 }, { 2615 2618 .blkid = AMDGPU_RAS_BLOCK__SDMA, 2616 2619 .ip = AMDGPU_MCA_IP_SMU, 2617 2620 .err_code_array = sdma_err_codes, 2618 2621 .err_code_count = ARRAY_SIZE(sdma_err_codes), 2619 2622 .get_err_count = mca_smu_mca_get_err_count, 2623 2623 + .bank_is_valid = mca_smu_bank_is_valid, 2620 2624 }, { 2621 2625 .blkid = AMDGPU_RAS_BLOCK__MMHUB, 2622 2626 .ip = AMDGPU_MCA_IP_SMU, 2623 2627 .err_code_array = mmhub_err_codes, 2624 2628 .err_code_count = ARRAY_SIZE(mmhub_err_codes), 2625 2629 .get_err_count = mca_smu_mca_get_err_count, 2630 2630 + .bank_is_valid = mca_smu_bank_is_valid, 2631 2631 + }, { 2632 2632 + .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL, 2633 2633 + .ip = AMDGPU_MCA_IP_PCS_XGMI, 2634 2634 + .get_err_count = mca_pcs_xgmi_mca_get_err_count, 2626 2635 }, 2627 2636 }; 2628 2637 ··· 2664 2659 } 2665 2660 2666 2661 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras, 2667 2667 - enum amdgpu_mca_error_type type, int idx) 2662 2662 + enum amdgpu_mca_error_type type, struct mca_bank_entry *entry) 2668 2663 { 2669 2669 - int ret, ip = AMDGPU_MCA_IP_UNKNOW; 2670 2670 - 2671 2671 - ret = mca_decode_mca_ipid(adev, type, idx, &ip); 2672 2672 - if (ret) 2664 2664 + if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip) 2673 2665 return false; 2674 2666 2675 2675 - if (ip == AMDGPU_MCA_IP_UNKNOW) 2676 2676 - return false; 2667 2667 + if (mca_ras->bank_is_valid) 2668 2668 + return mca_ras->bank_is_valid(mca_ras, adev, type, entry); 2677 2669 2678 2678 - return ip == mca_ras->ip; 2670 2670 + return true; 2679 2671 } 2680 2672 2681 2681 - static int mca_get_valid_mca_idx(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras, 2682 2682 - enum amdgpu_mca_error_type type, 2683 2683 - uint32_t mca_cnt, int *idx_array, int idx_array_size) 2673 2673 + static int __mca_smu_get_ras_mca_set(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras, 2674 2674 + enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set) 2684 2675 { 2685 2685 - int i, idx_cnt = 0; 2686 2686 - 2687 2687 - for (i = 0; i < mca_cnt; i++) { 2688 2688 - if (!mca_bank_is_valid(adev, mca_ras, type, i)) 2689 2689 - continue; 2690 2690 - 2691 2691 - if (idx_array) { 2692 2692 - if (idx_cnt < idx_array_size) 2693 2693 - idx_array[idx_cnt] = i; 2694 2694 - else 2695 2695 - return -EINVAL; 2696 2696 - } 2697 2697 - 2698 2698 - idx_cnt++; 2699 2699 - } 2700 2700 - 2701 2701 - return idx_cnt; 2702 2702 - } 2703 2703 - 2704 2704 - static int __mca_smu_get_error_count(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras, enum amdgpu_mca_error_type type, uint32_t *count) 2705 2705 - { 2706 2706 - uint32_t result, mca_cnt, total = 0; 2707 2707 - int idx_array[16]; 2708 2708 - int i, ret, idx_cnt = 0; 2676 2676 + struct mca_bank_entry entry; 2677 2677 + uint32_t mca_cnt; 2678 2678 + int i, ret; 2709 2679 2710 2680 ret = mca_get_valid_mca_count(adev, type, &mca_cnt); 2711 2681 if (ret) 2712 2682 return ret; 2713 2683 2714 2684 /* if valid mca bank count is 0, the driver can return 0 directly */ 2715 2715 - if (!mca_cnt) { 2685 2685 + if (!mca_cnt) 2686 2686 + return 0; 2687 2687 + 2688 2688 + for (i = 0; i < mca_cnt; i++) { 2689 2689 + memset(&entry, 0, sizeof(entry)); 2690 2690 + ret = mca_get_mca_entry(adev, type, i, &entry); 2691 2691 + if (ret) 2692 2692 + return ret; 2693 2693 + 2694 2694 + if (mca_ras && !mca_bank_is_valid(adev, mca_ras, type, &entry)) 2695 2695 + continue; 2696 2696 + 2697 2697 + ret = amdgpu_mca_bank_set_add_entry(mca_set, &entry); 2698 2698 + if (ret) 2699 2699 + return ret; 2700 2700 + } 2701 2701 + 2702 2702 + return 0; 2703 2703 + } 2704 2704 + 2705 2705 + static int mca_smu_get_ras_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 2706 2706 + enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set) 2707 2707 + { 2708 2708 + const struct mca_ras_info *mca_ras = NULL; 2709 2709 + 2710 2710 + if (!mca_set) 2711 2711 + return -EINVAL; 2712 2712 + 2713 2713 + if (blk != AMDGPU_RAS_BLOCK_COUNT) { 2714 2714 + mca_ras = mca_get_mca_ras_info(adev, blk); 2715 2715 + if (!mca_ras) 2716 2716 + return -EOPNOTSUPP; 2717 2717 + } 2718 2718 + 2719 2719 + return __mca_smu_get_ras_mca_set(adev, mca_ras, type, mca_set); 2720 2720 + } 2721 2721 + 2722 2722 + static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, 2723 2723 + struct mca_bank_entry *entry, uint32_t *count) 2724 2724 + { 2725 2725 + const struct mca_ras_info *mca_ras; 2726 2726 + 2727 2727 + if (!entry || !count) 2728 2728 + return -EINVAL; 2729 2729 + 2730 2730 + mca_ras = mca_get_mca_ras_info(adev, blk); 2731 2731 + if (!mca_ras) 2732 2732 + return -EOPNOTSUPP; 2733 2733 + 2734 2734 + if (!mca_bank_is_valid(adev, mca_ras, type, entry)) { 2716 2735 *count = 0; 2717 2736 return 0; 2718 2737 } 2719 2738 2720 2720 - if (!mca_ras->get_err_count) 2721 2721 - return -EINVAL; 2722 2722 - 2723 2723 - idx_cnt = mca_get_valid_mca_idx(adev, mca_ras, type, mca_cnt, idx_array, ARRAY_SIZE(idx_array)); 2724 2724 - if (idx_cnt < 0) 2725 2725 - return -EINVAL; 2726 2726 - 2727 2727 - for (i = 0; i < idx_cnt; i++) { 2728 2728 - result = 0; 2729 2729 - ret = mca_ras->get_err_count(mca_ras, adev, type, idx_array[i], &result); 2730 2730 - if (ret) 2731 2731 - return ret; 2732 2732 - 2733 2733 - total += result; 2734 2734 - } 2735 2735 - 2736 2736 - *count = total; 2737 2737 - 2738 2738 - return 0; 2739 2739 - } 2740 2740 - 2741 2741 - static int mca_smu_get_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 2742 2742 - enum amdgpu_mca_error_type type, uint32_t *count) 2743 2743 - { 2744 2744 - const struct mca_ras_info *mca_ras; 2745 2745 - 2746 2746 - if (!count) 2747 2747 - return -EINVAL; 2748 2748 - 2749 2749 - mca_ras = mca_get_mca_ras_info(adev, blk); 2750 2750 - if (!mca_ras) 2751 2751 - return -EOPNOTSUPP; 2752 2752 - 2753 2753 - return __mca_smu_get_error_count(adev, mca_ras, type, count); 2754 2754 - } 2755 2755 - 2756 2756 - static int __mca_smu_get_ras_mca_idx_array(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras, 2757 2757 - enum amdgpu_mca_error_type type, int *idx_array, int *idx_array_size) 2758 2758 - { 2759 2759 - uint32_t mca_cnt = 0; 2760 2760 - int ret, idx_cnt = 0; 2761 2761 - 2762 2762 - ret = mca_get_valid_mca_count(adev, type, &mca_cnt); 2763 2763 - if (ret) 2764 2764 - return ret; 2765 2765 - 2766 2766 - /* if valid mca bank count is 0, the driver can return 0 directly */ 2767 2767 - if (!mca_cnt) { 2768 2768 - *idx_array_size = 0; 2769 2769 - return 0; 2770 2770 - } 2771 2771 - 2772 2772 - idx_cnt = mca_get_valid_mca_idx(adev, mca_ras, type, mca_cnt, idx_array, *idx_array_size); 2773 2773 - if (idx_cnt < 0) 2774 2774 - return -EINVAL; 2775 2775 - 2776 2776 - *idx_array_size = idx_cnt; 2777 2777 - 2778 2778 - return 0; 2779 2779 - } 2780 2780 - 2781 2781 - static int mca_smu_get_ras_mca_idx_array(struct amdgpu_device *adev, enum amdgpu_ras_block blk, 2782 2782 - enum amdgpu_mca_error_type type, int *idx_array, int *idx_array_size) 2783 2783 - { 2784 2784 - const struct mca_ras_info *mca_ras; 2785 2785 - 2786 2786 - mca_ras = mca_get_mca_ras_info(adev, blk); 2787 2787 - if (!mca_ras) 2788 2788 - return -EOPNOTSUPP; 2789 2789 - 2790 2790 - return __mca_smu_get_ras_mca_idx_array(adev, mca_ras, type, idx_array, idx_array_size); 2739 2739 + return mca_ras->get_err_count(mca_ras, adev, type, entry, count); 2791 2740 } 2792 2741 2793 2742 static int mca_smu_get_mca_entry(struct amdgpu_device *adev, ··· 2760 2801 .max_ue_count = 12, 2761 2802 .max_ce_count = 12, 2762 2803 .mca_set_debug_mode = mca_smu_set_debug_mode, 2763 2763 - .mca_get_error_count = mca_smu_get_error_count, 2804 2804 + .mca_get_ras_mca_set = mca_smu_get_ras_mca_set, 2805 2805 + .mca_parse_mca_error_count = mca_smu_parse_mca_error_count, 2764 2806 .mca_get_mca_entry = mca_smu_get_mca_entry, 2765 2807 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count, 2766 2766 - .mca_get_ras_mca_idx_array = mca_smu_get_ras_mca_idx_array, 2767 2808 }; 2768 2809 2769 2810 static int smu_v13_0_6_select_xgmi_plpd_policy(struct smu_context *smu,

+2 -1

drivers/gpu/drm/drm_syncobj.c

reviewed

··· 1069 1069 fence = drm_syncobj_fence_get(syncobjs[i]); 1070 1070 if (!fence || dma_fence_chain_find_seqno(&fence, points[i])) { 1071 1071 dma_fence_put(fence); 1072 1072 - if (flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT) { 1072 1072 + if (flags & (DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT | 1073 1073 + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE)) { 1073 1074 continue; 1074 1075 } else { 1075 1076 timeout = -EINVAL;

+12

drivers/gpu/drm/i915/display/intel_cdclk.c

reviewed

··· 2750 2750 for_each_pipe(dev_priv, pipe) 2751 2751 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2752 2752 2753 2753 + /* 2754 2754 + * Avoid glk_force_audio_cdclk() causing excessive screen 2755 2755 + * blinking when multiple pipes are active by making sure 2756 2756 + * CDCLK frequency is always high enough for audio. With a 2757 2757 + * single active pipe we can always change CDCLK frequency 2758 2758 + * by changing the cd2x divider (see glk_cdclk_table[]) and 2759 2759 + * thus a full modeset won't be needed then. 2760 2760 + */ 2761 2761 + if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2762 2762 + !is_power_of_2(cdclk_state->active_pipes)) 2763 2763 + min_cdclk = max(2 * 96000, min_cdclk); 2764 2764 + 2753 2765 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2754 2766 drm_dbg_kms(&dev_priv->drm, 2755 2767 "required cdclk (%d kHz) exceeds max (%d kHz)\n",

+1 -1

drivers/gpu/drm/i915/display/intel_dp.c

reviewed

··· 430 430 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 431 431 432 432 if (intel_is_c10phy(i915, phy)) 433 433 - return intel_dp_is_edp(intel_dp) ? 675000 : 810000; 433 433 + return 810000; 434 434 435 435 return 2000000; 436 436 }

+8 -3

drivers/gpu/drm/i915/display/intel_tc.c

reviewed

··· 58 58 struct delayed_work link_reset_work; 59 59 int link_refcount; 60 60 bool legacy_port:1; 61 61 - char port_name[8]; 61 61 + const char *port_name; 62 62 enum tc_port_mode mode; 63 63 enum tc_port_mode init_mode; 64 64 enum phy_fia phy_fia; ··· 1875 1875 else 1876 1876 tc->phy_ops = &icl_tc_phy_ops; 1877 1877 1878 1878 - snprintf(tc->port_name, sizeof(tc->port_name), 1879 1879 - "%c/TC#%d", port_name(port), tc_port + 1); 1878 1878 + tc->port_name = kasprintf(GFP_KERNEL, "%c/TC#%d", port_name(port), 1879 1879 + tc_port + 1); 1880 1880 + if (!tc->port_name) { 1881 1881 + kfree(tc); 1882 1882 + return -ENOMEM; 1883 1883 + } 1880 1884 1881 1885 mutex_init(&tc->lock); 1882 1886 /* TODO: Combine the two works */ ··· 1901 1897 { 1902 1898 intel_tc_port_suspend(dig_port); 1903 1899 1900 1900 + kfree(dig_port->tc->port_name); 1904 1901 kfree(dig_port->tc); 1905 1902 dig_port->tc = NULL; 1906 1903 }

+1

drivers/gpu/drm/i915/gem/i915_gem_context.c

reviewed

··· 844 844 if (idx >= pc->num_user_engines) 845 845 return -EINVAL; 846 846 847 847 + idx = array_index_nospec(idx, pc->num_user_engines); 847 848 pe = &pc->user_engines[idx]; 848 849 849 850 /* Only render engine supports RPCS configuration. */

+24 -11

drivers/gpu/drm/i915/gt/intel_ggtt.c

reviewed

··· 195 195 spin_unlock_irq(&uncore->lock); 196 196 } 197 197 198 198 + static bool needs_wc_ggtt_mapping(struct drm_i915_private *i915) 199 199 + { 200 200 + /* 201 201 + * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range 202 202 + * will be dropped. For WC mappings in general we have 64 byte burst 203 203 + * writes when the WC buffer is flushed, so we can't use it, but have to 204 204 + * resort to an uncached mapping. The WC issue is easily caught by the 205 205 + * readback check when writing GTT PTE entries. 206 206 + */ 207 207 + if (!IS_GEN9_LP(i915) && GRAPHICS_VER(i915) < 11) 208 208 + return true; 209 209 + 210 210 + return false; 211 211 + } 212 212 + 198 213 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt) 199 214 { 200 215 struct intel_uncore *uncore = ggtt->vm.gt->uncore; ··· 217 202 /* 218 203 * Note that as an uncached mmio write, this will flush the 219 204 * WCB of the writes into the GGTT before it triggers the invalidate. 205 205 + * 206 206 + * Only perform this when GGTT is mapped as WC, see ggtt_probe_common(). 220 207 */ 221 221 - intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 208 208 + if (needs_wc_ggtt_mapping(ggtt->vm.i915)) 209 209 + intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, 210 210 + GFX_FLSH_CNTL_EN); 222 211 } 223 212 224 213 static void guc_ggtt_ct_invalidate(struct intel_gt *gt) ··· 1159 1140 GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); 1160 1141 phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915); 1161 1142 1162 1162 - /* 1163 1163 - * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range 1164 1164 - * will be dropped. For WC mappings in general we have 64 byte burst 1165 1165 - * writes when the WC buffer is flushed, so we can't use it, but have to 1166 1166 - * resort to an uncached mapping. The WC issue is easily caught by the 1167 1167 - * readback check when writing GTT PTE entries. 1168 1168 - */ 1169 1169 - if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11) 1170 1170 - ggtt->gsm = ioremap(phys_addr, size); 1171 1171 - else 1143 1143 + if (needs_wc_ggtt_mapping(i915)) 1172 1144 ggtt->gsm = ioremap_wc(phys_addr, size); 1145 1145 + else 1146 1146 + ggtt->gsm = ioremap(phys_addr, size); 1147 1147 + 1173 1148 if (!ggtt->gsm) { 1174 1149 drm_err(&i915->drm, "Failed to map the ggtt page table\n"); 1175 1150 return -ENOMEM;

+10 -6

drivers/gpu/drm/i915/gt/intel_rc6.c

reviewed

··· 581 581 582 582 static void rc6_res_reg_init(struct intel_rc6 *rc6) 583 583 { 584 584 - memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg)); 584 584 + i915_reg_t res_reg[INTEL_RC6_RES_MAX] = { 585 585 + [0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG, 586 586 + }; 585 587 586 588 switch (rc6_to_gt(rc6)->type) { 587 589 case GT_MEDIA: 588 588 - rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6; 590 590 + res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6; 589 591 break; 590 592 default: 591 591 - rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; 592 592 - rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; 593 593 - rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; 594 594 - rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; 593 593 + res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; 594 594 + res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; 595 595 + res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; 596 596 + res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; 595 597 break; 596 598 } 599 599 + 600 600 + memcpy(rc6->res_reg, res_reg, sizeof(res_reg)); 597 601 } 598 602 599 603 void intel_rc6_init(struct intel_rc6 *rc6)

+6 -3

drivers/gpu/drm/i915/i915_debugfs_params.c

reviewed

··· 38 38 39 39 static int notify_guc(struct drm_i915_private *i915) 40 40 { 41 41 - int ret = 0; 41 41 + struct intel_gt *gt; 42 42 + int i, ret = 0; 42 43 43 43 - if (intel_uc_uses_guc_submission(&to_gt(i915)->uc)) 44 44 - ret = intel_guc_global_policies_update(&to_gt(i915)->uc.guc); 44 44 + for_each_gt(gt, i915, i) { 45 45 + if (intel_uc_uses_guc_submission(&gt->uc)) 46 46 + ret = intel_guc_global_policies_update(&gt->uc.guc); 47 47 + } 45 48 46 49 return ret; 47 50 }

+3 -12

drivers/gpu/drm/i915/i915_perf.c

reviewed

··· 4227 4227 u32 known_open_flags; 4228 4228 int ret; 4229 4229 4230 4230 - if (!perf->i915) { 4231 4231 - drm_dbg(&perf->i915->drm, 4232 4232 - "i915 perf interface not available for this system\n"); 4230 4230 + if (!perf->i915) 4233 4231 return -ENOTSUPP; 4234 4234 - } 4235 4232 4236 4233 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC | 4237 4234 I915_PERF_FLAG_FD_NONBLOCK | ··· 4604 4607 struct i915_oa_reg *regs; 4605 4608 int err, id; 4606 4609 4607 4607 - if (!perf->i915) { 4608 4608 - drm_dbg(&perf->i915->drm, 4609 4609 - "i915 perf interface not available for this system\n"); 4610 4610 + if (!perf->i915) 4610 4611 return -ENOTSUPP; 4611 4611 - } 4612 4612 4613 4613 if (!perf->metrics_kobj) { 4614 4614 drm_dbg(&perf->i915->drm, ··· 4767 4773 struct i915_oa_config *oa_config; 4768 4774 int ret; 4769 4775 4770 4770 - if (!perf->i915) { 4771 4771 - drm_dbg(&perf->i915->drm, 4772 4772 - "i915 perf interface not available for this system\n"); 4776 4776 + if (!perf->i915) 4773 4777 return -ENOTSUPP; 4774 4774 - } 4775 4778 4776 4779 if (i915_perf_stream_paranoid && !perfmon_capable()) { 4777 4780 drm_dbg(&perf->i915->drm,

+3

drivers/gpu/drm/qxl/qxl_display.c

reviewed

··· 1229 1229 if (!qdev->monitors_config_bo) 1230 1230 return 0; 1231 1231 1232 1232 + kfree(qdev->dumb_heads); 1233 1233 + qdev->dumb_heads = NULL; 1234 1234 + 1232 1235 qdev->monitors_config = NULL; 1233 1236 qdev->ram_header->monitors_config = 0; 1234 1237

+1 -1

drivers/gpu/drm/vc4/tests/vc4_mock_crtc.c

reviewed

··· 26 26 struct vc4_crtc *vc4_crtc; 27 27 int ret; 28 28 29 29 - dummy_crtc = kunit_kzalloc(test, sizeof(*dummy_crtc), GFP_KERNEL); 29 29 + dummy_crtc = drmm_kzalloc(drm, sizeof(*dummy_crtc), GFP_KERNEL); 30 30 KUNIT_ASSERT_NOT_NULL(test, dummy_crtc); 31 31 32 32 vc4_crtc = &dummy_crtc->crtc;

+1 -1

drivers/gpu/drm/vc4/tests/vc4_mock_output.c

reviewed

··· 32 32 struct drm_encoder *enc; 33 33 int ret; 34 34 35 35 - dummy_output = kunit_kzalloc(test, sizeof(*dummy_output), GFP_KERNEL); 35 35 + dummy_output = drmm_kzalloc(drm, sizeof(*dummy_output), GFP_KERNEL); 36 36 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, dummy_output); 37 37 dummy_output->encoder.type = vc4_encoder_type; 38 38