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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
Add device tree bindings for IPQ5210 TLMM block.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
authored by
Kathiravan Thirumoorthy
and committed by
Linus Walleij
c0dd33f0
0720208b
+123
+123
Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
+123
Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ5210 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,ipq5210-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 27
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gpio-line-names:
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maxItems: 54
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-ipq5210-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-ipq5210-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-ipq5210-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char_start, atest_char_status0, atest_char_status1,
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atest_char_status2, atest_char_status3, atest_tic_en, audio_pri,
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audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1,
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audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2,
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audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec,
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audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1,
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audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2,
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audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0,
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cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out,
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gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0,
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led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst,
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mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n,
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pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test,
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pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx,
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pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los,
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gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0,
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pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
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qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
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qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
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qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
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qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2,
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qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2,
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qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1,
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rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5210-tlmm";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <0x2>;
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gpio-ranges = <&tlmm 0 0 54>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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qup-uart1-default-state {
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pins = "gpio38", "gpio39";
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function = "qup_se1";
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drive-strength = <6>;
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bias-pull-down;
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};
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};