tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

powerpc/perf: Add generic and cache event list for power10 DD1

There are event code updates for some of the generic events
and cache events for power10. Inorder to maintain the current
event codes work with DD1 also, create a new array of generic_events,
cache_events and pmu_attr_groups with suffix _dd1, example,
power10_events_attr_dd1. So that further updates to event codes
can be made in the original list, ie, power10_events_attr. Update the
power10 pmu init code to pick the dd1 list while registering
the power PMU, based on the pvr (Processor Version Register) value.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-5-git-send-email-atrajeev@linux.vnet.ibm.com

authored by

Athira Rajeev and committed by
Michael Ellerman c0e39857 0263bbb3

+152
+152
arch/powerpc/perf/power10-pmu.c
··· 129 129 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 130 130 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 131 131 132 + static struct attribute *power10_events_attr_dd1[] = { 133 + GENERIC_EVENT_PTR(PM_RUN_CYC), 134 + GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), 135 + GENERIC_EVENT_PTR(PM_BR_CMPL), 136 + GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 137 + GENERIC_EVENT_PTR(PM_LD_REF_L1), 138 + GENERIC_EVENT_PTR(PM_LD_MISS_L1), 139 + GENERIC_EVENT_PTR(MEM_LOADS), 140 + GENERIC_EVENT_PTR(MEM_STORES), 141 + CACHE_EVENT_PTR(PM_LD_MISS_L1), 142 + CACHE_EVENT_PTR(PM_LD_REF_L1), 143 + CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS), 144 + CACHE_EVENT_PTR(PM_ST_MISS_L1), 145 + CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 146 + CACHE_EVENT_PTR(PM_INST_FROM_L1), 147 + CACHE_EVENT_PTR(PM_IC_PREF_REQ), 148 + CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 149 + CACHE_EVENT_PTR(PM_DATA_FROM_L3), 150 + CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 151 + CACHE_EVENT_PTR(PM_BR_CMPL), 152 + CACHE_EVENT_PTR(PM_DTLB_MISS), 153 + CACHE_EVENT_PTR(PM_ITLB_MISS), 154 + NULL 155 + }; 156 + 132 157 static struct attribute *power10_events_attr[] = { 133 158 GENERIC_EVENT_PTR(PM_RUN_CYC), 134 159 GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), ··· 177 152 CACHE_EVENT_PTR(PM_DTLB_MISS), 178 153 CACHE_EVENT_PTR(PM_ITLB_MISS), 179 154 NULL 155 + }; 156 + 157 + static struct attribute_group power10_pmu_events_group_dd1 = { 158 + .name = "events", 159 + .attrs = power10_events_attr_dd1, 180 160 }; 181 161 182 162 static struct attribute_group power10_pmu_events_group = { ··· 235 205 .attrs = power10_pmu_format_attr, 236 206 }; 237 207 208 + static const struct attribute_group *power10_pmu_attr_groups_dd1[] = { 209 + &power10_pmu_format_group, 210 + &power10_pmu_events_group_dd1, 211 + NULL, 212 + }; 213 + 238 214 static const struct attribute_group *power10_pmu_attr_groups[] = { 239 215 &power10_pmu_format_group, 240 216 &power10_pmu_events_group, 241 217 NULL, 218 + }; 219 + 220 + static int power10_generic_events_dd1[] = { 221 + [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC, 222 + [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL, 223 + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 224 + [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 225 + [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 226 + [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 242 227 }; 243 228 244 229 static int power10_generic_events[] = { ··· 321 276 * 0 means not supported, -1 means nonsensical, other values 322 277 * are event codes. 323 278 */ 279 + static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 280 + [C(L1D)] = { 281 + [C(OP_READ)] = { 282 + [C(RESULT_ACCESS)] = PM_LD_REF_L1, 283 + [C(RESULT_MISS)] = PM_LD_MISS_L1, 284 + }, 285 + [C(OP_WRITE)] = { 286 + [C(RESULT_ACCESS)] = 0, 287 + [C(RESULT_MISS)] = PM_ST_MISS_L1, 288 + }, 289 + [C(OP_PREFETCH)] = { 290 + [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS, 291 + [C(RESULT_MISS)] = 0, 292 + }, 293 + }, 294 + [C(L1I)] = { 295 + [C(OP_READ)] = { 296 + [C(RESULT_ACCESS)] = PM_INST_FROM_L1, 297 + [C(RESULT_MISS)] = PM_L1_ICACHE_MISS, 298 + }, 299 + [C(OP_WRITE)] = { 300 + [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS, 301 + [C(RESULT_MISS)] = -1, 302 + }, 303 + [C(OP_PREFETCH)] = { 304 + [C(RESULT_ACCESS)] = PM_IC_PREF_REQ, 305 + [C(RESULT_MISS)] = 0, 306 + }, 307 + }, 308 + [C(LL)] = { 309 + [C(OP_READ)] = { 310 + [C(RESULT_ACCESS)] = PM_DATA_FROM_L3, 311 + [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, 312 + }, 313 + [C(OP_WRITE)] = { 314 + [C(RESULT_ACCESS)] = -1, 315 + [C(RESULT_MISS)] = -1, 316 + }, 317 + [C(OP_PREFETCH)] = { 318 + [C(RESULT_ACCESS)] = -1, 319 + [C(RESULT_MISS)] = 0, 320 + }, 321 + }, 322 + [C(DTLB)] = { 323 + [C(OP_READ)] = { 324 + [C(RESULT_ACCESS)] = 0, 325 + [C(RESULT_MISS)] = PM_DTLB_MISS, 326 + }, 327 + [C(OP_WRITE)] = { 328 + [C(RESULT_ACCESS)] = -1, 329 + [C(RESULT_MISS)] = -1, 330 + }, 331 + [C(OP_PREFETCH)] = { 332 + [C(RESULT_ACCESS)] = -1, 333 + [C(RESULT_MISS)] = -1, 334 + }, 335 + }, 336 + [C(ITLB)] = { 337 + [C(OP_READ)] = { 338 + [C(RESULT_ACCESS)] = 0, 339 + [C(RESULT_MISS)] = PM_ITLB_MISS, 340 + }, 341 + [C(OP_WRITE)] = { 342 + [C(RESULT_ACCESS)] = -1, 343 + [C(RESULT_MISS)] = -1, 344 + }, 345 + [C(OP_PREFETCH)] = { 346 + [C(RESULT_ACCESS)] = -1, 347 + [C(RESULT_MISS)] = -1, 348 + }, 349 + }, 350 + [C(BPU)] = { 351 + [C(OP_READ)] = { 352 + [C(RESULT_ACCESS)] = PM_BR_CMPL, 353 + [C(RESULT_MISS)] = PM_BR_MPRED_CMPL, 354 + }, 355 + [C(OP_WRITE)] = { 356 + [C(RESULT_ACCESS)] = -1, 357 + [C(RESULT_MISS)] = -1, 358 + }, 359 + [C(OP_PREFETCH)] = { 360 + [C(RESULT_ACCESS)] = -1, 361 + [C(RESULT_MISS)] = -1, 362 + }, 363 + }, 364 + [C(NODE)] = { 365 + [C(OP_READ)] = { 366 + [C(RESULT_ACCESS)] = -1, 367 + [C(RESULT_MISS)] = -1, 368 + }, 369 + [C(OP_WRITE)] = { 370 + [C(RESULT_ACCESS)] = -1, 371 + [C(RESULT_MISS)] = -1, 372 + }, 373 + [C(OP_PREFETCH)] = { 374 + [C(RESULT_ACCESS)] = -1, 375 + [C(RESULT_MISS)] = -1, 376 + }, 377 + }, 378 + }; 379 + 324 380 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 325 381 [C(L1D)] = { 326 382 [C(OP_READ)] = { ··· 567 421 568 422 /* Set the PERF_REG_EXTENDED_MASK here */ 569 423 PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31; 424 + 425 + if ((PVR_CFG(pvr) == 1)) { 426 + power10_pmu.generic_events = power10_generic_events_dd1; 427 + power10_pmu.attr_groups = power10_pmu_attr_groups_dd1; 428 + power10_pmu.cache_events = &power10_cache_events_dd1; 429 + } 570 430 571 431 rc = register_power_pmu(&power10_pmu); 572 432 if (rc)