Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_urgent_for_v5.15_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Borislav Petkov:
- A FPU fix to properly handle invalid MXCSR values: 32-bit masks them
out due to historical reasons and 64-bit kernels reject them
- A fix to clear X86_FEATURE_SMAP when support for is not
config-enabled
- Three fixes correcting misspelled Kconfig symbols used in code
- Two resctrl object cleanup fixes
- Yet another attempt at fixing the neverending saga of botched x86
timers, this time because some incredibly smart hardware decides to
turn off the HPET timer in a low power state - who cares if the OS is
relying on it...
- Check the full return value range of an SEV VMGEXIT call to determine
whether it returned an error
* tag 'x86_urgent_for_v5.15_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/fpu: Restore the masking out of reserved MXCSR bits
x86/Kconfig: Correct reference to MWINCHIP3D
x86/platform/olpc: Correct ifdef symbol to intended CONFIG_OLPC_XO15_SCI
x86/entry: Clear X86_FEATURE_SMAP when CONFIG_X86_SMAP=n
x86/entry: Correct reference to intended CONFIG_64_BIT
x86/resctrl: Fix kfree() of the wrong type in domain_add_cpu()
x86/resctrl: Free the ctrlval arrays when domain_setup_mon_state() fails
x86/hpet: Use another crystalball to evaluate HPET usability
x86/sev: Return an error on a returned non-zero SW_EXITINFO1[31:0]
+99
-14
+1
-1
arch/x86/Kconfig
+1
-1
arch/x86/Kconfig
···
1405
1405
1406
1406
config HIGHMEM64G
1407
1407
bool "64GB"
1408
-
depends on !M486SX && !M486 && !M586 && !M586TSC && !M586MMX && !MGEODE_LX && !MGEODEGX1 && !MCYRIXIII && !MELAN && !MWINCHIPC6 && !WINCHIP3D && !MK6
1408
+
depends on !M486SX && !M486 && !M586 && !M586TSC && !M586MMX && !MGEODE_LX && !MGEODEGX1 && !MCYRIXIII && !MELAN && !MWINCHIPC6 && !MWINCHIP3D && !MK6
1409
1409
select X86_PAE
1410
1410
help
1411
1411
Select this if you have a 32-bit processor and more than 4
+1
-1
arch/x86/include/asm/entry-common.h
+1
-1
arch/x86/include/asm/entry-common.h
···
25
25
* For !SMAP hardware we patch out CLAC on entry.
26
26
*/
27
27
if (boot_cpu_has(X86_FEATURE_SMAP) ||
28
-
(IS_ENABLED(CONFIG_64_BIT) && boot_cpu_has(X86_FEATURE_XENPV)))
28
+
(IS_ENABLED(CONFIG_64BIT) && boot_cpu_has(X86_FEATURE_XENPV)))
29
29
mask |= X86_EFLAGS_AC;
30
30
31
31
WARN_ON_ONCE(flags & mask);
+1
arch/x86/kernel/cpu/common.c
+1
arch/x86/kernel/cpu/common.c
+4
-2
arch/x86/kernel/cpu/resctrl/core.c
+4
-2
arch/x86/kernel/cpu/resctrl/core.c
···
527
527
rdt_domain_reconfigure_cdp(r);
528
528
529
529
if (r->alloc_capable && domain_setup_ctrlval(r, d)) {
530
-
kfree(d);
530
+
kfree(hw_dom);
531
531
return;
532
532
}
533
533
534
534
if (r->mon_capable && domain_setup_mon_state(r, d)) {
535
-
kfree(d);
535
+
kfree(hw_dom->ctrl_val);
536
+
kfree(hw_dom->mbps_val);
537
+
kfree(hw_dom);
536
538
return;
537
539
}
538
540
-6
arch/x86/kernel/early-quirks.c
-6
arch/x86/kernel/early-quirks.c
···
714
714
*/
715
715
{ PCI_VENDOR_ID_INTEL, 0x0f00,
716
716
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
717
-
{ PCI_VENDOR_ID_INTEL, 0x3e20,
718
-
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
719
-
{ PCI_VENDOR_ID_INTEL, 0x3ec4,
720
-
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
721
-
{ PCI_VENDOR_ID_INTEL, 0x8a12,
722
-
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
723
717
{ PCI_VENDOR_ID_BROADCOM, 0x4331,
724
718
PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
725
719
{}
+8
-3
arch/x86/kernel/fpu/signal.c
+8
-3
arch/x86/kernel/fpu/signal.c
···
379
379
sizeof(fpu->state.fxsave)))
380
380
return -EFAULT;
381
381
382
-
/* Reject invalid MXCSR values. */
383
-
if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
384
-
return -EINVAL;
382
+
if (IS_ENABLED(CONFIG_X86_64)) {
383
+
/* Reject invalid MXCSR values. */
384
+
if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
385
+
return -EINVAL;
386
+
} else {
387
+
/* Mask invalid bits out for historical reasons (broken hardware). */
388
+
fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
389
+
}
385
390
386
391
/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
387
392
if (use_xsave())
+81
arch/x86/kernel/hpet.c
+81
arch/x86/kernel/hpet.c
···
10
10
#include <asm/irq_remapping.h>
11
11
#include <asm/hpet.h>
12
12
#include <asm/time.h>
13
+
#include <asm/mwait.h>
13
14
14
15
#undef pr_fmt
15
16
#define pr_fmt(fmt) "hpet: " fmt
···
917
916
return false;
918
917
}
919
918
919
+
static bool __init mwait_pc10_supported(void)
920
+
{
921
+
unsigned int eax, ebx, ecx, mwait_substates;
922
+
923
+
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
924
+
return false;
925
+
926
+
if (!cpu_feature_enabled(X86_FEATURE_MWAIT))
927
+
return false;
928
+
929
+
if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
930
+
return false;
931
+
932
+
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
933
+
934
+
return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) &&
935
+
(ecx & CPUID5_ECX_INTERRUPT_BREAK) &&
936
+
(mwait_substates & (0xF << 28));
937
+
}
938
+
939
+
/*
940
+
* Check whether the system supports PC10. If so force disable HPET as that
941
+
* stops counting in PC10. This check is overbroad as it does not take any
942
+
* of the following into account:
943
+
*
944
+
* - ACPI tables
945
+
* - Enablement of intel_idle
946
+
* - Command line arguments which limit intel_idle C-state support
947
+
*
948
+
* That's perfectly fine. HPET is a piece of hardware designed by committee
949
+
* and the only reasons why it is still in use on modern systems is the
950
+
* fact that it is impossible to reliably query TSC and CPU frequency via
951
+
* CPUID or firmware.
952
+
*
953
+
* If HPET is functional it is useful for calibrating TSC, but this can be
954
+
* done via PMTIMER as well which seems to be the last remaining timer on
955
+
* X86/INTEL platforms that has not been completely wreckaged by feature
956
+
* creep.
957
+
*
958
+
* In theory HPET support should be removed altogether, but there are older
959
+
* systems out there which depend on it because TSC and APIC timer are
960
+
* dysfunctional in deeper C-states.
961
+
*
962
+
* It's only 20 years now that hardware people have been asked to provide
963
+
* reliable and discoverable facilities which can be used for timekeeping
964
+
* and per CPU timer interrupts.
965
+
*
966
+
* The probability that this problem is going to be solved in the
967
+
* forseeable future is close to zero, so the kernel has to be cluttered
968
+
* with heuristics to keep up with the ever growing amount of hardware and
969
+
* firmware trainwrecks. Hopefully some day hardware people will understand
970
+
* that the approach of "This can be fixed in software" is not sustainable.
971
+
* Hope dies last...
972
+
*/
973
+
static bool __init hpet_is_pc10_damaged(void)
974
+
{
975
+
unsigned long long pcfg;
976
+
977
+
/* Check whether PC10 substates are supported */
978
+
if (!mwait_pc10_supported())
979
+
return false;
980
+
981
+
/* Check whether PC10 is enabled in PKG C-state limit */
982
+
rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
983
+
if ((pcfg & 0xF) < 8)
984
+
return false;
985
+
986
+
if (hpet_force_user) {
987
+
pr_warn("HPET force enabled via command line, but dysfunctional in PC10.\n");
988
+
return false;
989
+
}
990
+
991
+
pr_info("HPET dysfunctional in PC10. Force disabled.\n");
992
+
boot_hpet_disable = true;
993
+
return true;
994
+
}
995
+
920
996
/**
921
997
* hpet_enable - Try to setup the HPET timer. Returns 1 on success.
922
998
*/
···
1005
927
u64 freq;
1006
928
1007
929
if (!is_hpet_capable())
930
+
return 0;
931
+
932
+
if (hpet_is_pc10_damaged())
1008
933
return 0;
1009
934
1010
935
hpet_set_mapping();
+1
-1
arch/x86/platform/olpc/olpc.c
+1
-1
arch/x86/platform/olpc/olpc.c