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spi: sh-msiof: SITSCR/SIRSCR bitfield conversion

Convert MSIOF Transmit and Receive Clock Select Register field accesses
to use the FIELD_PREP() bitfield access macro.

This gets rid of explicit shifts and custom field preparation macros.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/f2462c99b6ea2e45b995ab4509c2f039043da032.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Geert Uytterhoeven and committed by
Mark Brown c2cc4b72 386cc520

+10 -10
+10 -10
drivers/spi/spi-sh-msiof.c
··· 105 105 #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ 106 106 107 107 /* SITSCR and SIRSCR */ 108 - #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */ 109 - #define SISCR_BRPS(i) (((i) - 1) << 8) 110 - #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ 111 - #define SISCR_BRDV_DIV_2 0 112 - #define SISCR_BRDV_DIV_4 1 113 - #define SISCR_BRDV_DIV_8 2 114 - #define SISCR_BRDV_DIV_16 3 115 - #define SISCR_BRDV_DIV_32 4 116 - #define SISCR_BRDV_DIV_1 7 108 + #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ 109 + #define SISCR_BRDV GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ 110 + #define SISCR_BRDV_DIV_2 0U 111 + #define SISCR_BRDV_DIV_4 1U 112 + #define SISCR_BRDV_DIV_8 2U 113 + #define SISCR_BRDV_DIV_16 3U 114 + #define SISCR_BRDV_DIV_32 4U 115 + #define SISCR_BRDV_DIV_1 7U 117 116 118 117 /* SICTR */ 119 118 #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ ··· 298 299 299 300 t->effective_speed_hz = parent_rate / (brps << div_pow); 300 301 301 - scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps); 302 + scr = FIELD_PREP(SISCR_BRDV, sh_msiof_spi_div_array[div_pow]) | 303 + FIELD_PREP(SISCR_BRPS, brps - 1); 302 304 sh_msiof_write(p, SITSCR, scr); 303 305 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 304 306 sh_msiof_write(p, SIRSCR, scr);