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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
powercap: intel_rapl: Consolidate PL4 and PMU support flags into rapl_defaults
Currently, PL4 and MSR-based RAPL PMU support are detected using
separate CPU ID tables (pl4_support_ids and pmu_support_ids) in the
MSR driver probe path. This creates a maintenance burden since adding
a new CPU requires updates in two places: the rapl_ids table and one
or both of these capability tables.
Consolidate PL4 and PMU capability information directly into
struct rapl_defaults by adding msr_pl4_support and msr_pmu_support
flags. This allows per-CPU capability to be expressed in a single
place alongside other per-CPU defaults, eliminating the duplicate
CPU ID tables entirely.
No functional changes are intended.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: https://patch.msgid.link/20260331211950.3329932-8-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
authored by
Kuppuswamy Sathyanarayanan
and committed by
Rafael J. Wysocki
c3bb8d4f
b0ee5110
+38
-47
+36
-47
drivers/powercap/intel_rapl_msr.c
+36
-47
drivers/powercap/intel_rapl_msr.c
···
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return ra->err;
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}
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-
/* List of verified CPUs. */
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static const struct x86_cpu_id pl4_support_ids[] = {
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X86_MATCH_VFM(INTEL_ICELAKE_L, NULL),
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X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_ALDERLAKE, NULL),
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X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL),
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-
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL),
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X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL),
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-
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL),
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-
X86_MATCH_VFM(INTEL_METEORLAKE, NULL),
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X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL),
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-
X86_MATCH_VFM(INTEL_ARROWLAKE_U, NULL),
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-
X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL),
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-
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_NOVALAKE, NULL),
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X86_MATCH_VFM(INTEL_NOVALAKE_L, NULL),
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{}
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};
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-
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/* List of MSR-based RAPL PMU support CPUs */
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static const struct x86_cpu_id pmu_support_ids[] = {
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X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
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-
{}
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-
};
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-
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static int rapl_check_unit_atom(struct rapl_domain *rd)
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{
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struct reg_action ra;
···
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.check_unit = rapl_default_check_unit,
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};
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+
static const struct rapl_defaults rapl_defaults_core_pl4 = {
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.floor_freq_reg_addr = 0,
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+
.check_unit = rapl_default_check_unit,
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+
.set_floor_freq = rapl_default_set_floor_freq,
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+
.compute_time_window = rapl_default_compute_time_window,
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.msr_pl4_support = 1,
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+
};
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+
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static const struct rapl_defaults rapl_defaults_core_pl4_pmu = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_default_check_unit,
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.set_floor_freq = rapl_default_set_floor_freq,
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.compute_time_window = rapl_default_compute_time_window,
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.msr_pl4_support = 1,
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.msr_pmu_support = 1,
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};
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+
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static const struct x86_cpu_id rapl_ids[] = {
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X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
···
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X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
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-
X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
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+
X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
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+
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
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-
X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
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-
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
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-
X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
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X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
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X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
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-
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
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+
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core_pl4_pmu),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core_pl4_pmu),
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X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
···
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static int rapl_msr_probe(struct platform_device *pdev)
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{
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const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
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int ret;
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switch (boot_cpu_data.x86_vendor) {
···
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rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data;
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rapl_msr_priv->rpi = rpi_msr;
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-
if (id) {
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+
if (rapl_msr_priv->defaults->msr_pl4_support) {
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rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);
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rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4].msr =
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MSR_VR_CURRENT_CONFIG;
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pr_info("PL4 support detected.\n");
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pr_info("PL4 support detected (updated).\n");
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}
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-
if (x86_match_cpu(pmu_support_ids)) {
528
+
if (rapl_msr_priv->defaults->msr_pmu_support) {
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rapl_msr_pmu = true;
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pr_info("MSR-based RAPL PMU support enabled\n");
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pr_info("MSR-based RAPL PMU support enabled (updated)\n");
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}
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rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);