tjh.dev / kernel
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clk: qcom: mmcc-msm8960: use parent_hws/_data instead of parent_names

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-10-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson c3ddc184 d226c5f0

+203 -119
+203 -119
drivers/clk/qcom/mmcc-msm8960.c
··· 51 51 .status_bit = 16, 52 52 .clkr.hw.init = &(struct clk_init_data){ 53 53 .name = "pll2", 54 - .parent_names = (const char *[]){ "pxo" }, 54 + .parent_data = (const struct clk_parent_data[]){ 55 + { .fw_name = "pxo", .name = "pxo_board" }, 56 + }, 55 57 .num_parents = 1, 56 58 .ops = &clk_pll_ops, 57 59 }, ··· 69 67 .status_bit = 16, 70 68 .clkr.hw.init = &(struct clk_init_data){ 71 69 .name = "pll15", 72 - .parent_names = (const char *[]){ "pxo" }, 70 + .parent_data = (const struct clk_parent_data[]){ 71 + { .fw_name = "pxo", .name = "pxo_board" }, 72 + }, 73 73 .num_parents = 1, 74 74 .ops = &clk_pll_ops, 75 75 }, ··· 97 93 { P_PLL2, 1 } 98 94 }; 99 95 100 - static const char * const mmcc_pxo_pll8_pll2[] = { 101 - "pxo", 102 - "pll8_vote", 103 - "pll2", 96 + static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = { 97 + { .fw_name = "pxo", .name = "pxo_board" }, 98 + { .fw_name = "pll8_vote", .name = "pll8_vote" }, 99 + { .hw = &pll2.clkr.hw }, 104 100 }; 105 101 106 102 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { ··· 110 106 { P_PLL3, 3 } 111 107 }; 112 108 113 - static const char * const mmcc_pxo_pll8_pll2_pll15[] = { 114 - "pxo", 115 - "pll8_vote", 116 - "pll2", 117 - "pll15", 109 + static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = { 110 + { .fw_name = "pxo", .name = "pxo_board" }, 111 + { .fw_name = "pll8_vote", .name = "pll8_vote" }, 112 + { .hw = &pll2.clkr.hw }, 113 + { .hw = &pll15.clkr.hw }, 118 114 }; 119 115 120 116 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { ··· 124 120 { P_PLL15, 3 } 125 121 }; 126 122 127 - static const char * const mmcc_pxo_pll8_pll2_pll3[] = { 128 - "pxo", 129 - "pll8_vote", 130 - "pll2", 131 - "pll3", 123 + static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = { 124 + { .fw_name = "pxo", .name = "pxo_board" }, 125 + { .fw_name = "pll8_vote", .name = "pll8_vote" }, 126 + { .hw = &pll2.clkr.hw }, 127 + { .fw_name = "pll3", .name = "pll3" }, 132 128 }; 133 129 134 130 static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = { ··· 137 133 { P_DSI1_PLL_DSICLK, 3 }, 138 134 }; 139 135 140 - static const char * const mmcc_pxo_dsi2_dsi1[] = { 141 - "pxo", 142 - "dsi2pll", 143 - "dsi1pll", 136 + static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = { 137 + { .fw_name = "pxo", .name = "pxo_board" }, 138 + { .fw_name = "dsi2pll", .name = "dsi2pll" }, 139 + { .fw_name = "dsi1pll", .name = "dsi1pll" }, 144 140 }; 145 141 146 142 static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = { ··· 149 145 { P_DSI2_PLL_BYTECLK, 2 }, 150 146 }; 151 147 152 - static const char * const mmcc_pxo_dsi1_dsi2_byte[] = { 153 - "pxo", 154 - "dsi1pllbyte", 155 - "dsi2pllbyte", 148 + static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = { 149 + { .fw_name = "pxo", .name = "pxo_board" }, 150 + { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }, 151 + { .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" }, 156 152 }; 157 153 158 154 static struct freq_tbl clk_tbl_cam[] = { ··· 196 192 .enable_mask = BIT(2), 197 193 .hw.init = &(struct clk_init_data){ 198 194 .name = "camclk0_src", 199 - .parent_names = mmcc_pxo_pll8_pll2, 195 + .parent_data = mmcc_pxo_pll8_pll2, 200 196 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 201 197 .ops = &clk_rcg_ops, 202 198 }, ··· 211 207 .enable_mask = BIT(0), 212 208 .hw.init = &(struct clk_init_data){ 213 209 .name = "camclk0_clk", 214 - .parent_names = (const char *[]){ "camclk0_src" }, 210 + .parent_hws = (const struct clk_hw*[]){ 211 + &camclk0_src.clkr.hw 212 + }, 215 213 .num_parents = 1, 216 214 .ops = &clk_branch_ops, 217 215 }, ··· 247 241 .enable_mask = BIT(2), 248 242 .hw.init = &(struct clk_init_data){ 249 243 .name = "camclk1_src", 250 - .parent_names = mmcc_pxo_pll8_pll2, 244 + .parent_data = mmcc_pxo_pll8_pll2, 251 245 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 252 246 .ops = &clk_rcg_ops, 253 247 }, ··· 262 256 .enable_mask = BIT(0), 263 257 .hw.init = &(struct clk_init_data){ 264 258 .name = "camclk1_clk", 265 - .parent_names = (const char *[]){ "camclk1_src" }, 259 + .parent_hws = (const struct clk_hw*[]){ 260 + &camclk1_src.clkr.hw 261 + }, 266 262 .num_parents = 1, 267 263 .ops = &clk_branch_ops, 268 264 }, ··· 298 290 .enable_mask = BIT(2), 299 291 .hw.init = &(struct clk_init_data){ 300 292 .name = "camclk2_src", 301 - .parent_names = mmcc_pxo_pll8_pll2, 293 + .parent_data = mmcc_pxo_pll8_pll2, 302 294 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 303 295 .ops = &clk_rcg_ops, 304 296 }, ··· 313 305 .enable_mask = BIT(0), 314 306 .hw.init = &(struct clk_init_data){ 315 307 .name = "camclk2_clk", 316 - .parent_names = (const char *[]){ "camclk2_src" }, 308 + .parent_hws = (const struct clk_hw*[]){ 309 + &camclk2_src.clkr.hw 310 + }, 317 311 .num_parents = 1, 318 312 .ops = &clk_branch_ops, 319 313 }, ··· 355 345 .enable_mask = BIT(2), 356 346 .hw.init = &(struct clk_init_data){ 357 347 .name = "csi0_src", 358 - .parent_names = mmcc_pxo_pll8_pll2, 348 + .parent_data = mmcc_pxo_pll8_pll2, 359 349 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 360 350 .ops = &clk_rcg_ops, 361 351 }, ··· 369 359 .enable_reg = 0x0040, 370 360 .enable_mask = BIT(0), 371 361 .hw.init = &(struct clk_init_data){ 372 - .parent_names = (const char *[]){ "csi0_src" }, 362 + .parent_hws = (const struct clk_hw*[]){ 363 + &csi0_src.clkr.hw 364 + }, 373 365 .num_parents = 1, 374 366 .name = "csi0_clk", 375 367 .ops = &clk_branch_ops, ··· 387 375 .enable_reg = 0x0040, 388 376 .enable_mask = BIT(8), 389 377 .hw.init = &(struct clk_init_data){ 390 - .parent_names = (const char *[]){ "csi0_src" }, 378 + .parent_hws = (const struct clk_hw*[]){ 379 + &csi0_src.clkr.hw 380 + }, 391 381 .num_parents = 1, 392 382 .name = "csi0_phy_clk", 393 383 .ops = &clk_branch_ops, ··· 423 409 .enable_mask = BIT(2), 424 410 .hw.init = &(struct clk_init_data){ 425 411 .name = "csi1_src", 426 - .parent_names = mmcc_pxo_pll8_pll2, 412 + .parent_data = mmcc_pxo_pll8_pll2, 427 413 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 428 414 .ops = &clk_rcg_ops, 429 415 }, ··· 437 423 .enable_reg = 0x0024, 438 424 .enable_mask = BIT(0), 439 425 .hw.init = &(struct clk_init_data){ 440 - .parent_names = (const char *[]){ "csi1_src" }, 426 + .parent_hws = (const struct clk_hw*[]){ 427 + &csi1_src.clkr.hw 428 + }, 441 429 .num_parents = 1, 442 430 .name = "csi1_clk", 443 431 .ops = &clk_branch_ops, ··· 455 439 .enable_reg = 0x0024, 456 440 .enable_mask = BIT(8), 457 441 .hw.init = &(struct clk_init_data){ 458 - .parent_names = (const char *[]){ "csi1_src" }, 442 + .parent_hws = (const struct clk_hw*[]){ 443 + &csi1_src.clkr.hw 444 + }, 459 445 .num_parents = 1, 460 446 .name = "csi1_phy_clk", 461 447 .ops = &clk_branch_ops, ··· 491 473 .enable_mask = BIT(2), 492 474 .hw.init = &(struct clk_init_data){ 493 475 .name = "csi2_src", 494 - .parent_names = mmcc_pxo_pll8_pll2, 476 + .parent_data = mmcc_pxo_pll8_pll2, 495 477 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 496 478 .ops = &clk_rcg_ops, 497 479 }, ··· 505 487 .enable_reg = 0x022c, 506 488 .enable_mask = BIT(0), 507 489 .hw.init = &(struct clk_init_data){ 508 - .parent_names = (const char *[]){ "csi2_src" }, 490 + .parent_hws = (const struct clk_hw*[]){ 491 + &csi2_src.clkr.hw 492 + }, 509 493 .num_parents = 1, 510 494 .name = "csi2_clk", 511 495 .ops = &clk_branch_ops, ··· 523 503 .enable_reg = 0x022c, 524 504 .enable_mask = BIT(8), 525 505 .hw.init = &(struct clk_init_data){ 526 - .parent_names = (const char *[]){ "csi2_src" }, 506 + .parent_hws = (const struct clk_hw*[]){ 507 + &csi2_src.clkr.hw 508 + }, 527 509 .num_parents = 1, 528 510 .name = "csi2_phy_clk", 529 511 .ops = &clk_branch_ops, ··· 624 602 .determine_rate = __clk_mux_determine_rate, 625 603 }; 626 604 627 - static const char * const pix_rdi_parents[] = { 628 - "csi0_clk", 629 - "csi1_clk", 630 - "csi2_clk", 605 + static const struct clk_hw *pix_rdi_parents[] = { 606 + &csi0_clk.clkr.hw, 607 + &csi1_clk.clkr.hw, 608 + &csi2_clk.clkr.hw, 631 609 }; 632 610 633 611 static struct clk_pix_rdi csi_pix_clk = { ··· 640 618 .enable_mask = BIT(26), 641 619 .hw.init = &(struct clk_init_data){ 642 620 .name = "csi_pix_clk", 643 - .parent_names = pix_rdi_parents, 621 + .parent_hws = pix_rdi_parents, 644 622 .num_parents = ARRAY_SIZE(pix_rdi_parents), 645 623 .ops = &clk_ops_pix_rdi, 646 624 }, ··· 657 635 .enable_mask = BIT(10), 658 636 .hw.init = &(struct clk_init_data){ 659 637 .name = "csi_pix1_clk", 660 - .parent_names = pix_rdi_parents, 638 + .parent_hws = pix_rdi_parents, 661 639 .num_parents = ARRAY_SIZE(pix_rdi_parents), 662 640 .ops = &clk_ops_pix_rdi, 663 641 }, ··· 674 652 .enable_mask = BIT(13), 675 653 .hw.init = &(struct clk_init_data){ 676 654 .name = "csi_rdi_clk", 677 - .parent_names = pix_rdi_parents, 655 + .parent_hws = pix_rdi_parents, 678 656 .num_parents = ARRAY_SIZE(pix_rdi_parents), 679 657 .ops = &clk_ops_pix_rdi, 680 658 }, ··· 691 669 .enable_mask = BIT(2), 692 670 .hw.init = &(struct clk_init_data){ 693 671 .name = "csi_rdi1_clk", 694 - .parent_names = pix_rdi_parents, 672 + .parent_hws = pix_rdi_parents, 695 673 .num_parents = ARRAY_SIZE(pix_rdi_parents), 696 674 .ops = &clk_ops_pix_rdi, 697 675 }, ··· 708 686 .enable_mask = BIT(6), 709 687 .hw.init = &(struct clk_init_data){ 710 688 .name = "csi_rdi2_clk", 711 - .parent_names = pix_rdi_parents, 689 + .parent_hws = pix_rdi_parents, 712 690 .num_parents = ARRAY_SIZE(pix_rdi_parents), 713 691 .ops = &clk_ops_pix_rdi, 714 692 }, ··· 747 725 .enable_mask = BIT(2), 748 726 .hw.init = &(struct clk_init_data){ 749 727 .name = "csiphytimer_src", 750 - .parent_names = mmcc_pxo_pll8_pll2, 728 + .parent_data = mmcc_pxo_pll8_pll2, 751 729 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 752 730 .ops = &clk_rcg_ops, 753 731 }, 754 732 }, 755 733 }; 756 - 757 - static const char * const csixphy_timer_src[] = { "csiphytimer_src" }; 758 734 759 735 static struct clk_branch csiphy0_timer_clk = { 760 736 .halt_reg = 0x01e8, ··· 761 741 .enable_reg = 0x0160, 762 742 .enable_mask = BIT(0), 763 743 .hw.init = &(struct clk_init_data){ 764 - .parent_names = csixphy_timer_src, 765 - .num_parents = ARRAY_SIZE(csixphy_timer_src), 744 + .parent_hws = (const struct clk_hw*[]){ 745 + &csiphytimer_src.clkr.hw, 746 + }, 747 + .num_parents = 1, 766 748 .name = "csiphy0_timer_clk", 767 749 .ops = &clk_branch_ops, 768 750 .flags = CLK_SET_RATE_PARENT, ··· 779 757 .enable_reg = 0x0160, 780 758 .enable_mask = BIT(9), 781 759 .hw.init = &(struct clk_init_data){ 782 - .parent_names = csixphy_timer_src, 783 - .num_parents = ARRAY_SIZE(csixphy_timer_src), 760 + .parent_hws = (const struct clk_hw*[]){ 761 + &csiphytimer_src.clkr.hw, 762 + }, 763 + .num_parents = 1, 784 764 .name = "csiphy1_timer_clk", 785 765 .ops = &clk_branch_ops, 786 766 .flags = CLK_SET_RATE_PARENT, ··· 797 773 .enable_reg = 0x0160, 798 774 .enable_mask = BIT(11), 799 775 .hw.init = &(struct clk_init_data){ 800 - .parent_names = csixphy_timer_src, 801 - .num_parents = ARRAY_SIZE(csixphy_timer_src), 776 + .parent_hws = (const struct clk_hw*[]){ 777 + &csiphytimer_src.clkr.hw, 778 + }, 779 + .num_parents = 1, 802 780 .name = "csiphy2_timer_clk", 803 781 .ops = &clk_branch_ops, 804 782 .flags = CLK_SET_RATE_PARENT, ··· 861 835 .enable_mask = BIT(2), 862 836 .hw.init = &(struct clk_init_data){ 863 837 .name = "gfx2d0_src", 864 - .parent_names = mmcc_pxo_pll8_pll2, 838 + .parent_data = mmcc_pxo_pll8_pll2, 865 839 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 866 840 .ops = &clk_dyn_rcg_ops, 867 841 }, ··· 876 850 .enable_mask = BIT(0), 877 851 .hw.init = &(struct clk_init_data){ 878 852 .name = "gfx2d0_clk", 879 - .parent_names = (const char *[]){ "gfx2d0_src" }, 853 + .parent_hws = (const struct clk_hw*[]){ 854 + &gfx2d0_src.clkr.hw 855 + }, 880 856 .num_parents = 1, 881 857 .ops = &clk_branch_ops, 882 858 .flags = CLK_SET_RATE_PARENT, ··· 923 895 .enable_mask = BIT(2), 924 896 .hw.init = &(struct clk_init_data){ 925 897 .name = "gfx2d1_src", 926 - .parent_names = mmcc_pxo_pll8_pll2, 898 + .parent_data = mmcc_pxo_pll8_pll2, 927 899 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 928 900 .ops = &clk_dyn_rcg_ops, 929 901 }, ··· 938 910 .enable_mask = BIT(0), 939 911 .hw.init = &(struct clk_init_data){ 940 912 .name = "gfx2d1_clk", 941 - .parent_names = (const char *[]){ "gfx2d1_src" }, 913 + .parent_hws = (const struct clk_hw*[]){ 914 + &gfx2d1_src.clkr.hw 915 + }, 942 916 .num_parents = 1, 943 917 .ops = &clk_branch_ops, 944 918 .flags = CLK_SET_RATE_PARENT, ··· 1026 996 .enable_mask = BIT(2), 1027 997 .hw.init = &(struct clk_init_data){ 1028 998 .name = "gfx3d_src", 1029 - .parent_names = mmcc_pxo_pll8_pll2_pll3, 999 + .parent_data = mmcc_pxo_pll8_pll2_pll3, 1030 1000 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3), 1031 1001 .ops = &clk_dyn_rcg_ops, 1032 1002 }, ··· 1035 1005 1036 1006 static const struct clk_init_data gfx3d_8064_init = { 1037 1007 .name = "gfx3d_src", 1038 - .parent_names = mmcc_pxo_pll8_pll2_pll15, 1008 + .parent_data = mmcc_pxo_pll8_pll2_pll15, 1039 1009 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15), 1040 1010 .ops = &clk_dyn_rcg_ops, 1041 1011 }; ··· 1048 1018 .enable_mask = BIT(0), 1049 1019 .hw.init = &(struct clk_init_data){ 1050 1020 .name = "gfx3d_clk", 1051 - .parent_names = (const char *[]){ "gfx3d_src" }, 1021 + .parent_hws = (const struct clk_hw*[]){ 1022 + &gfx3d_src.clkr.hw 1023 + }, 1052 1024 .num_parents = 1, 1053 1025 .ops = &clk_branch_ops, 1054 1026 .flags = CLK_SET_RATE_PARENT, ··· 1106 1074 .enable_mask = BIT(2), 1107 1075 .hw.init = &(struct clk_init_data){ 1108 1076 .name = "vcap_src", 1109 - .parent_names = mmcc_pxo_pll8_pll2, 1077 + .parent_data = mmcc_pxo_pll8_pll2, 1110 1078 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1111 1079 .ops = &clk_dyn_rcg_ops, 1112 1080 }, ··· 1121 1089 .enable_mask = BIT(0), 1122 1090 .hw.init = &(struct clk_init_data){ 1123 1091 .name = "vcap_clk", 1124 - .parent_names = (const char *[]){ "vcap_src" }, 1092 + .parent_hws = (const struct clk_hw*[]){ 1093 + &vcap_src.clkr.hw 1094 + }, 1125 1095 .num_parents = 1, 1126 1096 .ops = &clk_branch_ops, 1127 1097 .flags = CLK_SET_RATE_PARENT, ··· 1139 1105 .enable_mask = BIT(13), 1140 1106 .hw.init = &(struct clk_init_data){ 1141 1107 .name = "vcap_npl_clk", 1142 - .parent_names = (const char *[]){ "vcap_src" }, 1108 + .parent_hws = (const struct clk_hw*[]){ 1109 + &vcap_src.clkr.hw 1110 + }, 1143 1111 .num_parents = 1, 1144 1112 .ops = &clk_branch_ops, 1145 1113 .flags = CLK_SET_RATE_PARENT, ··· 1189 1153 .enable_mask = BIT(2), 1190 1154 .hw.init = &(struct clk_init_data){ 1191 1155 .name = "ijpeg_src", 1192 - .parent_names = mmcc_pxo_pll8_pll2, 1156 + .parent_data = mmcc_pxo_pll8_pll2, 1193 1157 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1194 1158 .ops = &clk_rcg_ops, 1195 1159 }, ··· 1204 1168 .enable_mask = BIT(0), 1205 1169 .hw.init = &(struct clk_init_data){ 1206 1170 .name = "ijpeg_clk", 1207 - .parent_names = (const char *[]){ "ijpeg_src" }, 1171 + .parent_hws = (const struct clk_hw*[]){ 1172 + &ijpeg_src.clkr.hw 1173 + }, 1208 1174 .num_parents = 1, 1209 1175 .ops = &clk_branch_ops, 1210 1176 .flags = CLK_SET_RATE_PARENT, ··· 1239 1201 .enable_mask = BIT(2), 1240 1202 .hw.init = &(struct clk_init_data){ 1241 1203 .name = "jpegd_src", 1242 - .parent_names = mmcc_pxo_pll8_pll2, 1204 + .parent_data = mmcc_pxo_pll8_pll2, 1243 1205 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1244 1206 .ops = &clk_rcg_ops, 1245 1207 }, ··· 1254 1216 .enable_mask = BIT(0), 1255 1217 .hw.init = &(struct clk_init_data){ 1256 1218 .name = "jpegd_clk", 1257 - .parent_names = (const char *[]){ "jpegd_src" }, 1219 + .parent_hws = (const struct clk_hw*[]){ 1220 + &jpegd_src.clkr.hw 1221 + }, 1258 1222 .num_parents = 1, 1259 1223 .ops = &clk_branch_ops, 1260 1224 .flags = CLK_SET_RATE_PARENT, ··· 1321 1281 .enable_mask = BIT(2), 1322 1282 .hw.init = &(struct clk_init_data){ 1323 1283 .name = "mdp_src", 1324 - .parent_names = mmcc_pxo_pll8_pll2, 1284 + .parent_data = mmcc_pxo_pll8_pll2, 1325 1285 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1326 1286 .ops = &clk_dyn_rcg_ops, 1327 1287 }, ··· 1336 1296 .enable_mask = BIT(0), 1337 1297 .hw.init = &(struct clk_init_data){ 1338 1298 .name = "mdp_clk", 1339 - .parent_names = (const char *[]){ "mdp_src" }, 1299 + .parent_hws = (const struct clk_hw*[]){ 1300 + &mdp_src.clkr.hw 1301 + }, 1340 1302 .num_parents = 1, 1341 1303 .ops = &clk_branch_ops, 1342 1304 .flags = CLK_SET_RATE_PARENT, ··· 1353 1311 .enable_reg = 0x016c, 1354 1312 .enable_mask = BIT(0), 1355 1313 .hw.init = &(struct clk_init_data){ 1356 - .parent_names = (const char *[]){ "mdp_src" }, 1314 + .parent_hws = (const struct clk_hw*[]){ 1315 + &mdp_src.clkr.hw 1316 + }, 1357 1317 .num_parents = 1, 1358 1318 .name = "mdp_lut_clk", 1359 1319 .ops = &clk_branch_ops, ··· 1372 1328 .enable_mask = BIT(6), 1373 1329 .hw.init = &(struct clk_init_data){ 1374 1330 .name = "mdp_vsync_clk", 1375 - .parent_names = (const char *[]){ "pxo" }, 1331 + .parent_data = (const struct clk_parent_data[]){ 1332 + { .fw_name = "pxo", .name = "pxo_board" }, 1333 + }, 1376 1334 .num_parents = 1, 1377 1335 .ops = &clk_branch_ops 1378 1336 }, ··· 1426 1380 .enable_mask = BIT(2), 1427 1381 .hw.init = &(struct clk_init_data){ 1428 1382 .name = "rot_src", 1429 - .parent_names = mmcc_pxo_pll8_pll2, 1383 + .parent_data = mmcc_pxo_pll8_pll2, 1430 1384 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1431 1385 .ops = &clk_dyn_rcg_ops, 1432 1386 }, ··· 1441 1395 .enable_mask = BIT(0), 1442 1396 .hw.init = &(struct clk_init_data){ 1443 1397 .name = "rot_clk", 1444 - .parent_names = (const char *[]){ "rot_src" }, 1398 + .parent_hws = (const struct clk_hw*[]){ 1399 + &rot_src.clkr.hw 1400 + }, 1445 1401 .num_parents = 1, 1446 1402 .ops = &clk_branch_ops, 1447 1403 .flags = CLK_SET_RATE_PARENT, ··· 1456 1408 { P_HDMI_PLL, 3 } 1457 1409 }; 1458 1410 1459 - static const char * const mmcc_pxo_hdmi[] = { 1460 - "pxo", 1461 - "hdmi_pll", 1411 + static const struct clk_parent_data mmcc_pxo_hdmi[] = { 1412 + { .fw_name = "pxo", .name = "pxo_board" }, 1413 + { .fw_name = "hdmipll", .name = "hdmi_pll" }, 1462 1414 }; 1463 1415 1464 1416 static struct freq_tbl clk_tbl_tv[] = { ··· 1491 1443 .enable_mask = BIT(2), 1492 1444 .hw.init = &(struct clk_init_data){ 1493 1445 .name = "tv_src", 1494 - .parent_names = mmcc_pxo_hdmi, 1446 + .parent_data = mmcc_pxo_hdmi, 1495 1447 .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi), 1496 1448 .ops = &clk_rcg_bypass_ops, 1497 1449 .flags = CLK_SET_RATE_PARENT, 1498 1450 }, 1499 1451 }, 1500 1452 }; 1501 - 1502 - static const char * const tv_src_name[] = { "tv_src" }; 1503 1453 1504 1454 static struct clk_branch tv_enc_clk = { 1505 1455 .halt_reg = 0x01d4, ··· 1506 1460 .enable_reg = 0x00ec, 1507 1461 .enable_mask = BIT(8), 1508 1462 .hw.init = &(struct clk_init_data){ 1509 - .parent_names = tv_src_name, 1510 - .num_parents = ARRAY_SIZE(tv_src_name), 1463 + .parent_hws = (const struct clk_hw*[]){ 1464 + &tv_src.clkr.hw, 1465 + }, 1466 + .num_parents = 1, 1511 1467 .name = "tv_enc_clk", 1512 1468 .ops = &clk_branch_ops, 1513 1469 .flags = CLK_SET_RATE_PARENT, ··· 1524 1476 .enable_reg = 0x00ec, 1525 1477 .enable_mask = BIT(10), 1526 1478 .hw.init = &(struct clk_init_data){ 1527 - .parent_names = tv_src_name, 1528 - .num_parents = ARRAY_SIZE(tv_src_name), 1479 + .parent_hws = (const struct clk_hw*[]){ 1480 + &tv_src.clkr.hw, 1481 + }, 1482 + .num_parents = 1, 1529 1483 .name = "tv_dac_clk", 1530 1484 .ops = &clk_branch_ops, 1531 1485 .flags = CLK_SET_RATE_PARENT, ··· 1542 1492 .enable_reg = 0x00ec, 1543 1493 .enable_mask = BIT(0), 1544 1494 .hw.init = &(struct clk_init_data){ 1545 - .parent_names = tv_src_name, 1546 - .num_parents = ARRAY_SIZE(tv_src_name), 1495 + .parent_hws = (const struct clk_hw*[]){ 1496 + &tv_src.clkr.hw, 1497 + }, 1498 + .num_parents = 1, 1547 1499 .name = "mdp_tv_clk", 1548 1500 .ops = &clk_branch_ops, 1549 1501 .flags = CLK_SET_RATE_PARENT, ··· 1560 1508 .enable_reg = 0x00ec, 1561 1509 .enable_mask = BIT(12), 1562 1510 .hw.init = &(struct clk_init_data){ 1563 - .parent_names = tv_src_name, 1564 - .num_parents = ARRAY_SIZE(tv_src_name), 1511 + .parent_hws = (const struct clk_hw*[]){ 1512 + &tv_src.clkr.hw, 1513 + }, 1514 + .num_parents = 1, 1565 1515 .name = "hdmi_tv_clk", 1566 1516 .ops = &clk_branch_ops, 1567 1517 .flags = CLK_SET_RATE_PARENT, ··· 1578 1524 .enable_reg = 0x0124, 1579 1525 .enable_mask = BIT(14), 1580 1526 .hw.init = &(struct clk_init_data){ 1581 - .parent_names = tv_src_name, 1582 - .num_parents = ARRAY_SIZE(tv_src_name), 1527 + .parent_hws = (const struct clk_hw*[]){ 1528 + &tv_src.clkr.hw, 1529 + }, 1530 + .num_parents = 1, 1583 1531 .name = "rgb_tv_clk", 1584 1532 .ops = &clk_branch_ops, 1585 1533 .flags = CLK_SET_RATE_PARENT, ··· 1596 1540 .enable_reg = 0x0124, 1597 1541 .enable_mask = BIT(16), 1598 1542 .hw.init = &(struct clk_init_data){ 1599 - .parent_names = tv_src_name, 1600 - .num_parents = ARRAY_SIZE(tv_src_name), 1543 + .parent_hws = (const struct clk_hw*[]){ 1544 + &tv_src.clkr.hw, 1545 + }, 1546 + .num_parents = 1, 1601 1547 .name = "npl_tv_clk", 1602 1548 .ops = &clk_branch_ops, 1603 1549 .flags = CLK_SET_RATE_PARENT, ··· 1614 1556 .enable_reg = 0x005c, 1615 1557 .enable_mask = BIT(11), 1616 1558 .hw.init = &(struct clk_init_data){ 1617 - .parent_names = (const char *[]){ "pxo" }, 1559 + .parent_data = (const struct clk_parent_data[]){ 1560 + { .fw_name = "pxo", .name = "pxo_board" }, 1561 + }, 1618 1562 .num_parents = 1, 1619 1563 .name = "hdmi_app_clk", 1620 1564 .ops = &clk_branch_ops, ··· 1674 1614 .enable_mask = BIT(2), 1675 1615 .hw.init = &(struct clk_init_data){ 1676 1616 .name = "vcodec_src", 1677 - .parent_names = mmcc_pxo_pll8_pll2, 1617 + .parent_data = mmcc_pxo_pll8_pll2, 1678 1618 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1679 1619 .ops = &clk_dyn_rcg_ops, 1680 1620 }, ··· 1689 1629 .enable_mask = BIT(0), 1690 1630 .hw.init = &(struct clk_init_data){ 1691 1631 .name = "vcodec_clk", 1692 - .parent_names = (const char *[]){ "vcodec_src" }, 1632 + .parent_hws = (const struct clk_hw*[]){ 1633 + &vcodec_src.clkr.hw 1634 + }, 1693 1635 .num_parents = 1, 1694 1636 .ops = &clk_branch_ops, 1695 1637 .flags = CLK_SET_RATE_PARENT, ··· 1727 1665 .enable_mask = BIT(2), 1728 1666 .hw.init = &(struct clk_init_data){ 1729 1667 .name = "vpe_src", 1730 - .parent_names = mmcc_pxo_pll8_pll2, 1668 + .parent_data = mmcc_pxo_pll8_pll2, 1731 1669 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1732 1670 .ops = &clk_rcg_ops, 1733 1671 }, ··· 1742 1680 .enable_mask = BIT(0), 1743 1681 .hw.init = &(struct clk_init_data){ 1744 1682 .name = "vpe_clk", 1745 - .parent_names = (const char *[]){ "vpe_src" }, 1683 + .parent_hws = (const struct clk_hw*[]){ 1684 + &vpe_src.clkr.hw 1685 + }, 1746 1686 .num_parents = 1, 1747 1687 .ops = &clk_branch_ops, 1748 1688 .flags = CLK_SET_RATE_PARENT, ··· 1797 1733 .enable_mask = BIT(2), 1798 1734 .hw.init = &(struct clk_init_data){ 1799 1735 .name = "vfe_src", 1800 - .parent_names = mmcc_pxo_pll8_pll2, 1736 + .parent_data = mmcc_pxo_pll8_pll2, 1801 1737 .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), 1802 1738 .ops = &clk_rcg_ops, 1803 1739 }, ··· 1812 1748 .enable_mask = BIT(0), 1813 1749 .hw.init = &(struct clk_init_data){ 1814 1750 .name = "vfe_clk", 1815 - .parent_names = (const char *[]){ "vfe_src" }, 1751 + .parent_hws = (const struct clk_hw*[]){ 1752 + &vfe_src.clkr.hw 1753 + }, 1816 1754 .num_parents = 1, 1817 1755 .ops = &clk_branch_ops, 1818 1756 .flags = CLK_SET_RATE_PARENT, ··· 1829 1763 .enable_reg = 0x0104, 1830 1764 .enable_mask = BIT(12), 1831 1765 .hw.init = &(struct clk_init_data){ 1832 - .parent_names = (const char *[]){ "vfe_src" }, 1766 + .parent_hws = (const struct clk_hw*[]){ 1767 + &vfe_src.clkr.hw 1768 + }, 1833 1769 .num_parents = 1, 1834 1770 .name = "vfe_csi_clk", 1835 1771 .ops = &clk_branch_ops, ··· 2135 2067 .enable_mask = BIT(2), 2136 2068 .hw.init = &(struct clk_init_data){ 2137 2069 .name = "dsi1_src", 2138 - .parent_names = mmcc_pxo_dsi2_dsi1, 2070 + .parent_data = mmcc_pxo_dsi2_dsi1, 2139 2071 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2140 2072 .ops = &clk_rcg_bypass2_ops, 2141 2073 .flags = CLK_SET_RATE_PARENT, ··· 2151 2083 .enable_mask = BIT(0), 2152 2084 .hw.init = &(struct clk_init_data){ 2153 2085 .name = "dsi1_clk", 2154 - .parent_names = (const char *[]){ "dsi1_src" }, 2086 + .parent_hws = (const struct clk_hw*[]){ 2087 + &dsi1_src.clkr.hw 2088 + }, 2155 2089 .num_parents = 1, 2156 2090 .ops = &clk_branch_ops, 2157 2091 .flags = CLK_SET_RATE_PARENT, ··· 2185 2115 .enable_mask = BIT(2), 2186 2116 .hw.init = &(struct clk_init_data){ 2187 2117 .name = "dsi2_src", 2188 - .parent_names = mmcc_pxo_dsi2_dsi1, 2118 + .parent_data = mmcc_pxo_dsi2_dsi1, 2189 2119 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2190 2120 .ops = &clk_rcg_bypass2_ops, 2191 2121 .flags = CLK_SET_RATE_PARENT, ··· 2201 2131 .enable_mask = BIT(0), 2202 2132 .hw.init = &(struct clk_init_data){ 2203 2133 .name = "dsi2_clk", 2204 - .parent_names = (const char *[]){ "dsi2_src" }, 2134 + .parent_hws = (const struct clk_hw*[]){ 2135 + &dsi2_src.clkr.hw 2136 + }, 2205 2137 .num_parents = 1, 2206 2138 .ops = &clk_branch_ops, 2207 2139 .flags = CLK_SET_RATE_PARENT, ··· 2226 2154 .enable_mask = BIT(2), 2227 2155 .hw.init = &(struct clk_init_data){ 2228 2156 .name = "dsi1_byte_src", 2229 - .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2157 + .parent_data = mmcc_pxo_dsi1_dsi2_byte, 2230 2158 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2231 2159 .ops = &clk_rcg_bypass2_ops, 2232 2160 .flags = CLK_SET_RATE_PARENT, ··· 2242 2170 .enable_mask = BIT(0), 2243 2171 .hw.init = &(struct clk_init_data){ 2244 2172 .name = "dsi1_byte_clk", 2245 - .parent_names = (const char *[]){ "dsi1_byte_src" }, 2173 + .parent_hws = (const struct clk_hw*[]){ 2174 + &dsi1_byte_src.clkr.hw 2175 + }, 2246 2176 .num_parents = 1, 2247 2177 .ops = &clk_branch_ops, 2248 2178 .flags = CLK_SET_RATE_PARENT, ··· 2267 2193 .enable_mask = BIT(2), 2268 2194 .hw.init = &(struct clk_init_data){ 2269 2195 .name = "dsi2_byte_src", 2270 - .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2196 + .parent_data = mmcc_pxo_dsi1_dsi2_byte, 2271 2197 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2272 2198 .ops = &clk_rcg_bypass2_ops, 2273 2199 .flags = CLK_SET_RATE_PARENT, ··· 2283 2209 .enable_mask = BIT(0), 2284 2210 .hw.init = &(struct clk_init_data){ 2285 2211 .name = "dsi2_byte_clk", 2286 - .parent_names = (const char *[]){ "dsi2_byte_src" }, 2212 + .parent_hws = (const struct clk_hw*[]){ 2213 + &dsi2_byte_src.clkr.hw 2214 + }, 2287 2215 .num_parents = 1, 2288 2216 .ops = &clk_branch_ops, 2289 2217 .flags = CLK_SET_RATE_PARENT, ··· 2308 2232 .enable_mask = BIT(2), 2309 2233 .hw.init = &(struct clk_init_data){ 2310 2234 .name = "dsi1_esc_src", 2311 - .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2235 + .parent_data = mmcc_pxo_dsi1_dsi2_byte, 2312 2236 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2313 2237 .ops = &clk_rcg_esc_ops, 2314 2238 }, ··· 2323 2247 .enable_mask = BIT(0), 2324 2248 .hw.init = &(struct clk_init_data){ 2325 2249 .name = "dsi1_esc_clk", 2326 - .parent_names = (const char *[]){ "dsi1_esc_src" }, 2250 + .parent_hws = (const struct clk_hw*[]){ 2251 + &dsi1_esc_src.clkr.hw 2252 + }, 2327 2253 .num_parents = 1, 2328 2254 .ops = &clk_branch_ops, 2329 2255 .flags = CLK_SET_RATE_PARENT, ··· 2348 2270 .enable_mask = BIT(2), 2349 2271 .hw.init = &(struct clk_init_data){ 2350 2272 .name = "dsi2_esc_src", 2351 - .parent_names = mmcc_pxo_dsi1_dsi2_byte, 2273 + .parent_data = mmcc_pxo_dsi1_dsi2_byte, 2352 2274 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), 2353 2275 .ops = &clk_rcg_esc_ops, 2354 2276 }, ··· 2363 2285 .enable_mask = BIT(0), 2364 2286 .hw.init = &(struct clk_init_data){ 2365 2287 .name = "dsi2_esc_clk", 2366 - .parent_names = (const char *[]){ "dsi2_esc_src" }, 2288 + .parent_hws = (const struct clk_hw*[]){ 2289 + &dsi2_esc_src.clkr.hw 2290 + }, 2367 2291 .num_parents = 1, 2368 2292 .ops = &clk_branch_ops, 2369 2293 .flags = CLK_SET_RATE_PARENT, ··· 2397 2317 .enable_mask = BIT(2), 2398 2318 .hw.init = &(struct clk_init_data){ 2399 2319 .name = "dsi1_pixel_src", 2400 - .parent_names = mmcc_pxo_dsi2_dsi1, 2320 + .parent_data = mmcc_pxo_dsi2_dsi1, 2401 2321 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2402 2322 .ops = &clk_rcg_pixel_ops, 2403 2323 }, ··· 2412 2332 .enable_mask = BIT(0), 2413 2333 .hw.init = &(struct clk_init_data){ 2414 2334 .name = "mdp_pclk1_clk", 2415 - .parent_names = (const char *[]){ "dsi1_pixel_src" }, 2335 + .parent_hws = (const struct clk_hw*[]){ 2336 + &dsi1_pixel_src.clkr.hw 2337 + }, 2416 2338 .num_parents = 1, 2417 2339 .ops = &clk_branch_ops, 2418 2340 .flags = CLK_SET_RATE_PARENT, ··· 2446 2364 .enable_mask = BIT(2), 2447 2365 .hw.init = &(struct clk_init_data){ 2448 2366 .name = "dsi2_pixel_src", 2449 - .parent_names = mmcc_pxo_dsi2_dsi1, 2367 + .parent_data = mmcc_pxo_dsi2_dsi1, 2450 2368 .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), 2451 2369 .ops = &clk_rcg_pixel_ops, 2452 2370 }, ··· 2461 2379 .enable_mask = BIT(0), 2462 2380 .hw.init = &(struct clk_init_data){ 2463 2381 .name = "mdp_pclk2_clk", 2464 - .parent_names = (const char *[]){ "dsi2_pixel_src" }, 2382 + .parent_hws = (const struct clk_hw*[]){ 2383 + &dsi2_pixel_src.clkr.hw 2384 + }, 2465 2385 .num_parents = 1, 2466 2386 .ops = &clk_branch_ops, 2467 2387 .flags = CLK_SET_RATE_PARENT,