tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: qcom: mmcc-msm8960: move clock parent tables down

Move clock parent tables down, after the PLL declrataions, so that we
can use pll hw clock fields in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013)
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220623120418.250589-9-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson d226c5f0 53e1409c

+46 -46
+46 -46
drivers/clk/qcom/mmcc-msm8960.c
··· 41 41 42 42 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } 43 43 44 + static struct clk_pll pll2 = { 45 + .l_reg = 0x320, 46 + .m_reg = 0x324, 47 + .n_reg = 0x328, 48 + .config_reg = 0x32c, 49 + .mode_reg = 0x31c, 50 + .status_reg = 0x334, 51 + .status_bit = 16, 52 + .clkr.hw.init = &(struct clk_init_data){ 53 + .name = "pll2", 54 + .parent_names = (const char *[]){ "pxo" }, 55 + .num_parents = 1, 56 + .ops = &clk_pll_ops, 57 + }, 58 + }; 59 + 60 + static struct clk_pll pll15 = { 61 + .l_reg = 0x33c, 62 + .m_reg = 0x340, 63 + .n_reg = 0x344, 64 + .config_reg = 0x348, 65 + .mode_reg = 0x338, 66 + .status_reg = 0x350, 67 + .status_bit = 16, 68 + .clkr.hw.init = &(struct clk_init_data){ 69 + .name = "pll15", 70 + .parent_names = (const char *[]){ "pxo" }, 71 + .num_parents = 1, 72 + .ops = &clk_pll_ops, 73 + }, 74 + }; 75 + 76 + static const struct pll_config pll15_config = { 77 + .l = 33, 78 + .m = 1, 79 + .n = 3, 80 + .vco_val = 0x2 << 16, 81 + .vco_mask = 0x3 << 16, 82 + .pre_div_val = 0x0, 83 + .pre_div_mask = BIT(19), 84 + .post_div_val = 0x0, 85 + .post_div_mask = 0x3 << 20, 86 + .mn_ena_mask = BIT(22), 87 + .main_output_mask = BIT(23), 88 + }; 89 + 44 90 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { 45 91 { P_PXO, 0 }, 46 92 { P_PLL8, 2 }, ··· 149 103 "pxo", 150 104 "dsi1pllbyte", 151 105 "dsi2pllbyte", 152 - }; 153 - 154 - static struct clk_pll pll2 = { 155 - .l_reg = 0x320, 156 - .m_reg = 0x324, 157 - .n_reg = 0x328, 158 - .config_reg = 0x32c, 159 - .mode_reg = 0x31c, 160 - .status_reg = 0x334, 161 - .status_bit = 16, 162 - .clkr.hw.init = &(struct clk_init_data){ 163 - .name = "pll2", 164 - .parent_names = (const char *[]){ "pxo" }, 165 - .num_parents = 1, 166 - .ops = &clk_pll_ops, 167 - }, 168 - }; 169 - 170 - static struct clk_pll pll15 = { 171 - .l_reg = 0x33c, 172 - .m_reg = 0x340, 173 - .n_reg = 0x344, 174 - .config_reg = 0x348, 175 - .mode_reg = 0x338, 176 - .status_reg = 0x350, 177 - .status_bit = 16, 178 - .clkr.hw.init = &(struct clk_init_data){ 179 - .name = "pll15", 180 - .parent_names = (const char *[]){ "pxo" }, 181 - .num_parents = 1, 182 - .ops = &clk_pll_ops, 183 - }, 184 - }; 185 - 186 - static const struct pll_config pll15_config = { 187 - .l = 33, 188 - .m = 1, 189 - .n = 3, 190 - .vco_val = 0x2 << 16, 191 - .vco_mask = 0x3 << 16, 192 - .pre_div_val = 0x0, 193 - .pre_div_mask = BIT(19), 194 - .post_div_val = 0x0, 195 - .post_div_mask = 0x3 << 20, 196 - .mn_ena_mask = BIT(22), 197 - .main_output_mask = BIT(23), 198 106 }; 199 107 200 108 static struct freq_tbl clk_tbl_cam[] = {