Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: phy-snps-eusb2: add support for exynos2200
The Exynos2200 SoC reuses the Synopsis eUSB2 PHY IP, alongside an
external repeater, for USB 2.0. Add support for it to the existing
driver, while keeping in mind that it requires enabled more than the
reference clock.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250504144527.1723980-10-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Ivaylo Ivanov
and committed by
Vinod Koul
c4098f3e
e36a5d1e
+159
-5
+1
-1
drivers/phy/Kconfig
+1
-1
drivers/phy/Kconfig
+158
-4
drivers/phy/phy-snps-eusb2.c
+158
-4
drivers/phy/phy-snps-eusb2.c
···
13
13
#include <linux/regulator/consumer.h>
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14
#include <linux/reset.h>
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15
16
+
#define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0)
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#define USB_PHY_RST_MASK GENMASK(1, 0)
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#define UTMI_PORT_RST_MASK GENMASK(5, 4)
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+
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#define EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON (0x4)
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#define RPTR_MODE BIT(10)
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#define FSEL_20_MHZ_VAL (0x1)
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#define FSEL_24_MHZ_VAL (0x2)
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#define FSEL_26_MHZ_VAL (0x3)
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#define FSEL_48_MHZ_VAL (0x2)
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+
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#define EXYNOS_USB_PHY_CFG_PLLCFG0 (0x8)
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#define PHY_CFG_PLL_FB_DIV_19_8_MASK GENMASK(19, 8)
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#define DIV_19_8_19_2_MHZ_VAL (0x170)
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#define DIV_19_8_20_MHZ_VAL (0x160)
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#define DIV_19_8_24_MHZ_VAL (0x120)
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#define DIV_19_8_26_MHZ_VAL (0x107)
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#define DIV_19_8_48_MHZ_VAL (0x120)
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+
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#define EXYNOS_USB_PHY_CFG_PLLCFG1 (0xc)
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#define EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK GENMASK(11, 8)
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#define EXYNOS_DIV_11_8_19_2_MHZ_VAL (0x0)
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#define EXYNOS_DIV_11_8_20_MHZ_VAL (0x0)
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#define EXYNOS_DIV_11_8_24_MHZ_VAL (0x0)
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#define EXYNOS_DIV_11_8_26_MHZ_VAL (0x0)
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#define EXYNOS_DIV_11_8_48_MHZ_VAL (0x1)
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+
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#define EXYNOS_PHY_CFG_TX (0x14)
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#define EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK GENMASK(2, 1)
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+
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#define EXYNOS_USB_PHY_UTMI_TESTSE (0x20)
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#define TEST_IDDQ BIT(6)
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#define QCOM_USB_PHY_UTMI_CTRL0 (0x3c)
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#define SLEEPM BIT(0)
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#define OPMODE_MASK GENMASK(4, 3)
···
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struct snps_eusb2_phy_drvdata {
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int (*phy_init)(struct phy *p);
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const char * const *clk_names;
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int num_clks;
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};
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struct snps_eusb2_hsphy {
···
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void __iomem *base;
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struct clk *ref_clk;
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struct clk_bulk_data *clks;
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struct reset_control *phy_reset;
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struct regulator_bulk_data vregs[EUSB2_NUM_VREGS];
···
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u32 div_11_8_val;
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};
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static const struct snps_eusb2_ref_clk exynos_eusb2_ref_clk[] = {
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{ 19200000, FSEL_19_2_MHZ_VAL, DIV_19_8_19_2_MHZ_VAL, EXYNOS_DIV_11_8_19_2_MHZ_VAL },
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{ 20000000, FSEL_20_MHZ_VAL, DIV_19_8_20_MHZ_VAL, EXYNOS_DIV_11_8_20_MHZ_VAL },
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{ 24000000, FSEL_24_MHZ_VAL, DIV_19_8_24_MHZ_VAL, EXYNOS_DIV_11_8_24_MHZ_VAL },
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{ 26000000, FSEL_26_MHZ_VAL, DIV_19_8_26_MHZ_VAL, EXYNOS_DIV_11_8_26_MHZ_VAL },
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{ 48000000, FSEL_48_MHZ_VAL, DIV_19_8_48_MHZ_VAL, EXYNOS_DIV_11_8_48_MHZ_VAL },
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};
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static int exynos_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy)
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{
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const struct snps_eusb2_ref_clk *config = NULL;
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unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
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+
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for (int i = 0; i < ARRAY_SIZE(exynos_eusb2_ref_clk); i++) {
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if (exynos_eusb2_ref_clk[i].freq == ref_clk_freq) {
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config = &exynos_eusb2_ref_clk[i];
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break;
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}
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}
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+
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if (!config) {
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dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
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return -EINVAL;
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}
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+
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON,
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FSEL_MASK,
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FIELD_PREP(FSEL_MASK, config->fsel_val));
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+
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG0,
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PHY_CFG_PLL_FB_DIV_19_8_MASK,
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FIELD_PREP(PHY_CFG_PLL_FB_DIV_19_8_MASK,
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config->div_7_0_val));
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+
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_CFG_PLLCFG1,
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EXYNOS_PHY_CFG_PLL_FB_DIV_11_8_MASK,
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config->div_11_8_val);
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return 0;
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}
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+
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static const struct snps_eusb2_ref_clk qcom_eusb2_ref_clk[] = {
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{ 19200000, FSEL_19_2_MHZ_VAL, DIV_7_0_19_2_MHZ_VAL, DIV_11_8_19_2_MHZ_VAL },
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{ 38400000, FSEL_38_4_MHZ_VAL, DIV_7_0_38_4_MHZ_VAL, DIV_11_8_38_4_MHZ_VAL },
···
314
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return 0;
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}
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+
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static int exynos_snps_eusb2_hsphy_init(struct phy *p)
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{
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struct snps_eusb2_hsphy *phy = phy_get_drvdata(p);
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int ret;
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+
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST,
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USB_PHY_RST_MASK | UTMI_PORT_RST_MASK,
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USB_PHY_RST_MASK | UTMI_PORT_RST_MASK);
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fsleep(50); /* required after holding phy in reset */
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON,
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RPTR_MODE, RPTR_MODE);
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/* update ref_clk related registers */
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ret = exynos_eusb2_ref_clk_init(phy);
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if (ret)
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return ret;
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+
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/* default parameter: tx fsls-vref */
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_PHY_CFG_TX,
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EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK,
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FIELD_PREP(EXYNOS_PHY_CFG_TX_FSLS_VREF_TUNE_MASK, 0x0));
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_UTMI_TESTSE,
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TEST_IDDQ, 0);
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fsleep(10); /* required after releasing test_iddq */
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST,
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USB_PHY_RST_MASK, 0);
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_COMMON,
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PHY_ENABLE, PHY_ENABLE);
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snps_eusb2_hsphy_write_mask(phy->base, EXYNOS_USB_PHY_HS_PHY_CTRL_RST,
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UTMI_PORT_RST_MASK, 0);
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return 0;
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}
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static const char * const exynos_eusb2_hsphy_clock_names[] = {
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"ref", "bus", "ctrl",
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};
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static const struct snps_eusb2_phy_drvdata exynos2200_snps_eusb2_phy = {
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.phy_init = exynos_snps_eusb2_hsphy_init,
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.clk_names = exynos_eusb2_hsphy_clock_names,
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.num_clks = ARRAY_SIZE(exynos_eusb2_hsphy_clock_names),
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};
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static int qcom_snps_eusb2_hsphy_init(struct phy *p)
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{
···
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return 0;
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}
442
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static const char * const qcom_eusb2_hsphy_clock_names[] = {
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"ref",
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};
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+
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static const struct snps_eusb2_phy_drvdata sm8550_snps_eusb2_phy = {
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.phy_init = qcom_snps_eusb2_hsphy_init,
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.clk_names = qcom_eusb2_hsphy_clock_names,
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.num_clks = ARRAY_SIZE(qcom_eusb2_hsphy_clock_names),
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};
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static int snps_eusb2_hsphy_init(struct phy *p)
···
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goto disable_vreg;
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}
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-
ret = clk_prepare_enable(phy->ref_clk);
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ret = clk_bulk_prepare_enable(phy->data->num_clks, phy->clks);
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if (ret) {
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dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
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goto disable_vreg;
···
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return 0;
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disable_ref_clk:
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-
clk_disable_unprepare(phy->ref_clk);
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clk_bulk_disable_unprepare(phy->data->num_clks, phy->clks);
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disable_vreg:
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regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
···
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if (IS_ERR(phy->phy_reset))
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return PTR_ERR(phy->phy_reset);
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549
-
phy->ref_clk = devm_clk_get(dev, "ref");
550
-
if (IS_ERR(phy->ref_clk))
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phy->clks = devm_kcalloc(dev, phy->data->num_clks, sizeof(*phy->clks),
419
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GFP_KERNEL);
420
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if (!phy->clks)
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return -ENOMEM;
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+
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+
for (int i = 0; i < phy->data->num_clks; ++i)
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phy->clks[i].id = phy->data->clk_names[i];
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+
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+
ret = devm_clk_bulk_get(dev, phy->data->num_clks, phy->clks);
427
+
if (ret)
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return dev_err_probe(dev, ret,
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"failed to get phy clock(s)\n");
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+
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+
phy->ref_clk = NULL;
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for (int i = 0; i < phy->data->num_clks; ++i) {
433
+
if (!strcmp(phy->clks[i].id, "ref")) {
434
+
phy->ref_clk = phy->clks[i].clk;
435
+
break;
436
+
}
437
+
}
438
+
439
+
if (IS_ERR_OR_NULL(phy->ref_clk))
551
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return dev_err_probe(dev, PTR_ERR(phy->ref_clk),
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"failed to get ref clk\n");
553
442
···
607
456
{
608
457
.compatible = "qcom,sm8550-snps-eusb2-phy",
609
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.data = &sm8550_snps_eusb2_phy,
459
+
}, {
460
+
.compatible = "samsung,exynos2200-eusb2-phy",
461
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.data = &exynos2200_snps_eusb2_phy,
610
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}, { },
611
463
};
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MODULE_DEVICE_TABLE(of, snps_eusb2_hsphy_of_match_table);