tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

clk: renesas: r9a08g045: Drop power domain instantiation

Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain instantiations.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-6-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Claudiu Beznea and committed by
Geert Uytterhoeven c4969595 5cd33db5

+93 -123
+93 -123
drivers/clk/renesas/r9a08g045-cpg.c
··· 192 192 }; 193 193 194 194 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 195 - DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0, 0), 196 - DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0, 0), 197 - DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1, 0), 198 - DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0, 0), 199 - DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1, 0), 200 - DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0, 0), 201 - DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1, 0), 202 - DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0, 0), 203 - DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1, 0), 204 - DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2, 0), 205 - DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3, 0), 206 - DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4, 0), 207 - DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5, 0), 208 - DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6, 0), 209 - DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7, 0), 210 - DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8, 0), 211 - DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9, 0), 212 - DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10, 0), 213 - DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11, 0), 214 - DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0, 0), 215 - DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1, 0), 216 - DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2, 0), 217 - DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3, 0), 218 - DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4, 0), 219 - DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5, 0), 220 - DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6, 0), 221 - DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7, 0), 222 - DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0, 0), 223 - DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1, 0), 195 + DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0, 196 + MSTOP(BUS_ACPU, BIT(3))), 197 + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0, 198 + MSTOP(BUS_PERI_CPU, BIT(13))), 199 + DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1, 200 + MSTOP(BUS_PERI_CPU, BIT(13))), 201 + DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0, 202 + MSTOP(BUS_REG1, BIT(2))), 203 + DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1, 204 + MSTOP(BUS_REG1, BIT(3))), 205 + DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0, 206 + MSTOP(BUS_REG0, BIT(0))), 207 + DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1, 208 + MSTOP(BUS_REG0, BIT(0))), 209 + DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0, 210 + MSTOP(BUS_PERI_COM, BIT(0))), 211 + DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1, 212 + MSTOP(BUS_PERI_COM, BIT(0))), 213 + DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2, 214 + MSTOP(BUS_PERI_COM, BIT(0))), 215 + DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3, 216 + MSTOP(BUS_PERI_COM, BIT(0))), 217 + DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4, 218 + MSTOP(BUS_PERI_COM, BIT(1))), 219 + DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5, 220 + MSTOP(BUS_PERI_COM, BIT(1))), 221 + DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6, 222 + MSTOP(BUS_PERI_COM, BIT(1))), 223 + DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7, 224 + MSTOP(BUS_PERI_COM, BIT(1))), 225 + DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8, 226 + MSTOP(BUS_PERI_COM, BIT(11))), 227 + DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9, 228 + MSTOP(BUS_PERI_COM, BIT(11))), 229 + DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10, 230 + MSTOP(BUS_PERI_COM, BIT(11))), 231 + DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11, 232 + MSTOP(BUS_PERI_COM, BIT(11))), 233 + DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0, 234 + MSTOP(BUS_MCPU1, BIT(10))), 235 + DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1, 236 + MSTOP(BUS_MCPU1, BIT(10))), 237 + DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2, 238 + MSTOP(BUS_MCPU1, BIT(11))), 239 + DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3, 240 + MSTOP(BUS_MCPU1, BIT(11))), 241 + DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4, 242 + MSTOP(BUS_MCPU1, BIT(12))), 243 + DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5, 244 + MSTOP(BUS_MCPU1, BIT(12))), 245 + DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6, 246 + MSTOP(BUS_MCPU1, BIT(13))), 247 + DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7, 248 + MSTOP(BUS_MCPU1, BIT(13))), 249 + DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0, 250 + MSTOP(BUS_PERI_COM, BIT(5))), 251 + DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1, 252 + MSTOP(BUS_PERI_COM, BIT(7))), 224 253 DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2, 225 - 0), 226 - DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3, 0), 227 - DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0, 0), 254 + MSTOP(BUS_PERI_COM, BIT(6))), 255 + DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3, 256 + MSTOP(BUS_PERI_COM, BIT(4))), 257 + DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0, 258 + MSTOP(BUS_PERI_COM, BIT(2))), 228 259 DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0, 0), 229 260 DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0), 230 - DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1, 0), 261 + DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1, 262 + MSTOP(BUS_PERI_COM, BIT(3))), 231 263 DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1, 0), 232 264 DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0), 233 - DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0, 0), 234 - DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1, 0), 235 - DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2, 0), 236 - DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3, 0), 237 - DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0, 0), 238 - DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1, 0), 239 - DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2, 0), 240 - DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3, 0), 241 - DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4, 0), 242 - DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5, 0), 265 + DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0, 266 + MSTOP(BUS_MCPU2, BIT(10))), 267 + DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1, 268 + MSTOP(BUS_MCPU2, BIT(11))), 269 + DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2, 270 + MSTOP(BUS_MCPU2, BIT(12))), 271 + DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3, 272 + MSTOP(BUS_MCPU2, BIT(13))), 273 + DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0, 274 + MSTOP(BUS_MCPU2, BIT(1))), 275 + DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1, 276 + MSTOP(BUS_MCPU2, BIT(2))), 277 + DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2, 278 + MSTOP(BUS_MCPU2, BIT(3))), 279 + DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3, 280 + MSTOP(BUS_MCPU2, BIT(4))), 281 + DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4, 282 + MSTOP(BUS_MCPU2, BIT(5))), 283 + DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5, 284 + MSTOP(BUS_MCPU3, BIT(4))), 243 285 DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0), 244 - DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0, 0), 245 - DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1, 0), 246 - DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0, 0), 247 - DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0, 0), 286 + DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0, 287 + MSTOP(BUS_MCPU2, BIT(14))), 288 + DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1, 289 + MSTOP(BUS_MCPU2, BIT(14))), 290 + DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0, 291 + MSTOP(BUS_MCPU2, BIT(15))), 292 + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0, 293 + MSTOP(BUS_MCPU3, GENMASK(8, 7))), 248 294 }; 249 295 250 296 static const struct rzg2l_reset r9a08g045_resets[] = { ··· 340 294 MOD_CLK_BASE + R9A08G045_VBAT_BCLK, 341 295 }; 342 296 343 - static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { 344 - /* Keep always-on domain on the first position for proper domains registration. */ 345 - DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, 346 - DEF_REG_CONF(0, 0), 347 - GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE), 348 - DEF_PD("gic", R9A08G045_PD_GIC, 349 - DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)), 350 - GENPD_FLAG_ALWAYS_ON), 351 - DEF_PD("ia55", R9A08G045_PD_IA55, 352 - DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)), 353 - GENPD_FLAG_ALWAYS_ON), 354 - DEF_PD("dmac", R9A08G045_PD_DMAC, 355 - DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)), 356 - GENPD_FLAG_ALWAYS_ON), 357 - DEF_PD("wdt0", R9A08G045_PD_WDT0, 358 - DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 359 - GENPD_FLAG_IRQ_SAFE), 360 - DEF_PD("sdhi0", R9A08G045_PD_SDHI0, 361 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0), 362 - DEF_PD("sdhi1", R9A08G045_PD_SDHI1, 363 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0), 364 - DEF_PD("sdhi2", R9A08G045_PD_SDHI2, 365 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0), 366 - DEF_PD("ssi0", R9A08G045_PD_SSI0, 367 - DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0), 368 - DEF_PD("ssi1", R9A08G045_PD_SSI1, 369 - DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0), 370 - DEF_PD("ssi2", R9A08G045_PD_SSI2, 371 - DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0), 372 - DEF_PD("ssi3", R9A08G045_PD_SSI3, 373 - DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0), 374 - DEF_PD("usb0", R9A08G045_PD_USB0, 375 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0), 376 - DEF_PD("usb1", R9A08G045_PD_USB1, 377 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)), 0), 378 - DEF_PD("usb-phy", R9A08G045_PD_USB_PHY, 379 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)), 0), 380 - DEF_PD("eth0", R9A08G045_PD_ETHER0, 381 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0), 382 - DEF_PD("eth1", R9A08G045_PD_ETHER1, 383 - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0), 384 - DEF_PD("i2c0", R9A08G045_PD_I2C0, 385 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0), 386 - DEF_PD("i2c1", R9A08G045_PD_I2C1, 387 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0), 388 - DEF_PD("i2c2", R9A08G045_PD_I2C2, 389 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0), 390 - DEF_PD("i2c3", R9A08G045_PD_I2C3, 391 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0), 392 - DEF_PD("scif0", R9A08G045_PD_SCIF0, 393 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0), 394 - DEF_PD("scif1", R9A08G045_PD_SCIF1, 395 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)), 0), 396 - DEF_PD("scif2", R9A08G045_PD_SCIF2, 397 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)), 0), 398 - DEF_PD("scif3", R9A08G045_PD_SCIF3, 399 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)), 0), 400 - DEF_PD("scif4", R9A08G045_PD_SCIF4, 401 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0), 402 - DEF_PD("scif5", R9A08G045_PD_SCIF5, 403 - DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0), 404 - DEF_PD("adc", R9A08G045_PD_ADC, 405 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), 406 - DEF_PD("tsu", R9A08G045_PD_TSU, 407 - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0), 408 - DEF_PD("vbat", R9A08G045_PD_VBAT, 409 - DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), 410 - GENPD_FLAG_ALWAYS_ON), 411 - DEF_PD("rtc", R9A08G045_PD_RTC, 412 - DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0), 413 - }; 414 - 415 297 const struct rzg2l_cpg_info r9a08g045_cpg_info = { 416 298 /* Core Clocks */ 417 299 .core_clks = r9a08g045_core_clks, ··· 359 385 /* Resets */ 360 386 .resets = r9a08g045_resets, 361 387 .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ 362 - 363 - /* Power domains */ 364 - .pm_domains = r9a08g045_pm_domains, 365 - .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains), 366 388 367 389 .has_clk_mon_regs = true, 368 390 };