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Docs: iio: ad4030: Add double PWM SPI offload doc
Document double PWM setup SPI offload wiring schema.
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Marcelo Schmitt
and committed by
Jonathan Cameron
c4c1c5b7
10373521
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Documentation/iio/ad4030.rst
+39
Documentation/iio/ad4030.rst
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In this mode, both channels conversion results are bit interleaved one SDO line.
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As such the wiring is the same as `One lane mode`_.
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SPI offload wiring
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^^^^^^^^^^^^^^^^^^
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.. code-block::
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+-------------+ +-------------+
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| CNV |<-----+--| GPIO |
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| | +--| PWM0 |
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| | | |
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| | +--| PWM1 |
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| | | +-------------+
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| | +->| TRIGGER |
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| CS |<--------| CS |
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| | | |
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| ADC | | SPI |
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| | | |
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| SDI |<--------| SDO |
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| SDO |-------->| SDI |
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| SCLK |<--------| SCLK |
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+-------------+ +-------------+
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In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required.
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The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin.
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The SPI offload will have a ``trigger-sources`` property to indicate the SPI
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offload (PWM) trigger source. For AD4030 and similar ADCs, there are two
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possible data transfer zones for sample N. One of them (zone 1) starts after the
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data conversion for sample N is complete while the other one (zone 2) starts 9.8
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nanoseconds after the rising edge of CNV for sample N + 1.
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The configuration depicted in the above diagram is intended to perform data
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transfer in zone 2. To achieve high sample rates while meeting ADC timing
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requirements, an offset is added between the rising edges of PWM0 and PWM1 to
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delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This
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requires a specialized PWM controller that can provide such an offset.
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The `AD4630-FMC HDL project`_, for example, can be configured to sample AD4030
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data during zone 2 data read window.
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.. _AD4630-FMC HDL project: https://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.html
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SPI Clock mode
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--------------
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