tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
"A handful of clk driver fixes:

- Fix an OOB issue in the Mediatek mt8365 driver where arrays of clks
are mismatched in size

- Use the proper clk_ops for a few clks in the Mediatek mt8365 driver

- Stop using abs() in clk_composite_determine_rate() because 64-bit
math goes wrong on large unsigned long numbers that are subtracted
and passed into abs()

- Zero initialize a struct clk_init_data in clk-loongson2 to avoid
stack junk confusing clk_hw_register()

- Actually use a pointer to __iomem for writel() in
pxa3xx_clk_update_accr() so we don't oops"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: pxa: fix NULL pointer dereference in pxa3xx_clk_update_accr
clk: clk-loongson2: Zero init clk_init_data
clk: mediatek: mt8365: Fix inverted topclk operations
clk: composite: Fix handling of high clock rates
clk: mediatek: mt8365: Fix index issue

Linus Torvalds c6cf6be9 1639fae5

+21 -6
+4 -1
drivers/clk/clk-composite.c
··· 119 119 if (ret) 120 120 continue; 121 121 122 - rate_diff = abs(req->rate - tmp_req.rate); 122 + if (req->rate >= tmp_req.rate) 123 + rate_diff = req->rate - tmp_req.rate; 124 + else 125 + rate_diff = tmp_req.rate - req->rate; 123 126 124 127 if (!rate_diff || !req->best_parent_hw 125 128 || best_rate_diff > rate_diff) {
+1 -1
drivers/clk/clk-loongson2.c
··· 40 40 { 41 41 int ret; 42 42 struct clk_hw *hw; 43 - struct clk_init_data init; 43 + struct clk_init_data init = { }; 44 44 45 45 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); 46 46 if (!hw)
+15 -3
drivers/clk/mediatek/clk-mt8365.c
··· 23 23 static DEFINE_SPINLOCK(mt8365_clk_lock); 24 24 25 25 static const struct mtk_fixed_clk top_fixed_clks[] = { 26 + FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), 26 27 FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), 27 28 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 28 29 75000000), ··· 560 559 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 561 560 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 562 561 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 562 + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel", 563 + 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 564 + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel", 565 + 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 566 + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel", 567 + 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 568 + DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel", 569 + 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 563 570 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 564 571 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 565 572 }; ··· 592 583 593 584 #define GATE_TOP0(_id, _name, _parent, _shift) \ 594 585 GATE_MTK(_id, _name, _parent, &top0_cg_regs, \ 595 - _shift, &mtk_clk_gate_ops_no_setclr_inv) 586 + _shift, &mtk_clk_gate_ops_no_setclr) 596 587 597 588 #define GATE_TOP1(_id, _name, _parent, _shift) \ 598 589 GATE_MTK(_id, _name, _parent, &top1_cg_regs, \ 599 - _shift, &mtk_clk_gate_ops_no_setclr) 590 + _shift, &mtk_clk_gate_ops_no_setclr_inv) 600 591 601 592 #define GATE_TOP2(_id, _name, _parent, _shift) \ 602 593 GATE_MTK(_id, _name, _parent, &top2_cg_regs, \ 603 - _shift, &mtk_clk_gate_ops_no_setclr) 594 + _shift, &mtk_clk_gate_ops_no_setclr_inv) 604 595 605 596 static const struct mtk_gate top_clk_gates[] = { 606 597 GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10), ··· 705 696 GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), 706 697 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), 707 698 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), 699 + GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11), 708 700 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), 709 701 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), 710 702 GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), ··· 727 717 GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), 728 718 GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), 729 719 GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), 720 + GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs, 721 + 17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED), 730 722 GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), 731 723 GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), 732 724 GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),
+1 -1
drivers/clk/pxa/clk-pxa3xx.c
··· 164 164 accr &= ~disable; 165 165 accr |= enable; 166 166 167 - writel(accr, ACCR); 167 + writel(accr, clk_regs + ACCR); 168 168 if (xclkcfg) 169 169 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg)); 170 170