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ARM: dts: r9a06g032: Describe GMAC2

The RZ/N1 SoC includes two MACs named GMACx that are compatible with the
"snps,dwmac" driver. GMAC1 is connected directly to the MII converter
port 1. GMAC2 however can be used as the MAC for the switch CPU
management port or can be muxed to be connected directly to the MII
converter port 2. This commit adds the description for the GMAC2 which
will be used by the switch description.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://lore.kernel.org/r/20220624144001.95518-14-clement.leger@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Clément Léger and committed by
Geert Uytterhoeven c6f60092 dc0f6731

+18
+18
arch/arm/boot/dts/r9a06g032.dtsi
··· 304 304 data-width = <8>; 305 305 }; 306 306 307 + gmac2: ethernet@44002000 { 308 + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 309 + reg = <0x44002000 0x2000>; 310 + interrupt-parent = <&gic>; 311 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 312 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 313 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 314 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 315 + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; 316 + clock-names = "stmmaceth"; 317 + power-domains = <&sysctrl>; 318 + snps,multicast-filter-bins = <256>; 319 + snps,perfect-filter-entries = <128>; 320 + tx-fifo-depth = <2048>; 321 + rx-fifo-depth = <4096>; 322 + status = "disabled"; 323 + }; 324 + 307 325 eth_miic: eth-miic@44030000 { 308 326 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 309 327 #address-cells = <1>;