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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-qmp-pcie: add support for sm8350 platform
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm
SM8350 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221118233242.2904088-7-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
c7005273
c99649c3
+119
-1
+119
-1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+119
-1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
1313
1313
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1314
1314
};
1315
1315
1316
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
1317
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1318
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1319
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1320
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1321
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1322
+
};
1323
+
1324
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1325
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1326
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1327
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1328
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1329
+
};
1330
+
1331
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
1332
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1333
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1334
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1335
+
};
1336
+
1337
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
1338
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1339
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1340
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1341
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1342
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1343
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1344
+
};
1345
+
1346
+
static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
1347
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
1348
+
};
1349
+
1316
1350
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
1317
1351
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1318
1352
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
···
2055
2021
.phy_status = PHYSTATUS_4_20,
2056
2022
};
2057
2023
2024
+
static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
2025
+
.lanes = 1,
2026
+
2027
+
.offsets = &qmp_pcie_offsets_v5,
2028
+
2029
+
.tbls = {
2030
+
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2031
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2032
+
.tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
2033
+
.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
2034
+
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
2035
+
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2036
+
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2037
+
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2038
+
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2039
+
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2040
+
},
2041
+
2042
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2043
+
.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2044
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2045
+
.rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
2046
+
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
2047
+
},
2048
+
2049
+
.clk_list = sc8280xp_pciephy_clk_l,
2050
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2051
+
.reset_list = sdm845_pciephy_reset_l,
2052
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2053
+
.vreg_list = qmp_phy_vreg_l,
2054
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2055
+
.regs = sm8250_pcie_regs_layout,
2056
+
2057
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2058
+
.phy_status = PHYSTATUS,
2059
+
};
2060
+
2061
+
static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
2062
+
.lanes = 2,
2063
+
2064
+
.offsets = &qmp_pcie_offsets_v5,
2065
+
2066
+
.tbls = {
2067
+
.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2068
+
.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2069
+
.tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
2070
+
.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
2071
+
.rx = sm8450_qmp_gen3_pcie_rx_tbl,
2072
+
.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2073
+
.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2074
+
.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2075
+
.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2076
+
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2077
+
},
2078
+
2079
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2080
+
.rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
2081
+
.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
2082
+
.pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
2083
+
.pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
2084
+
},
2085
+
2086
+
.clk_list = sc8280xp_pciephy_clk_l,
2087
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2088
+
.reset_list = sdm845_pciephy_reset_l,
2089
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2090
+
.vreg_list = qmp_phy_vreg_l,
2091
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2092
+
.regs = sm8250_pcie_regs_layout,
2093
+
2094
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2095
+
.phy_status = PHYSTATUS,
2096
+
};
2097
+
2058
2098
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
2059
2099
.lanes = 1,
2060
2100
···
2721
2613
qmp->pipe_clks[0].id = "pipe";
2722
2614
qmp->pipe_clks[1].id = "pipediv2";
2723
2615
2724
-
ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
2616
+
ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
2617
+
if (ret)
2618
+
return ret;
2619
+
2620
+
ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
2725
2621
if (ret)
2726
2622
return ret;
2727
2623
···
2845
2733
}, {
2846
2734
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
2847
2735
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
2736
+
}, {
2737
+
.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
2738
+
.data = &sm8350_qmp_gen3x1_pciephy_cfg,
2739
+
}, {
2740
+
.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
2741
+
.data = &sm8350_qmp_gen3x2_pciephy_cfg,
2848
2742
}, {
2849
2743
.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
2850
2744
.data = &sm8450_qmp_gen3x1_pciephy_cfg,