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Merge tag 'x86_mm_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 mm updates from Borislav Petkov:

- Use the proper accessors when reading CR3 as part of the page level
transitions (5-level to 4-level, the use case being kexec) so that
only the physical address in CR3 is picked up and not flags which are
above the physical mask shift

- Clean up and unify __phys_addr_symbol() definitions

* tag 'x86_mm_for_v6.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
efi/libstub: Fix page table access in 5-level to 4-level paging transition
x86/boot: Fix page table access in 5-level to 4-level paging transition
x86/mm: Unify __phys_addr_symbol()

+20 -20
+7 -4
arch/x86/boot/compressed/pgtable_64.c
··· 3 3 #include <asm/bootparam.h> 4 4 #include <asm/bootparam_utils.h> 5 5 #include <asm/e820/types.h> 6 + #include <asm/pgtable.h> 6 7 #include <asm/processor.h> 7 8 #include "../string.h" 8 9 #include "efi.h" ··· 169 168 * For 4- to 5-level paging transition, set up current CR3 as 170 169 * the first and the only entry in a new top-level page table. 171 170 */ 172 - *trampoline_32bit = __native_read_cr3() | _PAGE_TABLE_NOENC; 171 + *trampoline_32bit = native_read_cr3_pa() | _PAGE_TABLE_NOENC; 173 172 } else { 174 - unsigned long src; 173 + u64 *new_cr3; 174 + pgd_t *pgdp; 175 175 176 176 /* 177 177 * For 5- to 4-level paging transition, copy page table pointed ··· 182 180 * We cannot just point to the page table from trampoline as it 183 181 * may be above 4G. 184 182 */ 185 - src = *(unsigned long *)__native_read_cr3() & PAGE_MASK; 186 - memcpy(trampoline_32bit, (void *)src, PAGE_SIZE); 183 + pgdp = (pgd_t *)native_read_cr3_pa(); 184 + new_cr3 = (u64 *)(native_pgd_val(pgdp[0]) & PTE_PFN_MASK); 185 + memcpy(trampoline_32bit, new_cr3, PAGE_SIZE); 187 186 } 188 187 189 188 toggle_la57(trampoline_32bit);
+11 -3
arch/x86/include/asm/page_64.h
··· 9 9 #include <asm/alternative.h> 10 10 11 11 #include <linux/kmsan-checks.h> 12 + #include <linux/mmdebug.h> 12 13 13 14 /* duplicated to the one in bootmem.h */ 14 15 extern unsigned long max_pfn; ··· 32 31 33 32 #ifdef CONFIG_DEBUG_VIRTUAL 34 33 extern unsigned long __phys_addr(unsigned long); 35 - extern unsigned long __phys_addr_symbol(unsigned long); 36 34 #else 37 35 #define __phys_addr(x) __phys_addr_nodebug(x) 38 - #define __phys_addr_symbol(x) \ 39 - ((unsigned long)(x) - __START_KERNEL_map + phys_base) 40 36 #endif 37 + 38 + static inline unsigned long __phys_addr_symbol(unsigned long x) 39 + { 40 + unsigned long y = x - __START_KERNEL_map; 41 + 42 + /* only check upper bounds since lower bounds will trigger carry */ 43 + VIRTUAL_BUG_ON(y >= KERNEL_IMAGE_SIZE); 44 + 45 + return y + phys_base; 46 + } 41 47 42 48 #define __phys_reloc_hide(x) (x) 43 49
-11
arch/x86/mm/physaddr.c
··· 31 31 return x; 32 32 } 33 33 EXPORT_SYMBOL(__phys_addr); 34 - 35 - unsigned long __phys_addr_symbol(unsigned long x) 36 - { 37 - unsigned long y = x - __START_KERNEL_map; 38 - 39 - /* only check upper bounds since lower bounds will trigger carry */ 40 - VIRTUAL_BUG_ON(y >= KERNEL_IMAGE_SIZE); 41 - 42 - return y + phys_base; 43 - } 44 - EXPORT_SYMBOL(__phys_addr_symbol); 45 34 #endif 46 35 47 36 bool __virt_addr_valid(unsigned long x)
+2 -2
drivers/firmware/efi/libstub/x86-5lvl.c
··· 66 66 bool have_la57 = native_read_cr4() & X86_CR4_LA57; 67 67 bool need_toggle = want_la57 ^ have_la57; 68 68 u64 *pgt = (void *)la57_toggle + PAGE_SIZE; 69 - u64 *cr3 = (u64 *)__native_read_cr3(); 69 + pgd_t *cr3 = (pgd_t *)native_read_cr3_pa(); 70 70 u64 *new_cr3; 71 71 72 72 if (!la57_toggle || !need_toggle) ··· 82 82 new_cr3[0] = (u64)cr3 | _PAGE_TABLE_NOENC; 83 83 } else { 84 84 /* take the new root table pointer from the current entry #0 */ 85 - new_cr3 = (u64 *)(cr3[0] & PAGE_MASK); 85 + new_cr3 = (u64 *)(native_pgd_val(cr3[0]) & PTE_PFN_MASK); 86 86 87 87 /* copy the new root table if it is not 32-bit addressable */ 88 88 if ((u64)new_cr3 > U32_MAX)