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clk: ingenic: Add .set_rate_hook() for PLL clocks

The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Aidan MacDonald and committed by
Stephen Boyd c799a777 d84bf9d6

+7
+3
drivers/clk/ingenic/cgu.c
··· 232 232 233 233 writel(ctl, cgu->base + pll_info->reg); 234 234 235 + if (pll_info->set_rate_hook) 236 + pll_info->set_rate_hook(pll_info, rate, parent_rate); 237 + 235 238 /* If the PLL is enabled, verify that it's stable */ 236 239 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) 237 240 ret = ingenic_pll_check_stable(cgu, pll_info);
+4
drivers/clk/ingenic/cgu.h
··· 46 46 * -1 if there is no enable bit (ie, the PLL is always on) 47 47 * @stable_bit: the index of the stable bit in the PLL control register, or 48 48 * -1 if there is no stable bit 49 + * @set_rate_hook: hook called immediately after updating the CGU register, 50 + * before releasing the spinlock 49 51 */ 50 52 struct ingenic_cgu_pll_info { 51 53 unsigned reg; ··· 63 61 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 64 62 unsigned long rate, unsigned long parent_rate, 65 63 unsigned int *m, unsigned int *n, unsigned int *od); 64 + void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, 65 + unsigned long rate, unsigned long parent_rate); 66 66 }; 67 67 68 68 /**