Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc fixes from Ben Herrenschmidt:
"Here are a few more powerpc fixes for 3.16
There's a small series of 3 patches that fix saving/restoring MMUCR2
when using KVM without which perf goes completely bonkers in the host
system. Another perf fix from Anton that's been rotting away in
patchwork due to my poor eyesight, a couple of compile fixes, a little
addition to the WSP removal by Michael (removing a bit more dead
stuff) and a fix for an embarassing regression with our soft irq
masking"
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc/perf: Never program book3s PMCs with values >= 0x80000000
powerpc: Disable RELOCATABLE for COMPILE_TEST with PPC64
powerpc/perf: Clear MMCR2 when enabling PMU
powerpc/perf: Add PPMU_ARCH_207S define
powerpc/kvm: Remove redundant save of SIER AND MMCR2
powerpc/powernv: Check for IRQHAPPENED before sleeping
powerpc: Clean up MMU_FTRS_A2 and MMU_FTR_TYPE_3E
powerpc/cell: Fix compilation with CONFIG_COREDUMP=n
+37
-37
+2
-1
arch/powerpc/Kconfig
+2
-1
arch/powerpc/Kconfig
···
414
414
config CRASH_DUMP
415
415
bool "Build a kdump crash kernel"
416
416
depends on PPC64 || 6xx || FSL_BOOKE || (44x && !SMP)
417
-
select RELOCATABLE if PPC64 || 44x || FSL_BOOKE
417
+
select RELOCATABLE if (PPC64 && !COMPILE_TEST) || 44x || FSL_BOOKE
418
418
help
419
419
Build a kernel suitable for use as a kdump capture kernel.
420
420
The same kernel binary can be used as production kernel and dump
···
1017
1017
if PPC64
1018
1018
config RELOCATABLE
1019
1019
bool "Build a relocatable kernel"
1020
+
depends on !COMPILE_TEST
1020
1021
select NONSTATIC_KERNEL
1021
1022
help
1022
1023
This builds a kernel image that is capable of running anywhere
+1
-9
arch/powerpc/include/asm/mmu.h
+1
-9
arch/powerpc/include/asm/mmu.h
···
19
19
#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20
20
#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21
21
#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
22
-
#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020)
23
-
#define MMU_FTR_TYPE_47x ASM_CONST(0x00000040)
22
+
#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
24
23
25
24
/*
26
25
* This is individual features
···
105
106
MMU_FTR_CI_LARGE_PAGE
106
107
#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
107
108
MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
108
-
#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
109
-
MMU_FTR_USE_TLBIVAX_BCAST | \
110
-
MMU_FTR_LOCK_BCAST_INVAL | \
111
-
MMU_FTR_USE_TLBRSRV | \
112
-
MMU_FTR_USE_PAIRED_MAS | \
113
-
MMU_FTR_TLBIEL | \
114
-
MMU_FTR_16M_PAGE
115
109
#ifndef __ASSEMBLY__
116
110
#include <asm/cputable.h>
117
111
+1
-2
arch/powerpc/include/asm/perf_event_server.h
+1
-2
arch/powerpc/include/asm/perf_event_server.h
···
61
61
#define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
62
62
#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
63
63
#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
64
-
#define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */
65
-
#define PPMU_EBB 0x00000100 /* supports event based branch */
64
+
#define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */
66
65
67
66
/*
68
67
* Values for flags to get_alternatives()
+1
-1
arch/powerpc/kernel/idle_power7.S
+1
-1
arch/powerpc/kernel/idle_power7.S
-5
arch/powerpc/kvm/book3s_hv_interrupts.S
-5
arch/powerpc/kvm/book3s_hv_interrupts.S
···
127
127
stw r10, HSTATE_PMC + 24(r13)
128
128
stw r11, HSTATE_PMC + 28(r13)
129
129
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
130
-
BEGIN_FTR_SECTION
131
-
mfspr r9, SPRN_SIER
132
-
std r8, HSTATE_MMCR + 40(r13)
133
-
std r9, HSTATE_MMCR + 48(r13)
134
-
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
135
130
31:
136
131
137
132
/*
+1
-11
arch/powerpc/mm/mmu_context_nohash.c
+1
-11
arch/powerpc/mm/mmu_context_nohash.c
···
410
410
} else if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
411
411
first_context = 1;
412
412
last_context = 65535;
413
-
} else
414
-
#ifdef CONFIG_PPC_BOOK3E_MMU
415
-
if (mmu_has_feature(MMU_FTR_TYPE_3E)) {
416
-
u32 mmucfg = mfspr(SPRN_MMUCFG);
417
-
u32 pid_bits = (mmucfg & MMUCFG_PIDSIZE_MASK)
418
-
>> MMUCFG_PIDSIZE_SHIFT;
419
-
first_context = 1;
420
-
last_context = (1UL << (pid_bits + 1)) - 1;
421
-
} else
422
-
#endif
423
-
{
413
+
} else {
424
414
first_context = 1;
425
415
last_context = 255;
426
416
}
+22
-4
arch/powerpc/perf/core-book3s.c
+22
-4
arch/powerpc/perf/core-book3s.c
···
485
485
* check that the PMU supports EBB, meaning those that don't can still
486
486
* use bit 63 of the event code for something else if they wish.
487
487
*/
488
-
return (ppmu->flags & PPMU_EBB) &&
488
+
return (ppmu->flags & PPMU_ARCH_207S) &&
489
489
((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
490
490
}
491
491
···
777
777
if (ppmu->flags & PPMU_HAS_SIER)
778
778
sier = mfspr(SPRN_SIER);
779
779
780
-
if (ppmu->flags & PPMU_EBB) {
780
+
if (ppmu->flags & PPMU_ARCH_207S) {
781
781
pr_info("MMCR2: %016lx EBBHR: %016lx\n",
782
782
mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
783
783
pr_info("EBBRR: %016lx BESCR: %016lx\n",
···
996
996
} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
997
997
998
998
local64_add(delta, &event->count);
999
-
local64_sub(delta, &event->hw.period_left);
999
+
1000
+
/*
1001
+
* A number of places program the PMC with (0x80000000 - period_left).
1002
+
* We never want period_left to be less than 1 because we will program
1003
+
* the PMC with a value >= 0x800000000 and an edge detected PMC will
1004
+
* roll around to 0 before taking an exception. We have seen this
1005
+
* on POWER8.
1006
+
*
1007
+
* To fix this, clamp the minimum value of period_left to 1.
1008
+
*/
1009
+
do {
1010
+
prev = local64_read(&event->hw.period_left);
1011
+
val = prev - delta;
1012
+
if (val < 1)
1013
+
val = 1;
1014
+
} while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1000
1015
}
1001
1016
1002
1017
/*
···
1314
1299
ppmu->config_bhrb(cpuhw->bhrb_filter);
1315
1300
1316
1301
write_mmcr0(cpuhw, mmcr0);
1302
+
1303
+
if (ppmu->flags & PPMU_ARCH_207S)
1304
+
mtspr(SPRN_MMCR2, 0);
1317
1305
1318
1306
/*
1319
1307
* Enable instruction sampling if necessary
···
1714
1696
1715
1697
if (has_branch_stack(event)) {
1716
1698
/* PMU has BHRB enabled */
1717
-
if (!(ppmu->flags & PPMU_BHRB))
1699
+
if (!(ppmu->flags & PPMU_ARCH_207S))
1718
1700
return -EOPNOTSUPP;
1719
1701
}
1720
1702
+1
-1
arch/powerpc/perf/power8-pmu.c
+1
-1
arch/powerpc/perf/power8-pmu.c
···
792
792
.get_constraint = power8_get_constraint,
793
793
.get_alternatives = power8_get_alternatives,
794
794
.disable_pmc = power8_disable_pmc,
795
-
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
795
+
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S,
796
796
.n_generic = ARRAY_SIZE(power8_generic_events),
797
797
.generic_events = power8_generic_events,
798
798
.cache_events = &power8_cache_events,
+2
arch/powerpc/platforms/cell/spu_syscalls.c
+2
arch/powerpc/platforms/cell/spu_syscalls.c
+2
-1
arch/powerpc/platforms/cell/spufs/Makefile
+2
-1
arch/powerpc/platforms/cell/spufs/Makefile
···
1
1
2
2
obj-$(CONFIG_SPU_FS) += spufs.o
3
-
spufs-y += inode.o file.o context.o syscalls.o coredump.o
3
+
spufs-y += inode.o file.o context.o syscalls.o
4
4
spufs-y += sched.o backing_ops.o hw_ops.o run.o gang.o
5
5
spufs-y += switch.o fault.o lscsa_alloc.o
6
+
spufs-$(CONFIG_COREDUMP) += coredump.o
6
7
7
8
# magic for the trace events
8
9
CFLAGS_sched.o := -I$(src)
+4
-2
arch/powerpc/platforms/cell/spufs/syscalls.c
+4
-2
arch/powerpc/platforms/cell/spufs/syscalls.c
···
79
79
struct spufs_calls spufs_calls = {
80
80
.create_thread = do_spu_create,
81
81
.spu_run = do_spu_run,
82
-
.coredump_extra_notes_size = spufs_coredump_extra_notes_size,
83
-
.coredump_extra_notes_write = spufs_coredump_extra_notes_write,
84
82
.notify_spus_active = do_notify_spus_active,
85
83
.owner = THIS_MODULE,
84
+
#ifdef CONFIG_COREDUMP
85
+
.coredump_extra_notes_size = spufs_coredump_extra_notes_size,
86
+
.coredump_extra_notes_write = spufs_coredump_extra_notes_write,
87
+
#endif
86
88
};