Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata fixes from Tejun Heo:
"Assorted libata updates.
The most critical one is a fix for ahci oops during boot. Also, a new
smallish platform ahci driver is added and sata_inic162x is marked
clearly as experimental (it whines during boot too) as data corruption
seems rather common on the device and it's unlikely to get any love in
the foreseeable future. If the whining doesn't draw any attention, I
think we'd probably be better of making the driver depend on BROKEN in
a couple releases"
This is v2 of this pull request with fixed dependencies for ahci_imx.
* 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
ahci_imx: depend on CONFIG_MFD_SYSCON
ahci_imx: add ahci sata support on imx platforms
ARM: imx6q: update the sata bits definitions of gpr13
ahci: fix Null pointer dereference in achi_host_active()
libata: make it clear that sata_inic162x is experimental
libata: replace strict_strtol() with kstrtol()
ata: Fix DVD not dectected at some platform with Wellsburg PCH
+358
-42
+10
-1
drivers/ata/Kconfig
+10
-1
drivers/ata/Kconfig
···
97
97
98
98
If unsure, say N.
99
99
100
+
config AHCI_IMX
101
+
tristate "Freescale i.MX AHCI SATA support"
102
+
depends on SATA_AHCI_PLATFORM && MFD_SYSCON
103
+
help
104
+
This option enables support for the Freescale i.MX SoC's
105
+
onboard AHCI SATA.
106
+
107
+
If unsure, say N.
108
+
100
109
config SATA_FSL
101
110
tristate "Freescale 3.0Gbps SATA support"
102
111
depends on FSL_SOC
···
116
107
If unsure, say N.
117
108
118
109
config SATA_INIC162X
119
-
tristate "Initio 162x SATA support"
110
+
tristate "Initio 162x SATA support (Very Experimental)"
120
111
depends on PCI
121
112
help
122
113
This option enables support for Initio 162x Serial ATA.
+1
drivers/ata/Makefile
+1
drivers/ata/Makefile
+8
-1
drivers/ata/ahci.c
+8
-1
drivers/ata/ahci.c
···
1146
1146
return rc;
1147
1147
1148
1148
for (i = 0; i < host->n_ports; i++) {
1149
+
const char* desc;
1149
1150
struct ahci_port_priv *pp = host->ports[i]->private_data;
1151
+
1152
+
/* pp is NULL for dummy ports */
1153
+
if (pp)
1154
+
desc = pp->irq_desc;
1155
+
else
1156
+
desc = dev_driver_string(host->dev);
1150
1157
1151
1158
rc = devm_request_threaded_irq(host->dev,
1152
1159
irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1153
-
pp->irq_desc, host->ports[i]);
1160
+
desc, host->ports[i]);
1154
1161
if (rc)
1155
1162
goto out_free_irqs;
1156
1163
}
+236
drivers/ata/ahci_imx.c
+236
drivers/ata/ahci_imx.c
···
1
+
/*
2
+
* Freescale IMX AHCI SATA platform driver
3
+
* Copyright 2013 Freescale Semiconductor, Inc.
4
+
*
5
+
* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify it
8
+
* under the terms and conditions of the GNU General Public License,
9
+
* version 2, as published by the Free Software Foundation.
10
+
*
11
+
* This program is distributed in the hope it will be useful, but WITHOUT
12
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14
+
* more details.
15
+
*
16
+
* You should have received a copy of the GNU General Public License along with
17
+
* this program. If not, see <http://www.gnu.org/licenses/>.
18
+
*/
19
+
20
+
#include <linux/kernel.h>
21
+
#include <linux/module.h>
22
+
#include <linux/platform_device.h>
23
+
#include <linux/regmap.h>
24
+
#include <linux/ahci_platform.h>
25
+
#include <linux/of_device.h>
26
+
#include <linux/mfd/syscon.h>
27
+
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
28
+
#include "ahci.h"
29
+
30
+
enum {
31
+
HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
32
+
};
33
+
34
+
struct imx_ahci_priv {
35
+
struct platform_device *ahci_pdev;
36
+
struct clk *sata_ref_clk;
37
+
struct clk *ahb_clk;
38
+
struct regmap *gpr;
39
+
};
40
+
41
+
static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
42
+
{
43
+
int ret = 0;
44
+
unsigned int reg_val;
45
+
struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
46
+
47
+
imxpriv->gpr =
48
+
syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
49
+
if (IS_ERR(imxpriv->gpr)) {
50
+
dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
51
+
return PTR_ERR(imxpriv->gpr);
52
+
}
53
+
54
+
ret = clk_prepare_enable(imxpriv->sata_ref_clk);
55
+
if (ret < 0) {
56
+
dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
57
+
return ret;
58
+
}
59
+
60
+
/*
61
+
* set PHY Paremeters, two steps to configure the GPR13,
62
+
* one write for rest of parameters, mask of first write
63
+
* is 0x07fffffd, and the other one write for setting
64
+
* the mpll_clk_en.
65
+
*/
66
+
regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
67
+
| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
68
+
| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
69
+
| IMX6Q_GPR13_SATA_SPD_MODE_MASK
70
+
| IMX6Q_GPR13_SATA_MPLL_SS_EN
71
+
| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
72
+
| IMX6Q_GPR13_SATA_TX_BOOST_MASK
73
+
| IMX6Q_GPR13_SATA_TX_LVL_MASK
74
+
| IMX6Q_GPR13_SATA_TX_EDGE_RATE
75
+
, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
76
+
| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
77
+
| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
78
+
| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
79
+
| IMX6Q_GPR13_SATA_MPLL_SS_EN
80
+
| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
81
+
| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
82
+
| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
83
+
regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
84
+
IMX6Q_GPR13_SATA_MPLL_CLK_EN);
85
+
usleep_range(100, 200);
86
+
87
+
/*
88
+
* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
89
+
* and IP vendor specific register HOST_TIMER1MS.
90
+
* Configure CAP_SSS (support stagered spin up).
91
+
* Implement the port0.
92
+
* Get the ahb clock rate, and configure the TIMER1MS register.
93
+
*/
94
+
reg_val = readl(mmio + HOST_CAP);
95
+
if (!(reg_val & HOST_CAP_SSS)) {
96
+
reg_val |= HOST_CAP_SSS;
97
+
writel(reg_val, mmio + HOST_CAP);
98
+
}
99
+
reg_val = readl(mmio + HOST_PORTS_IMPL);
100
+
if (!(reg_val & 0x1)) {
101
+
reg_val |= 0x1;
102
+
writel(reg_val, mmio + HOST_PORTS_IMPL);
103
+
}
104
+
105
+
reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
106
+
writel(reg_val, mmio + HOST_TIMER1MS);
107
+
108
+
return 0;
109
+
}
110
+
111
+
static void imx6q_sata_exit(struct device *dev)
112
+
{
113
+
struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
114
+
115
+
regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
116
+
!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
117
+
clk_disable_unprepare(imxpriv->sata_ref_clk);
118
+
}
119
+
120
+
static struct ahci_platform_data imx6q_sata_pdata = {
121
+
.init = imx6q_sata_init,
122
+
.exit = imx6q_sata_exit,
123
+
};
124
+
125
+
static const struct of_device_id imx_ahci_of_match[] = {
126
+
{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
127
+
{},
128
+
};
129
+
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
130
+
131
+
static int imx_ahci_probe(struct platform_device *pdev)
132
+
{
133
+
struct device *dev = &pdev->dev;
134
+
struct resource *mem, *irq, res[2];
135
+
const struct of_device_id *of_id;
136
+
const struct ahci_platform_data *pdata = NULL;
137
+
struct imx_ahci_priv *imxpriv;
138
+
struct device *ahci_dev;
139
+
struct platform_device *ahci_pdev;
140
+
int ret;
141
+
142
+
imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
143
+
if (!imxpriv) {
144
+
dev_err(dev, "can't alloc ahci_host_priv\n");
145
+
return -ENOMEM;
146
+
}
147
+
148
+
ahci_pdev = platform_device_alloc("ahci", -1);
149
+
if (!ahci_pdev)
150
+
return -ENODEV;
151
+
152
+
ahci_dev = &ahci_pdev->dev;
153
+
ahci_dev->parent = dev;
154
+
155
+
imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
156
+
if (IS_ERR(imxpriv->ahb_clk)) {
157
+
dev_err(dev, "can't get ahb clock.\n");
158
+
ret = PTR_ERR(imxpriv->ahb_clk);
159
+
goto err_out;
160
+
}
161
+
162
+
imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
163
+
if (IS_ERR(imxpriv->sata_ref_clk)) {
164
+
dev_err(dev, "can't get sata_ref clock.\n");
165
+
ret = PTR_ERR(imxpriv->sata_ref_clk);
166
+
goto err_out;
167
+
}
168
+
169
+
imxpriv->ahci_pdev = ahci_pdev;
170
+
platform_set_drvdata(pdev, imxpriv);
171
+
172
+
of_id = of_match_device(imx_ahci_of_match, dev);
173
+
if (of_id) {
174
+
pdata = of_id->data;
175
+
} else {
176
+
ret = -EINVAL;
177
+
goto err_out;
178
+
}
179
+
180
+
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
181
+
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
182
+
if (!mem || !irq) {
183
+
dev_err(dev, "no mmio/irq resource\n");
184
+
ret = -ENOMEM;
185
+
goto err_out;
186
+
}
187
+
188
+
res[0] = *mem;
189
+
res[1] = *irq;
190
+
191
+
ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
192
+
ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
193
+
ahci_dev->of_node = dev->of_node;
194
+
195
+
ret = platform_device_add_resources(ahci_pdev, res, 2);
196
+
if (ret)
197
+
goto err_out;
198
+
199
+
ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
200
+
if (ret)
201
+
goto err_out;
202
+
203
+
ret = platform_device_add(ahci_pdev);
204
+
if (ret) {
205
+
err_out:
206
+
platform_device_put(ahci_pdev);
207
+
return ret;
208
+
}
209
+
210
+
return 0;
211
+
}
212
+
213
+
static int imx_ahci_remove(struct platform_device *pdev)
214
+
{
215
+
struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
216
+
struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
217
+
218
+
platform_device_unregister(ahci_pdev);
219
+
return 0;
220
+
}
221
+
222
+
static struct platform_driver imx_ahci_driver = {
223
+
.probe = imx_ahci_probe,
224
+
.remove = imx_ahci_remove,
225
+
.driver = {
226
+
.name = "ahci-imx",
227
+
.owner = THIS_MODULE,
228
+
.of_match_table = imx_ahci_of_match,
229
+
},
230
+
};
231
+
module_platform_driver(imx_ahci_driver);
232
+
233
+
MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
234
+
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
235
+
MODULE_LICENSE("GPL");
236
+
MODULE_ALIAS("ahci:imx");
+1
-1
drivers/ata/ata_piix.c
+1
-1
drivers/ata/ata_piix.c
···
330
330
/* SATA Controller IDE (Wellsburg) */
331
331
{ 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
332
332
/* SATA Controller IDE (Wellsburg) */
333
-
{ 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
333
+
{ 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
334
334
/* SATA Controller IDE (Wellsburg) */
335
335
{ 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
336
336
/* SATA Controller IDE (Wellsburg) */
+4
-2
drivers/ata/libata-scsi.c
+4
-2
drivers/ata/libata-scsi.c
···
206
206
unsigned long flags;
207
207
int rc;
208
208
209
-
rc = strict_strtol(buf, 10, &input);
210
-
if (rc || input < -2)
209
+
rc = kstrtol(buf, 10, &input);
210
+
if (rc)
211
+
return rc;
212
+
if (input < -2)
211
213
return -EINVAL;
212
214
if (input > ATA_TMOUT_MAX_PARK) {
213
215
rc = -EOVERFLOW;
+14
drivers/ata/sata_inic162x.c
+14
drivers/ata/sata_inic162x.c
···
6
6
*
7
7
* This file is released under GPL v2.
8
8
*
9
+
* **** WARNING ****
10
+
*
11
+
* This driver never worked properly and unfortunately data corruption is
12
+
* relatively common. There isn't anyone working on the driver and there's
13
+
* no support from the vendor. Do not use this driver in any production
14
+
* environment.
15
+
*
16
+
* http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
17
+
* https://bugzilla.kernel.org/show_bug.cgi?id=60565
18
+
*
19
+
* *****************
20
+
*
9
21
* This controller is eccentric and easily locks up if something isn't
10
22
* right. Documentation is available at initio's website but it only
11
23
* documents registers (not programming model).
···
818
806
int i, rc;
819
807
820
808
ata_print_version_once(&pdev->dev, DRV_VERSION);
809
+
810
+
dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
821
811
822
812
/* alloc host */
823
813
host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
+84
-37
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+84
-37
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
···
279
279
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
280
280
#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
281
281
#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
282
-
#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
283
-
#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
284
-
#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
285
-
#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
286
-
#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
287
-
#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
288
-
#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
289
-
#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
290
-
#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
291
-
#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
292
-
#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
293
-
#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
294
-
#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
295
-
#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
296
-
#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
297
-
#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
298
-
#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
299
-
#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
300
-
#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
301
-
#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
302
-
#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
303
-
#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
304
-
#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
305
-
#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
306
-
#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
307
-
#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
308
-
#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
309
-
#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
310
-
#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
311
-
#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
312
-
#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
313
-
#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
314
-
#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
315
-
#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
316
-
#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
317
-
#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
318
-
282
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24)
283
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24)
284
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24)
285
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
286
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24)
287
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24)
288
+
#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24)
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#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24)
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#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
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#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
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#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16)
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#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16)
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#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16)
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#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16)
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#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16)
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#define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15)
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#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0
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#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15)
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#define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11)
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#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11)
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#define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7)
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#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7)
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#define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2)
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#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2)
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#define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
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#define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
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#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */