Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'linux-watchdog-6.5-rc1' of git://www.linux-watchdog.org/linux-watchdog
Pull watchdog updates from Wim Van Sebroeck:
- add Xilinx Versal watchdog
- support Hygon FCH/SCH (Server Controller Hub)
- convert GPL notices to SPDX identifiers
- other improvements
* tag 'linux-watchdog-6.5-rc1' of git://www.linux-watchdog.org/linux-watchdog:
watchdog: sp5100_tco: support Hygon FCH/SCH (Server Controller Hub)
dt-bindings: watchdog: restrict node name suffixes
MAINTAINERS: Add support for Xilinx versal watchdog
watchdog: xilinx_wwdt: Add Versal window watchdog support
dt-bindings: watchdog: xlnx,versal-wwdt: Add versal watchdog
watchdog: ziirave_wdt: Switch i2c driver back to use .probe()
watchdog: ibmasr: Replace GPL license notice with SPDX identifier
watchdog: Convert GPL 2.0 notice to SPDX identifier
watchdog: loongson1_wdt: Add DT support
+299
-36
+50
Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml
+50
Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Xilinx Versal window watchdog timer controller
8
+
9
+
maintainers:
10
+
- Neeli Srinivas <srinivas.neeli@amd.com>
11
+
12
+
description:
13
+
Versal watchdog intellectual property uses window watchdog mode.
14
+
Window watchdog timer(WWDT) contains closed(first) and open(second)
15
+
window with 32 bit width. Write to the watchdog timer within
16
+
predefined window periods of time. This means a period that is not
17
+
too soon and a period that is not too late. The WWDT has to be
18
+
restarted within the open window time. If software tries to restart
19
+
WWDT outside of the open window time period, it generates a reset.
20
+
21
+
allOf:
22
+
- $ref: watchdog.yaml#
23
+
24
+
properties:
25
+
compatible:
26
+
enum:
27
+
- xlnx,versal-wwdt
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
clocks:
33
+
maxItems: 1
34
+
35
+
required:
36
+
- compatible
37
+
- reg
38
+
- clocks
39
+
40
+
unevaluatedProperties: false
41
+
42
+
examples:
43
+
- |
44
+
watchdog@fd4d0000 {
45
+
compatible = "xlnx,versal-wwdt";
46
+
reg = <0xfd4d0000 0x10000>;
47
+
clocks = <&clock25>;
48
+
timeout-sec = <30>;
49
+
};
50
+
...
+2
MAINTAINERS
+2
MAINTAINERS
···
23460
23460
R: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
23461
23461
R: Michal Simek <michal.simek@amd.com>
23462
23462
S: Maintained
23463
+
F: Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml
23463
23464
F: Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
23464
23465
F: drivers/watchdog/of_xilinx_wdt.c
23466
+
F: drivers/watchdog/xilinx_wwdt.c
23465
23467
23466
23468
XILINX XDMA DRIVER
23467
23469
M: Lizhi Hou <lizhi.hou@amd.com>
+18
drivers/watchdog/Kconfig
+18
drivers/watchdog/Kconfig
···
304
304
To compile this driver as a module, choose M here: the
305
305
module will be called of_xilinx_wdt.
306
306
307
+
config XILINX_WINDOW_WATCHDOG
308
+
tristate "Xilinx window watchdog timer"
309
+
depends on HAS_IOMEM
310
+
depends on ARM64
311
+
select WATCHDOG_CORE
312
+
help
313
+
Window watchdog driver for the versal_wwdt IP core.
314
+
Window watchdog timer(WWDT) contains closed(first) and
315
+
open(second) window with 32 bit width. Write to the watchdog
316
+
timer within predefined window periods of time. This means
317
+
a period that is not too soon and a period that is not too
318
+
late. The WWDT has to be restarted within the open window time.
319
+
If software tries to restart WWDT outside of the open window
320
+
time period, it generates a reset.
321
+
322
+
To compile this driver as a module, choose M here: the
323
+
module will be called xilinx_wwdt.
324
+
307
325
config ZIIRAVE_WATCHDOG
308
326
tristate "Zodiac RAVE Watchdog Timer"
309
327
depends on I2C
+1
drivers/watchdog/Makefile
+1
drivers/watchdog/Makefile
+1
-4
drivers/watchdog/ep93xx_wdt.c
+1
-4
drivers/watchdog/ep93xx_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* Watchdog driver for Cirrus Logic EP93xx family of devices.
3
4
*
···
11
10
*
12
11
* Copyright (c) 2012 H Hartley Sweeten <hsweeten@visionengravers.com>
13
12
* Convert to a platform device and use the watchdog framework API
14
-
*
15
-
* This file is licensed under the terms of the GNU General Public
16
-
* License version 2. This program is licensed "as is" without any
17
-
* warranty of any kind, whether express or implied.
18
13
*
19
14
* This watchdog fires after 250msec, which is a too short interval
20
15
* for us to rely on the user space daemon alone. So we ping the
+1
-2
drivers/watchdog/ibmasr.c
+1
-2
drivers/watchdog/ibmasr.c
···
1
+
// SPDX-License-Identifier: GPL-1.0+
1
2
/*
2
3
* IBM Automatic Server Restart driver.
3
4
*
···
7
6
* Based on driver written by Pete Reynolds.
8
7
* Copyright (c) IBM Corporation, 1998-2004.
9
8
*
10
-
* This software may be used and distributed according to the terms
11
-
* of the GNU Public License, incorporated herein by reference.
12
9
*/
13
10
14
11
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+12
-1
drivers/watchdog/loongson1_wdt.c
+12
-1
drivers/watchdog/loongson1_wdt.c
···
5
5
6
6
#include <linux/clk.h>
7
7
#include <linux/module.h>
8
+
#include <linux/of.h>
8
9
#include <linux/platform_device.h>
9
10
#include <linux/watchdog.h>
10
11
···
113
112
if (IS_ERR(drvdata->base))
114
113
return PTR_ERR(drvdata->base);
115
114
116
-
drvdata->clk = devm_clk_get_enabled(dev, pdev->name);
115
+
drvdata->clk = devm_clk_get_enabled(dev, NULL);
117
116
if (IS_ERR(drvdata->clk))
118
117
return PTR_ERR(drvdata->clk);
119
118
···
145
144
return 0;
146
145
}
147
146
147
+
#ifdef CONFIG_OF
148
+
static const struct of_device_id ls1x_wdt_dt_ids[] = {
149
+
{ .compatible = "loongson,ls1b-wdt", },
150
+
{ .compatible = "loongson,ls1c-wdt", },
151
+
{ /* sentinel */ }
152
+
};
153
+
MODULE_DEVICE_TABLE(of, ls1x_wdt_dt_ids);
154
+
#endif
155
+
148
156
static struct platform_driver ls1x_wdt_driver = {
149
157
.probe = ls1x_wdt_probe,
150
158
.driver = {
151
159
.name = "ls1x-wdt",
160
+
.of_match_table = of_match_ptr(ls1x_wdt_dt_ids),
152
161
},
153
162
};
154
163
+1
-3
drivers/watchdog/m54xx_wdt.c
+1
-3
drivers/watchdog/m54xx_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* drivers/watchdog/m54xx_wdt.c
3
4
*
···
12
11
* Copyright 2004 (c) MontaVista, Software, Inc.
13
12
* Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
14
13
*
15
-
* This file is licensed under the terms of the GNU General Public
16
-
* License version 2. This program is licensed "as is" without any
17
-
* warranty of any kind, whether express or implied.
18
14
*/
19
15
20
16
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+1
-4
drivers/watchdog/max63xx_wdt.c
+1
-4
drivers/watchdog/max63xx_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* drivers/char/watchdog/max63xx_wdt.c
3
4
*
4
5
* Driver for max63{69,70,71,72,73,74} watchdog timers
5
6
*
6
7
* Copyright (C) 2009 Marc Zyngier <maz@misterjones.org>
7
-
*
8
-
* This file is licensed under the terms of the GNU General Public
9
-
* License version 2. This program is licensed "as is" without any
10
-
* warranty of any kind, whether express or implied.
11
8
*
12
9
* This driver assumes the watchdog pins are memory mapped (as it is
13
10
* the case for the Arcom Zeus). Should it be connected over GPIOs or
+1
-3
drivers/watchdog/moxart_wdt.c
+1
-3
drivers/watchdog/moxart_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* MOXA ART SoCs watchdog driver.
3
4
*
···
6
5
*
7
6
* Jonas Jensen <jonas.jensen@gmail.com>
8
7
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
8
*/
13
9
14
10
#include <linux/clk.h>
+1
-4
drivers/watchdog/octeon-wdt-nmi.S
+1
-4
drivers/watchdog/octeon-wdt-nmi.S
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
1
2
/*
2
-
* This file is subject to the terms and conditions of the GNU General Public
3
-
* License. See the file "COPYING" in the main directory of this archive
4
-
* for more details.
5
-
*
6
3
* Copyright (C) 2007-2017 Cavium, Inc.
7
4
*/
8
5
#include <asm/asm.h>
+1
-3
drivers/watchdog/orion_wdt.c
+1
-3
drivers/watchdog/orion_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* drivers/watchdog/orion_wdt.c
3
4
*
···
6
5
*
7
6
* Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
8
7
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
8
*/
13
9
14
10
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+1
-1
drivers/watchdog/rtd119x_wdt.c
+1
-1
drivers/watchdog/rtd119x_wdt.c
+1
-3
drivers/watchdog/sbc_fitpc2_wdt.c
+1
-3
drivers/watchdog/sbc_fitpc2_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* Watchdog driver for SBC-FITPC2 board
3
4
*
···
6
5
*
7
6
* Adapted from the IXP2000 watchdog driver by Deepak Saxena.
8
7
*
9
-
* This file is licensed under the terms of the GNU General Public
10
-
* License version 2. This program is licensed "as is" without any
11
-
* warranty of any kind, whether express or implied.
12
8
*/
13
9
14
10
#define pr_fmt(fmt) KBUILD_MODNAME " WATCHDOG: " fmt
+3
-1
drivers/watchdog/sp5100_tco.c
+3
-1
drivers/watchdog/sp5100_tco.c
···
96
96
sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
97
97
sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
98
98
return efch_mmio;
99
-
} else if (dev->vendor == PCI_VENDOR_ID_AMD &&
99
+
} else if ((dev->vendor == PCI_VENDOR_ID_AMD || dev->vendor == PCI_VENDOR_ID_HYGON) &&
100
100
((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
101
101
dev->revision >= 0x41) ||
102
102
(dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
···
578
578
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
579
579
PCI_ANY_ID, },
580
580
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
581
+
PCI_ANY_ID, },
582
+
{ PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
581
583
PCI_ANY_ID, },
582
584
{ 0, }, /* End of list */
583
585
};
+1
-3
drivers/watchdog/ts4800_wdt.c
+1
-3
drivers/watchdog/ts4800_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* Watchdog driver for TS-4800 based boards
3
4
*
4
5
* Copyright (c) 2015 - Savoir-faire Linux
5
6
*
6
-
* This file is licensed under the terms of the GNU General Public
7
-
* License version 2. This program is licensed "as is" without any
8
-
* warranty of any kind, whether express or implied.
9
7
*/
10
8
11
9
#include <linux/kernel.h>
+1
-3
drivers/watchdog/ts72xx_wdt.c
+1
-3
drivers/watchdog/ts72xx_wdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
1
2
/*
2
3
* Watchdog driver for Technologic Systems TS-72xx based SBCs
3
4
* (TS-7200, TS-7250 and TS-7260). These boards have external
···
9
8
*
10
9
* This driver is based on ep93xx_wdt and wm831x_wdt drivers.
11
10
*
12
-
* This file is licensed under the terms of the GNU General Public
13
-
* License version 2. This program is licensed "as is" without any
14
-
* warranty of any kind, whether express or implied.
15
11
*/
16
12
17
13
#include <linux/platform_device.h>
+201
drivers/watchdog/xilinx_wwdt.c
+201
drivers/watchdog/xilinx_wwdt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Window watchdog device driver for Xilinx Versal WWDT
4
+
*
5
+
* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
6
+
*/
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/interrupt.h>
10
+
#include <linux/io.h>
11
+
#include <linux/ioport.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/of_address.h>
15
+
#include <linux/watchdog.h>
16
+
17
+
/* Max timeout is calculated at 100MHz source clock */
18
+
#define XWWDT_DEFAULT_TIMEOUT 42
19
+
#define XWWDT_MIN_TIMEOUT 1
20
+
21
+
/* Register offsets for the WWDT device */
22
+
#define XWWDT_MWR_OFFSET 0x00
23
+
#define XWWDT_ESR_OFFSET 0x04
24
+
#define XWWDT_FCR_OFFSET 0x08
25
+
#define XWWDT_FWR_OFFSET 0x0c
26
+
#define XWWDT_SWR_OFFSET 0x10
27
+
28
+
/* Master Write Control Register Masks */
29
+
#define XWWDT_MWR_MASK BIT(0)
30
+
31
+
/* Enable and Status Register Masks */
32
+
#define XWWDT_ESR_WINT_MASK BIT(16)
33
+
#define XWWDT_ESR_WSW_MASK BIT(8)
34
+
#define XWWDT_ESR_WEN_MASK BIT(0)
35
+
36
+
#define XWWDT_CLOSE_WINDOW_PERCENT 50
37
+
38
+
static int wwdt_timeout;
39
+
static int closed_window_percent;
40
+
41
+
module_param(wwdt_timeout, int, 0);
42
+
MODULE_PARM_DESC(wwdt_timeout,
43
+
"Watchdog time in seconds. (default="
44
+
__MODULE_STRING(XWWDT_DEFAULT_TIMEOUT) ")");
45
+
module_param(closed_window_percent, int, 0);
46
+
MODULE_PARM_DESC(closed_window_percent,
47
+
"Watchdog closed window percentage. (default="
48
+
__MODULE_STRING(XWWDT_CLOSE_WINDOW_PERCENT) ")");
49
+
/**
50
+
* struct xwwdt_device - Watchdog device structure
51
+
* @base: base io address of WDT device
52
+
* @spinlock: spinlock for IO register access
53
+
* @xilinx_wwdt_wdd: watchdog device structure
54
+
* @freq: source clock frequency of WWDT
55
+
* @close_percent: Closed window percent
56
+
*/
57
+
struct xwwdt_device {
58
+
void __iomem *base;
59
+
spinlock_t spinlock; /* spinlock for register handling */
60
+
struct watchdog_device xilinx_wwdt_wdd;
61
+
unsigned long freq;
62
+
u32 close_percent;
63
+
};
64
+
65
+
static int xilinx_wwdt_start(struct watchdog_device *wdd)
66
+
{
67
+
struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
68
+
struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
69
+
u64 time_out, closed_timeout, open_timeout;
70
+
u32 control_status_reg;
71
+
72
+
/* Calculate timeout count */
73
+
time_out = xdev->freq * wdd->timeout;
74
+
closed_timeout = (time_out * xdev->close_percent) / 100;
75
+
open_timeout = time_out - closed_timeout;
76
+
wdd->min_hw_heartbeat_ms = xdev->close_percent * 10 * wdd->timeout;
77
+
78
+
spin_lock(&xdev->spinlock);
79
+
80
+
iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
81
+
iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET);
82
+
iowrite32((u32)closed_timeout, xdev->base + XWWDT_FWR_OFFSET);
83
+
iowrite32((u32)open_timeout, xdev->base + XWWDT_SWR_OFFSET);
84
+
85
+
/* Enable the window watchdog timer */
86
+
control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
87
+
control_status_reg |= XWWDT_ESR_WEN_MASK;
88
+
iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
89
+
90
+
spin_unlock(&xdev->spinlock);
91
+
92
+
dev_dbg(xilinx_wwdt_wdd->parent, "Watchdog Started!\n");
93
+
94
+
return 0;
95
+
}
96
+
97
+
static int xilinx_wwdt_keepalive(struct watchdog_device *wdd)
98
+
{
99
+
struct xwwdt_device *xdev = watchdog_get_drvdata(wdd);
100
+
u32 control_status_reg;
101
+
102
+
spin_lock(&xdev->spinlock);
103
+
104
+
/* Enable write access control bit for the window watchdog */
105
+
iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET);
106
+
107
+
/* Trigger restart kick to watchdog */
108
+
control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET);
109
+
control_status_reg |= XWWDT_ESR_WSW_MASK;
110
+
iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET);
111
+
112
+
spin_unlock(&xdev->spinlock);
113
+
114
+
return 0;
115
+
}
116
+
117
+
static const struct watchdog_info xilinx_wwdt_ident = {
118
+
.options = WDIOF_KEEPALIVEPING |
119
+
WDIOF_SETTIMEOUT,
120
+
.firmware_version = 1,
121
+
.identity = "xlnx_window watchdog",
122
+
};
123
+
124
+
static const struct watchdog_ops xilinx_wwdt_ops = {
125
+
.owner = THIS_MODULE,
126
+
.start = xilinx_wwdt_start,
127
+
.ping = xilinx_wwdt_keepalive,
128
+
};
129
+
130
+
static int xwwdt_probe(struct platform_device *pdev)
131
+
{
132
+
struct watchdog_device *xilinx_wwdt_wdd;
133
+
struct device *dev = &pdev->dev;
134
+
struct xwwdt_device *xdev;
135
+
struct clk *clk;
136
+
int ret;
137
+
138
+
xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
139
+
if (!xdev)
140
+
return -ENOMEM;
141
+
142
+
xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd;
143
+
xilinx_wwdt_wdd->info = &xilinx_wwdt_ident;
144
+
xilinx_wwdt_wdd->ops = &xilinx_wwdt_ops;
145
+
xilinx_wwdt_wdd->parent = dev;
146
+
147
+
xdev->base = devm_platform_ioremap_resource(pdev, 0);
148
+
if (IS_ERR(xdev->base))
149
+
return PTR_ERR(xdev->base);
150
+
151
+
clk = devm_clk_get_enabled(dev, NULL);
152
+
if (IS_ERR(clk))
153
+
return PTR_ERR(clk);
154
+
155
+
xdev->freq = clk_get_rate(clk);
156
+
if (!xdev->freq)
157
+
return -EINVAL;
158
+
159
+
xilinx_wwdt_wdd->min_timeout = XWWDT_MIN_TIMEOUT;
160
+
xilinx_wwdt_wdd->timeout = XWWDT_DEFAULT_TIMEOUT;
161
+
xilinx_wwdt_wdd->max_hw_heartbeat_ms = 1000 * xilinx_wwdt_wdd->timeout;
162
+
163
+
if (closed_window_percent == 0 || closed_window_percent >= 100)
164
+
xdev->close_percent = XWWDT_CLOSE_WINDOW_PERCENT;
165
+
else
166
+
xdev->close_percent = closed_window_percent;
167
+
168
+
watchdog_init_timeout(xilinx_wwdt_wdd, wwdt_timeout, &pdev->dev);
169
+
spin_lock_init(&xdev->spinlock);
170
+
watchdog_set_drvdata(xilinx_wwdt_wdd, xdev);
171
+
watchdog_set_nowayout(xilinx_wwdt_wdd, 1);
172
+
173
+
ret = devm_watchdog_register_device(dev, xilinx_wwdt_wdd);
174
+
if (ret)
175
+
return ret;
176
+
177
+
dev_info(dev, "Xilinx window watchdog Timer with timeout %ds\n",
178
+
xilinx_wwdt_wdd->timeout);
179
+
180
+
return 0;
181
+
}
182
+
183
+
static const struct of_device_id xwwdt_of_match[] = {
184
+
{ .compatible = "xlnx,versal-wwdt", },
185
+
{},
186
+
};
187
+
MODULE_DEVICE_TABLE(of, xwwdt_of_match);
188
+
189
+
static struct platform_driver xwwdt_driver = {
190
+
.probe = xwwdt_probe,
191
+
.driver = {
192
+
.name = "Xilinx window watchdog",
193
+
.of_match_table = xwwdt_of_match,
194
+
},
195
+
};
196
+
197
+
module_platform_driver(xwwdt_driver);
198
+
199
+
MODULE_AUTHOR("Neeli Srinivas <srinivas.neeli@amd.com>");
200
+
MODULE_DESCRIPTION("Xilinx window watchdog driver");
201
+
MODULE_LICENSE("GPL");