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spi: rzv2h-rspi: Simplify clock rate search function signatures

The spr_min and spr_max parameters passed to
rzv2h_rspi_find_rate_variable() and rzv2h_rspi_find_rate_fixed() were
always called with RSPI_SPBR_SPR_MIN and RSPI_SPBR_SPR_MAX respectively.
There is no need to pass these as parameters since the valid SPR range
is fixed by the hardware.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20260410080517.2405700-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Lad Prabhakar and committed by
Mark Brown c958bb67 0335767d

+11 -15
+11 -15
drivers/spi/spi-rzv2h-rspi.c
··· 88 88 }; 89 89 90 90 struct rzv2h_rspi_info { 91 - void (*find_tclk_rate)(struct clk *clk, u32 hz, u8 spr_min, u8 spr_max, 91 + void (*find_tclk_rate)(struct clk *clk, u32 hz, 92 92 struct rzv2h_rspi_best_clock *best_clk); 93 - void (*find_pclk_rate)(struct clk *clk, u32 hz, u8 spr_low, u8 spr_high, 93 + void (*find_pclk_rate)(struct clk *clk, u32 hz, 94 94 struct rzv2h_rspi_best_clock *best_clk); 95 95 const char *tclk_name; 96 96 unsigned int fifo_size; ··· 413 413 } 414 414 415 415 static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz, 416 - u8 spr_min, u8 spr_max, 417 416 struct rzv2h_rspi_best_clock *best) 418 417 { 419 418 long clk_rate, clk_min_rate, clk_max_rate; ··· 463 464 * minimum SPR that is in the valid range. 464 465 */ 465 466 min_rate_spr = DIV_ROUND_CLOSEST(clk_min_rate, rate_div) - 1; 466 - if (min_rate_spr > spr_max) 467 + if (min_rate_spr > RSPI_SPBR_SPR_MAX) 467 468 continue; 468 469 469 470 /* ··· 473 474 * maximum SPR that is in the valid range. 474 475 */ 475 476 max_rate_spr = DIV_ROUND_CLOSEST(clk_max_rate, rate_div) - 1; 476 - if (max_rate_spr < spr_min) 477 + if (max_rate_spr < RSPI_SPBR_SPR_MIN) 477 478 break; 478 479 479 - if (min_rate_spr < spr_min) 480 - min_rate_spr = spr_min; 480 + if (min_rate_spr < RSPI_SPBR_SPR_MIN) 481 + min_rate_spr = RSPI_SPBR_SPR_MIN; 481 482 482 - if (max_rate_spr > spr_max) 483 - max_rate_spr = spr_max; 483 + if (max_rate_spr > RSPI_SPBR_SPR_MAX) 484 + max_rate_spr = RSPI_SPBR_SPR_MAX; 484 485 485 486 for (spr = min_rate_spr; spr <= max_rate_spr; spr++) { 486 487 clk_rate = (spr + 1) * rate_div; ··· 511 512 } 512 513 513 514 static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz, 514 - u8 spr_min, u8 spr_max, 515 515 struct rzv2h_rspi_best_clock *best) 516 516 { 517 517 unsigned long clk_rate; ··· 543 545 */ 544 546 if (!spr && !brdv) 545 547 continue; 546 - if (spr >= spr_min && spr <= spr_max) 548 + if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX) 547 549 goto clock_found; 548 550 } 549 551 ··· 573 575 }; 574 576 int ret; 575 577 576 - rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN, 577 - RSPI_SPBR_SPR_MAX, &best_clock); 578 + rspi->info->find_tclk_rate(rspi->tclk, hz, &best_clock); 578 579 579 580 if (best_clock.error && rspi->info->find_pclk_rate) 580 - rspi->info->find_pclk_rate(rspi->pclk, hz, RSPI_SPBR_SPR_MIN, 581 - RSPI_SPBR_SPR_MAX, &best_clock); 581 + rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock); 582 582 583 583 if (!best_clock.clk_rate) 584 584 return -EINVAL;