Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- Incorrect VIPT aliasing assumption
- Misc build warning fixes and some typos
* tag 'arc-6.9-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: [plat-hsdk]: Remove misplaced interrupt-cells property
ARC: Fix typos
ARC: mm: fix new code about cache aliasing
ARC: Fix -Wmissing-prototypes warnings
+50
-59
-1
arch/arc/Kconfig
-1
arch/arc/Kconfig
+2
-2
arch/arc/boot/Makefile
+2
-2
arch/arc/boot/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
3
-
# uImage build relies on mkimage being availble on your host for ARC target
3
+
# uImage build relies on mkimage being available on your host for ARC target
4
4
# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
5
-
# and make sure it's reacable from your PATH
5
+
# and make sure it's reachable from your PATH
6
6
7
7
OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S
8
8
+2
-2
arch/arc/boot/dts/axc003.dtsi
+2
-2
arch/arc/boot/dts/axc003.dtsi
···
119
119
/*
120
120
* The DW APB ICTL intc on MB is connected to CPU intc via a
121
121
* DT "invisible" DW APB GPIO block, configured to simply pass thru
122
-
* interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
122
+
* interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
123
123
*
124
-
* So here we mimic a direct connection betwen them, ignoring the
124
+
* So here we mimic a direct connection between them, ignoring the
125
125
* ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
126
126
* instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
127
127
*
-1
arch/arc/boot/dts/hsdk.dts
-1
arch/arc/boot/dts/hsdk.dts
+1
-1
arch/arc/boot/dts/vdk_axs10x_mb.dtsi
+1
-1
arch/arc/boot/dts/vdk_axs10x_mb.dtsi
···
113
113
/*
114
114
* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
115
115
*
116
-
* This node is intentionally put outside of MB above becase
116
+
* This node is intentionally put outside of MB above because
117
117
* it maps areas outside of MB's 0xez-0xfz.
118
118
*/
119
119
uio_ev: uio@d0000000 {
-9
arch/arc/include/asm/cachetype.h
-9
arch/arc/include/asm/cachetype.h
+1
-1
arch/arc/include/asm/dsp.h
+1
-1
arch/arc/include/asm/dsp.h
···
12
12
/*
13
13
* DSP-related saved registers - need to be saved only when you are
14
14
* scheduled out.
15
-
* structure fields name must correspond to aux register defenitions for
15
+
* structure fields name must correspond to aux register definitions for
16
16
* automatic offset calculation in DSP_AUX_SAVE_RESTORE macros
17
17
*/
18
18
struct dsp_callee_regs {
+5
-5
arch/arc/include/asm/entry-compact.h
+5
-5
arch/arc/include/asm/entry-compact.h
···
7
7
* Stack switching code can no longer reliably rely on the fact that
8
8
* if we are NOT in user mode, stack is switched to kernel mode.
9
9
* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
10
-
* it's prologue including stack switching from user mode
10
+
* its prologue including stack switching from user mode
11
11
*
12
12
* Vineetg: Aug 28th 2008: Bug #94984
13
13
* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
···
143
143
* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
144
144
* 3. But before it could switch SP from USER to KERNEL stack
145
145
* a L2 IRQ "Interrupts" L1
146
-
* Thay way although L2 IRQ happened in Kernel mode, stack is still
146
+
* That way although L2 IRQ happened in Kernel mode, stack is still
147
147
* not switched.
148
148
* To handle this, we may need to switch stack even if in kernel mode
149
149
* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
···
173
173
174
174
GET_CURR_TASK_ON_CPU r9
175
175
176
-
/* With current tsk in r9, get it's kernel mode stack base */
176
+
/* With current tsk in r9, get its kernel mode stack base */
177
177
GET_TSK_STACK_BASE r9, r9
178
178
179
179
/* save U mode SP @ pt_regs->sp */
···
282
282
* NOTE:
283
283
*
284
284
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
285
-
* for memory load operations. If used in that way interrupts are deffered
285
+
* for memory load operations. If used in that way interrupts are deferred
286
286
* by hardware and that is not good.
287
287
*-------------------------------------------------------------*/
288
288
.macro EXCEPTION_EPILOGUE
···
350
350
* NOTE:
351
351
*
352
352
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
353
-
* for memory load operations. If used in that way interrupts are deffered
353
+
* for memory load operations. If used in that way interrupts are deferred
354
354
* by hardware and that is not good.
355
355
*-------------------------------------------------------------*/
356
356
.macro INTERRUPT_EPILOGUE LVL
+2
-2
arch/arc/include/asm/entry.h
+2
-2
arch/arc/include/asm/entry.h
···
7
7
#ifndef __ASM_ARC_ENTRY_H
8
8
#define __ASM_ARC_ENTRY_H
9
9
10
-
#include <asm/unistd.h> /* For NR_syscalls defination */
10
+
#include <asm/unistd.h> /* For NR_syscalls definition */
11
11
#include <asm/arcregs.h>
12
12
#include <asm/ptrace.h>
13
13
#include <asm/processor.h> /* For VMALLOC_START */
···
56
56
.endm
57
57
58
58
/*-------------------------------------------------------------
59
-
* given a tsk struct, get to the base of it's kernel mode stack
59
+
* given a tsk struct, get to the base of its kernel mode stack
60
60
* tsk->thread_info is really a PAGE, whose bottom hoists stack
61
61
* which grows upwards towards thread_info
62
62
*------------------------------------------------------------*/
+1
-1
arch/arc/include/asm/irq.h
+1
-1
arch/arc/include/asm/irq.h
···
10
10
* ARCv2 can support 240 interrupts in the core interrupts controllers and
11
11
* 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
12
12
* configurations of boards.
13
-
* This doesnt affect ARCompact, but we change it to same value
13
+
* This doesn't affect ARCompact, but we change it to same value
14
14
*/
15
15
#define NR_IRQS 512
16
16
+1
-1
arch/arc/include/asm/irqflags-compact.h
+1
-1
arch/arc/include/asm/irqflags-compact.h
···
46
46
* IRQ Control Macros
47
47
*
48
48
* All of them have "memory" clobber (compiler barrier) which is needed to
49
-
* ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
49
+
* ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
50
50
* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
51
51
*
52
52
* Noted at the time of Abilis Timer List corruption
+1
-1
arch/arc/include/asm/mmu_context.h
+1
-1
arch/arc/include/asm/mmu_context.h
···
165
165
* for retiring-mm. However destroy_context( ) still needs to do that because
166
166
* between mm_release( ) = >deactive_mm( ) and
167
167
* mmput => .. => __mmdrop( ) => destroy_context( )
168
-
* there is a good chance that task gets sched-out/in, making it's ASID valid
168
+
* there is a good chance that task gets sched-out/in, making its ASID valid
169
169
* again (this teased me for a whole day).
170
170
*/
171
171
+1
-1
arch/arc/include/asm/pgtable-bits-arcv2.h
+1
-1
arch/arc/include/asm/pgtable-bits-arcv2.h
···
66
66
* Other rules which cause the divergence from 1:1 mapping
67
67
*
68
68
* 1. Although ARC700 can do exclusive execute/write protection (meaning R
69
-
* can be tracked independet of X/W unlike some other CPUs), still to
69
+
* can be tracked independently of X/W unlike some other CPUs), still to
70
70
* keep things consistent with other archs:
71
71
* -Write implies Read: W => R
72
72
* -Execute implies Read: X => R
+1
-1
arch/arc/include/asm/ptrace.h
+1
-1
arch/arc/include/asm/ptrace.h
+1
-1
arch/arc/include/asm/shmparam.h
+1
-1
arch/arc/include/asm/shmparam.h
+2
-2
arch/arc/include/asm/smp.h
+2
-2
arch/arc/include/asm/smp.h
···
77
77
78
78
/*
79
79
* ARC700 doesn't support atomic Read-Modify-Write ops.
80
-
* Originally Interrupts had to be disabled around code to gaurantee atomicity.
80
+
* Originally Interrupts had to be disabled around code to guarantee atomicity.
81
81
* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
82
82
* based on retry-if-irq-in-atomic (with hardware assist).
83
83
* However despite these, we provide the IRQ disabling variant
···
86
86
* support needed.
87
87
*
88
88
* (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
89
-
* gaurantted by the platform (not something which core handles).
89
+
* guaranteed by the platform (not something which core handles).
90
90
* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
91
91
* disabling for atomicity.
92
92
*
+1
-1
arch/arc/include/asm/thread_info.h
+1
-1
arch/arc/include/asm/thread_info.h
···
38
38
struct thread_info {
39
39
unsigned long flags; /* low level flags */
40
40
unsigned long ksp; /* kernel mode stack top in __switch_to */
41
-
int preempt_count; /* 0 => preemptable, <0 => BUG */
41
+
int preempt_count; /* 0 => preemptible, <0 => BUG */
42
42
int cpu; /* current CPU */
43
43
unsigned long thr_ptr; /* TLS ptr */
44
44
struct task_struct *task; /* main task structure */
+1
-1
arch/arc/include/uapi/asm/swab.h
+1
-1
arch/arc/include/uapi/asm/swab.h
···
62
62
* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
63
63
*
64
64
* Joern suggested a better "C" algorithm which is great since
65
-
* (1) It is portable to any architecure
65
+
* (1) It is portable to any architecture
66
66
* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
67
67
*/
68
68
+4
-4
arch/arc/kernel/entry-arcv2.S
+4
-4
arch/arc/kernel/entry-arcv2.S
···
5
5
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
6
6
*/
7
7
8
-
#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
8
+
#include <linux/linkage.h> /* ARC_{ENTRY,EXIT} */
9
9
#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
10
10
#include <asm/errno.h>
11
11
#include <asm/arcregs.h>
···
31
31
VECTOR mem_service ; Mem exception
32
32
VECTOR instr_service ; Instrn Error
33
33
VECTOR EV_MachineCheck ; Fatal Machine check
34
-
VECTOR EV_TLBMissI ; Intruction TLB miss
34
+
VECTOR EV_TLBMissI ; Instruction TLB miss
35
35
VECTOR EV_TLBMissD ; Data TLB miss
36
36
VECTOR EV_TLBProtV ; Protection Violation
37
37
VECTOR EV_PrivilegeV ; Privilege Violation
···
76
76
# query in hard ISR path would return false (since .IE is set) which would
77
77
# trips genirq interrupt handling asserts.
78
78
#
79
-
# So do a "soft" disable of interrutps here.
79
+
# So do a "soft" disable of interrupts here.
80
80
#
81
81
# Note this disable is only for consistent book-keeping as further interrupts
82
82
# will be disabled anyways even w/o this. Hardware tracks active interrupts
83
-
# seperately in AUX_IRQ_ACT.active and will not take new interrupts
83
+
# separately in AUX_IRQ_ACT.active and will not take new interrupts
84
84
# unless this one returns (or higher prio becomes pending in 2-prio scheme)
85
85
86
86
IRQ_DISABLE
+2
-2
arch/arc/kernel/entry.S
+2
-2
arch/arc/kernel/entry.S
···
95
95
lr r0, [efa]
96
96
mov r1, sp
97
97
98
-
; MC excpetions disable MMU
98
+
; MC exceptions disable MMU
99
99
ARC_MMU_REENABLE r3
100
100
101
101
lsr r3, r10, 8
···
209
209
210
210
; ---------------------------------------------
211
211
; syscall TRAP
212
-
; ABI: (r0-r7) upto 8 args, (r8) syscall number
212
+
; ABI: (r0-r7) up to 8 args, (r8) syscall number
213
213
; ---------------------------------------------
214
214
215
215
ENTRY(EV_Trap)
+1
-1
arch/arc/kernel/head.S
+1
-1
arch/arc/kernel/head.S
+1
-1
arch/arc/kernel/intc-arcv2.c
+1
-1
arch/arc/kernel/intc-arcv2.c
···
56
56
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
57
57
58
58
/*
59
-
* ARCv2 core intc provides multiple interrupt priorities (upto 16).
59
+
* ARCv2 core intc provides multiple interrupt priorities (up to 16).
60
60
* Typical builds though have only two levels (0-high, 1-low)
61
61
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
62
62
* NMI style interrupts in future (say perf)
+4
-3
arch/arc/kernel/kprobes.c
+4
-3
arch/arc/kernel/kprobes.c
···
190
190
}
191
191
}
192
192
193
-
int __kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
193
+
static int
194
+
__kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
194
195
{
195
196
struct kprobe *p;
196
197
struct kprobe_ctlblk *kcb;
···
242
241
return 0;
243
242
}
244
243
245
-
static int __kprobes arc_post_kprobe_handler(unsigned long addr,
246
-
struct pt_regs *regs)
244
+
static int
245
+
__kprobes arc_post_kprobe_handler(unsigned long addr, struct pt_regs *regs)
247
246
{
248
247
struct kprobe *cur = kprobe_running();
249
248
struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+1
-1
arch/arc/kernel/perf_event.c
+1
-1
arch/arc/kernel/perf_event.c
···
38
38
* (based on a specific RTL build)
39
39
* Below is the static map between perf generic/arc specific event_id and
40
40
* h/w condition names.
41
-
* At the time of probe, we loop thru each index and find it's name to
41
+
* At the time of probe, we loop thru each index and find its name to
42
42
* complete the mapping of perf event_id to h/w index as latter is needed
43
43
* to program the counter really
44
44
*/
+1
-1
arch/arc/kernel/setup.c
+1
-1
arch/arc/kernel/setup.c
···
390
390
#ifdef CONFIG_ARC_HAS_DCCM
391
391
/*
392
392
* DCCM can be arbit placed in hardware.
393
-
* Make sure it's placement/sz matches what Linux is built with
393
+
* Make sure its placement/sz matches what Linux is built with
394
394
*/
395
395
if ((unsigned int)__arc_dccm_base != info->dccm.base)
396
396
panic("Linux built with incorrect DCCM Base address\n");
+4
-3
arch/arc/kernel/signal.c
+4
-3
arch/arc/kernel/signal.c
···
8
8
*
9
9
* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
10
10
* -do_signal() supports TIF_RESTORE_SIGMASK
11
-
* -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
12
-
* -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
11
+
* -do_signal() no longer needs oldset, required by OLD sys_sigsuspend
12
+
* -sys_rt_sigsuspend() now comes from generic code, so discard arch
13
+
* implementation
13
14
* -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
14
15
* -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
15
16
* the job to do_signal()
16
17
*
17
18
* vineetg: July 2009
18
19
* -Modified Code to support the uClibc provided userland sigreturn stub
19
-
* to avoid kernel synthesing it on user stack at runtime, costing TLB
20
+
* to avoid kernel synthesizing it on user stack at runtime, costing TLB
20
21
* probes and Cache line flushes.
21
22
*
22
23
* vineetg: July 2009
+1
-1
arch/arc/kernel/traps.c
+1
-1
arch/arc/kernel/traps.c
+2
-2
arch/arc/kernel/vmlinux.lds.S
+2
-2
arch/arc/kernel/vmlinux.lds.S
···
41
41
#endif
42
42
43
43
/*
44
-
* The reason for having a seperate subsection .init.ramfs is to
45
-
* prevent objump from including it in kernel dumps
44
+
* The reason for having a separate subsection .init.ramfs is to
45
+
* prevent objdump from including it in kernel dumps
46
46
*
47
47
* Reason for having .init.ramfs above .init is to make sure that the
48
48
* binary blob is tucked away to one side, reducing the displacement
+2
-2
arch/arc/mm/tlb.c
+2
-2
arch/arc/mm/tlb.c
···
212
212
unsigned long flags;
213
213
214
214
/* If range @start to @end is more than 32 TLB entries deep,
215
-
* its better to move to a new ASID rather than searching for
215
+
* it's better to move to a new ASID rather than searching for
216
216
* individual entries and then shooting them down
217
217
*
218
218
* The calc above is rough, doesn't account for unaligned parts,
···
408
408
* -More importantly it makes this handler inconsistent with fast-path
409
409
* TLB Refill handler which always deals with "current"
410
410
*
411
-
* Lets see the use cases when current->mm != vma->mm and we land here
411
+
* Let's see the use cases when current->mm != vma->mm and we land here
412
412
* 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
413
413
* Here VM wants to pre-install a TLB entry for user stack while
414
414
* current->mm still points to pre-execve mm (hence the condition).
+4
-4
arch/arc/mm/tlbex.S
+4
-4
arch/arc/mm/tlbex.S
···
5
5
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6
6
*
7
7
* Vineetg: April 2011 :
8
-
* -MMU v1: moved out legacy code into a seperate file
8
+
* -MMU v1: moved out legacy code into a separate file
9
9
* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
10
10
* helps avoid a shift when preparing PD0 from PTE
11
11
*
12
12
* Vineetg: July 2009
13
-
* -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14
-
* entry, so that it doesn't knock out it's I-TLB entry
13
+
* -For MMU V2, we need not do heuristics at the time of committing a D-TLB
14
+
* entry, so that it doesn't knock out its I-TLB entry
15
15
* -Some more fine tuning:
16
16
* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
17
17
*
18
18
* Vineetg: July 2009
19
19
* -Practically rewrote the I/D TLB Miss handlers
20
-
* Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
20
+
* Now 40 and 135 instructions apiece as compared to 131 and 449 resp.
21
21
* Hence Leaner by 1.5 K
22
22
* Used Conditional arithmetic to replace excessive branching
23
23
* Also used short instructions wherever possible