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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dt-bindings: clock: qcom: Add SM7150 DISPCC clocks
Add device tree bindings for the display clock controller on Qualcomm
SM7150 platform.
Co-developed-by: David Wronek <david@mainlining.org>
Signed-off-by: David Wronek <david@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-4-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Danila Tikhonov
and committed by
Bjorn Andersson
ca3a9106
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Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller for SM7150
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maintainers:
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- Danila Tikhonov <danila@jiaxyga.com>
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- David Wronek <david@mainlining.org>
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- Jens Reidel <adrian@travitia.xyz>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM7150.
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See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
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properties:
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compatible:
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const: qcom,sm7150-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board Always On XO source
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- description: GPLL0 source from GCC
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- description: Sleep clock source
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- description: Byte clock from MDSS DSI PHY0
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- description: Pixel clock from MDSS DSI PHY0
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- description: Byte clock from MDSS DSI PHY1
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- description: Pixel clock from MDSS DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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power-domains:
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maxItems: 1
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description:
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CX power domain.
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required:
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- compatible
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- clocks
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- power-domains
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm7150-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm7150-dispcc";
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reg = <0x0af00000 0x200000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&sleep_clk>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,sm7150-dispcc.h
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include/dt-bindings/clock/qcom,sm7150-dispcc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
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* Copyright (c) 2024, David Wronek <david@mainlining.org>
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
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#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
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/* DISPCC clock registers */
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#define DISPCC_PLL0 0
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#define DISPCC_MDSS_AHB_CLK 1
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#define DISPCC_MDSS_AHB_CLK_SRC 2
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#define DISPCC_MDSS_BYTE0_CLK 3
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#define DISPCC_MDSS_BYTE0_CLK_SRC 4
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#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISPCC_MDSS_BYTE0_INTF_CLK 6
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#define DISPCC_MDSS_BYTE1_CLK 7
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#define DISPCC_MDSS_BYTE1_CLK_SRC 8
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#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9
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#define DISPCC_MDSS_BYTE1_INTF_CLK 10
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#define DISPCC_MDSS_DP_AUX_CLK 11
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#define DISPCC_MDSS_DP_AUX_CLK_SRC 12
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#define DISPCC_MDSS_DP_CRYPTO_CLK 13
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#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14
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#define DISPCC_MDSS_DP_LINK_CLK 15
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#define DISPCC_MDSS_DP_LINK_CLK_SRC 16
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#define DISPCC_MDSS_DP_LINK_INTF_CLK 17
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#define DISPCC_MDSS_DP_PIXEL1_CLK 18
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#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19
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#define DISPCC_MDSS_DP_PIXEL_CLK 20
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#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21
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#define DISPCC_MDSS_ESC0_CLK 22
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#define DISPCC_MDSS_ESC0_CLK_SRC 23
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#define DISPCC_MDSS_ESC1_CLK 24
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#define DISPCC_MDSS_ESC1_CLK_SRC 25
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#define DISPCC_MDSS_MDP_CLK 26
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#define DISPCC_MDSS_MDP_CLK_SRC 27
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#define DISPCC_MDSS_MDP_LUT_CLK 28
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#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29
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#define DISPCC_MDSS_PCLK0_CLK 30
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#define DISPCC_MDSS_PCLK0_CLK_SRC 31
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#define DISPCC_MDSS_PCLK1_CLK 32
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#define DISPCC_MDSS_PCLK1_CLK_SRC 33
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#define DISPCC_MDSS_ROT_CLK 34
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#define DISPCC_MDSS_ROT_CLK_SRC 35
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#define DISPCC_MDSS_RSCC_AHB_CLK 36
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#define DISPCC_MDSS_RSCC_VSYNC_CLK 37
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#define DISPCC_MDSS_VSYNC_CLK 38
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#define DISPCC_MDSS_VSYNC_CLK_SRC 39
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#define DISPCC_XO_CLK_SRC 40
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#define DISPCC_SLEEP_CLK 41
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#define DISPCC_SLEEP_CLK_SRC 42
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/* DISPCC GDSCR */
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#define MDSS_GDSC 0
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#endif