Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - add LF reset on queue disable
CPT LF must be reset and follow CPT LF disable sequence
suggested by HW team, when driver exits.
This patch adds code for the same.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Srujana Challa
and committed by
Herbert Xu
cac482f2
9d1d5702
+85
-28
+1
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+1
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
···
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int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);
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int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot);
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#endif /* __OTX2_CPT_COMMON_H */
+26
drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
+26
drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
···
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return otx2_mbox_check_rsp_msgs(mbox, 0);
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cpt_sync_mbox_msg, CRYPTO_DEV_OCTEONTX2_CPT);
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int otx2_cpt_lf_reset_msg(struct otx2_cptlfs_info *lfs, int slot)
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{
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struct otx2_mbox *mbox = lfs->mbox;
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struct pci_dev *pdev = lfs->pdev;
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struct cpt_lf_rst_req *req;
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int ret;
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req = (struct cpt_lf_rst_req *)otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
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sizeof(struct msg_rsp));
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if (!req) {
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dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
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return -EFAULT;
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}
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+
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req->hdr.id = MBOX_MSG_CPT_LF_RESET;
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req->hdr.sig = OTX2_MBOX_REQ_SIG;
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req->hdr.pcifunc = 0;
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req->slot = slot;
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ret = otx2_cpt_send_mbox_msg(mbox, pdev);
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if (ret)
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return ret;
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cpt_lf_reset_msg, CRYPTO_DEV_OCTEONTX2_CPT);
+50
-25
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+50
-25
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
···
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5
#define __OTX2_CPTLF_H
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#include <linux/soc/marvell/octeontx2/asm.h>
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#include <linux/bitfield.h>
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#include <mbox.h>
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#include <rvu.h>
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#include "otx2_cpt_common.h"
···
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u8 kvf_limits; /* Kernel crypto limits */
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atomic_t state; /* LF's state. started/reset */
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int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
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int global_slot; /* Global slot across the blocks */
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};
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static inline void otx2_cpt_free_instruction_queues(
···
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otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]);
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}
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+
#define INFLIGHT GENMASK_ULL(8, 0)
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#define GRB_CNT GENMASK_ULL(39, 32)
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#define GWB_CNT GENMASK_ULL(47, 40)
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#define XQ_XOR GENMASK_ULL(63, 63)
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#define DQPTR GENMASK_ULL(19, 0)
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#define NQPTR GENMASK_ULL(51, 32)
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static inline void otx2_cptlf_do_disable_iqueue(struct otx2_cptlf_info *lf)
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{
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-
union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };
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union otx2_cptx_lf_inprog lf_inprog;
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void __iomem *reg_base = lf->lfs->reg_base;
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struct pci_dev *pdev = lf->lfs->pdev;
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u8 blkaddr = lf->lfs->blkaddr;
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-
int timeout = 20;
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int timeout = 1000000;
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u64 inprog, inst_ptr;
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u64 slot = lf->slot;
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u64 qsize, pending;
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int i = 0;
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/* Disable instructions enqueuing */
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otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
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OTX2_CPT_LF_CTL, lf_ctl.u);
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otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_CTL, 0x0);
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-
/* Wait for instruction queue to become empty */
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inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);
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inprog |= BIT_ULL(16);
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otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG, inprog);
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qsize = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_SIZE) & 0x7FFF;
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do {
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lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr,
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lf->slot, OTX2_CPT_LF_INPROG);
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if (!lf_inprog.s.inflight)
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break;
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inst_ptr = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_INST_PTR);
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pending = (FIELD_GET(XQ_XOR, inst_ptr) * qsize * 40) +
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FIELD_GET(NQPTR, inst_ptr) - FIELD_GET(DQPTR, inst_ptr);
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udelay(1);
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timeout--;
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} while ((pending != 0) && (timeout != 0));
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-
usleep_range(10000, 20000);
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if (timeout-- < 0) {
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dev_err(&lf->lfs->pdev->dev,
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"Error LF %d is still busy.\n", lf->slot);
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-
break;
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if (timeout == 0)
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dev_warn(&pdev->dev, "TIMEOUT: CPT poll on pending instructions\n");
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timeout = 1000000;
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/* Wait for CPT queue to become execution-quiescent */
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do {
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inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);
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+
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if ((FIELD_GET(INFLIGHT, inprog) == 0) &&
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(FIELD_GET(GRB_CNT, inprog) == 0)) {
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i++;
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} else {
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i = 0;
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timeout--;
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}
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} while ((timeout != 0) && (i < 10));
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-
} while (1);
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-
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/*
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* Disable executions in the LF's queue,
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* the queue should be empty at this point
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*/
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lf_inprog.s.eena = 0x0;
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otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
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OTX2_CPT_LF_INPROG, lf_inprog.u);
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if (timeout == 0)
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dev_warn(&pdev->dev, "TIMEOUT: CPT poll on inflight count\n");
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/* Wait for 2 us to flush all queue writes to memory */
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udelay(2);
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}
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static inline void otx2_cptlf_disable_iqueues(struct otx2_cptlfs_info *lfs)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]);
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otx2_cpt_lf_reset_msg(lfs, lfs->global_slot + slot);
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}
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}
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static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,
+6
-3
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+6
-3
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
···
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struct mbox_msghdr *req)
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{
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struct otx2_cpt_rx_inline_lf_cfg *cfg_req;
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int num_lfs = 1, ret;
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u8 egrp;
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-
int ret;
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cfg_req = (struct otx2_cpt_rx_inline_lf_cfg *)req;
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if (cptpf->lfs.lfs_num) {
···
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otx2_cptlf_set_dev_info(&cptpf->lfs, cptpf->pdev, cptpf->reg_base,
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&cptpf->afpf_mbox, BLKADDR_CPT0);
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+
cptpf->lfs.global_slot = 0;
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ret = otx2_cptlf_init(&cptpf->lfs, 1 << egrp, OTX2_CPT_QUEUE_HI_PRIO,
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-
1);
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num_lfs);
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if (ret) {
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dev_err(&cptpf->pdev->dev,
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"LF configuration failed for RX inline ipsec.\n");
···
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otx2_cptlf_set_dev_info(&cptpf->cpt1_lfs, cptpf->pdev,
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cptpf->reg_base, &cptpf->afpf_mbox,
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BLKADDR_CPT1);
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cptpf->cpt1_lfs.global_slot = num_lfs;
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ret = otx2_cptlf_init(&cptpf->cpt1_lfs, 1 << egrp,
241
-
OTX2_CPT_QUEUE_HI_PRIO, 1);
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OTX2_CPT_QUEUE_HI_PRIO, num_lfs);
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if (ret) {
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dev_err(&cptpf->pdev->dev,
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"LF configuration failed for RX inline ipsec.\n");
···
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break;
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case MBOX_MSG_CPT_INLINE_IPSEC_CFG:
453
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case MBOX_MSG_NIX_INLINE_IPSEC_CFG:
452
+
case MBOX_MSG_CPT_LF_RESET:
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break;
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default:
+2
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
+2
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c