perf vendor events: Add silvermont counter information

+77

tools/perf/pmu-events/arch/x86/silvermont/cache.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.", 4 + "Counter": "0,1", 4 5 "EventCode": "0x31", 5 6 "EventName": "CORE_REJECT_L2Q.ALL", 6 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", ··· 9 8 }, 10 9 { 11 10 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 11 + "Counter": "0,1", 12 12 "EventCode": "0x86", 13 13 "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", 14 14 "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", ··· 18 16 }, 19 17 { 20 18 "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ", 19 + "Counter": "0,1", 21 20 "EventCode": "0x30", 22 21 "EventName": "L2_REJECT_XQ.ALL", 23 22 "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).", ··· 26 23 }, 27 24 { 28 25 "BriefDescription": "L2 cache request misses", 26 + "Counter": "0,1", 29 27 "EventCode": "0x2E", 30 28 "EventName": "LONGEST_LAT_CACHE.MISS", 31 29 "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.", ··· 35 31 }, 36 32 { 37 33 "BriefDescription": "L2 cache requests from this core", 34 + "Counter": "0,1", 38 35 "EventCode": "0x2E", 39 36 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 40 37 "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.", ··· 44 39 }, 45 40 { 46 41 "BriefDescription": "All Loads", 42 + "Counter": "0,1", 47 43 "EventCode": "0x04", 48 44 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 49 45 "PublicDescription": "This event counts the number of load ops retired.", ··· 53 47 }, 54 48 { 55 49 "BriefDescription": "All Stores", 50 + "Counter": "0,1", 56 51 "EventCode": "0x04", 57 52 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 58 53 "PublicDescription": "This event counts the number of store ops retired.", ··· 62 55 }, 63 56 { 64 57 "BriefDescription": "Cross core or cross module hitm", 58 + "Counter": "0,1", 65 59 "EventCode": "0x04", 66 60 "EventName": "MEM_UOPS_RETIRED.HITM", 67 61 "PEBS": "1", ··· 72 64 }, 73 65 { 74 66 "BriefDescription": "Loads missed L1", 67 + "Counter": "0,1", 75 68 "EventCode": "0x04", 76 69 "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", 77 70 "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", ··· 81 72 }, 82 73 { 83 74 "BriefDescription": "Loads hit L2", 75 + "Counter": "0,1", 84 76 "EventCode": "0x04", 85 77 "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", 86 78 "PEBS": "1", ··· 91 81 }, 92 82 { 93 83 "BriefDescription": "Loads missed L2", 84 + "Counter": "0,1", 94 85 "EventCode": "0x04", 95 86 "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", 96 87 "PEBS": "1", ··· 101 90 }, 102 91 { 103 92 "BriefDescription": "Loads missed UTLB", 93 + "Counter": "0,1", 104 94 "EventCode": "0x04", 105 95 "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", 106 96 "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.", ··· 110 98 }, 111 99 { 112 100 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", 101 + "Counter": "0,1", 113 102 "EventCode": "0xB7", 114 103 "EventName": "OFFCORE_RESPONSE", 115 104 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", ··· 119 106 }, 120 107 { 121 108 "BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.", 109 + "Counter": "0,1", 122 110 "EventCode": "0xB7", 123 111 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", 124 112 "MSRIndex": "0x1a6,0x1a7", ··· 129 115 }, 130 116 { 131 117 "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.", 118 + "Counter": "0,1", 132 119 "EventCode": "0xB7", 133 120 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", 134 121 "MSRIndex": "0x1a6,0x1a7", ··· 139 124 }, 140 125 { 141 126 "BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", 127 + "Counter": "0,1", 142 128 "EventCode": "0xB7", 143 129 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE", 144 130 "MSRIndex": "0x1a6,0x1a7", ··· 149 133 }, 150 134 { 151 135 "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 136 + "Counter": "0,1", 152 137 "EventCode": "0xB7", 153 138 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 154 139 "MSRIndex": "0x1a6,0x1a7", ··· 159 142 }, 160 143 { 161 144 "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.", 145 + "Counter": "0,1", 162 146 "EventCode": "0xB7", 163 147 "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", 164 148 "MSRIndex": "0x1a6,0x1a7", ··· 169 151 }, 170 152 { 171 153 "BriefDescription": "Counts any data read (demand & prefetch) that have any response type.", 154 + "Counter": "0,1", 172 155 "EventCode": "0xB7", 173 156 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", 174 157 "MSRIndex": "0x1a6,0x1a7", ··· 179 160 }, 180 161 { 181 162 "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.", 163 + "Counter": "0,1", 182 164 "EventCode": "0xB7", 183 165 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", 184 166 "MSRIndex": "0x1a6,0x1a7", ··· 189 169 }, 190 170 { 191 171 "BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", 172 + "Counter": "0,1", 192 173 "EventCode": "0xB7", 193 174 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", 194 175 "MSRIndex": "0x1a6,0x1a7", ··· 199 178 }, 200 179 { 201 180 "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 181 + "Counter": "0,1", 202 182 "EventCode": "0xB7", 203 183 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 204 184 "MSRIndex": "0x1a6,0x1a7", ··· 209 187 }, 210 188 { 211 189 "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.", 190 + "Counter": "0,1", 212 191 "EventCode": "0xB7", 213 192 "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", 214 193 "MSRIndex": "0x1a6,0x1a7", ··· 219 196 }, 220 197 { 221 198 "BriefDescription": "Counts any request that have any response type.", 199 + "Counter": "0,1", 222 200 "EventCode": "0xB7", 223 201 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", 224 202 "MSRIndex": "0x1a6,0x1a7", ··· 229 205 }, 230 206 { 231 207 "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.", 208 + "Counter": "0,1", 232 209 "EventCode": "0xB7", 233 210 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", 234 211 "MSRIndex": "0x1a6,0x1a7", ··· 239 214 }, 240 215 { 241 216 "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 217 + "Counter": "0,1", 242 218 "EventCode": "0xB7", 243 219 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", 244 220 "MSRIndex": "0x1a6,0x1a7", ··· 249 223 }, 250 224 { 251 225 "BriefDescription": "Counts any request that miss L2 with a snoop miss response.", 226 + "Counter": "0,1", 252 227 "EventCode": "0xB7", 253 228 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", 254 229 "MSRIndex": "0x1a6,0x1a7", ··· 259 232 }, 260 233 { 261 234 "BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.", 235 + "Counter": "0,1", 262 236 "EventCode": "0xB7", 263 237 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", 264 238 "MSRIndex": "0x1a6,0x1a7", ··· 269 241 }, 270 242 { 271 243 "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.", 244 + "Counter": "0,1", 272 245 "EventCode": "0xB7", 273 246 "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", 274 247 "MSRIndex": "0x1a6,0x1a7", ··· 279 250 }, 280 251 { 281 252 "BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", 253 + "Counter": "0,1", 282 254 "EventCode": "0xB7", 283 255 "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", 284 256 "MSRIndex": "0x1a6,0x1a7", ··· 289 259 }, 290 260 { 291 261 "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 262 + "Counter": "0,1", 292 263 "EventCode": "0xB7", 293 264 "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", 294 265 "MSRIndex": "0x1a6,0x1a7", ··· 299 268 }, 300 269 { 301 270 "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.", 271 + "Counter": "0,1", 302 272 "EventCode": "0xB7", 303 273 "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", 304 274 "MSRIndex": "0x1a6,0x1a7", ··· 309 277 }, 310 278 { 311 279 "BriefDescription": "Counts writeback (modified to exclusive) that miss L2.", 280 + "Counter": "0,1", 312 281 "EventCode": "0xB7", 313 282 "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", 314 283 "MSRIndex": "0x1a6,0x1a7", ··· 319 286 }, 320 287 { 321 288 "BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.", 289 + "Counter": "0,1", 322 290 "EventCode": "0xB7", 323 291 "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", 324 292 "MSRIndex": "0x1a6,0x1a7", ··· 329 295 }, 330 296 { 331 297 "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.", 298 + "Counter": "0,1", 332 299 "EventCode": "0xB7", 333 300 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", 334 301 "MSRIndex": "0x1a6,0x1a7", ··· 339 304 }, 340 305 { 341 306 "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.", 307 + "Counter": "0,1", 342 308 "EventCode": "0xB7", 343 309 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", 344 310 "MSRIndex": "0x1a6,0x1a7", ··· 349 313 }, 350 314 { 351 315 "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 316 + "Counter": "0,1", 352 317 "EventCode": "0xB7", 353 318 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 354 319 "MSRIndex": "0x1a6,0x1a7", ··· 359 322 }, 360 323 { 361 324 "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.", 325 + "Counter": "0,1", 362 326 "EventCode": "0xB7", 363 327 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", 364 328 "MSRIndex": "0x1a6,0x1a7", ··· 369 331 }, 370 332 { 371 333 "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", 334 + "Counter": "0,1", 372 335 "EventCode": "0xB7", 373 336 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", 374 337 "MSRIndex": "0x1a6", ··· 379 340 }, 380 341 { 381 342 "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.", 343 + "Counter": "0,1", 382 344 "EventCode": "0xB7", 383 345 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", 384 346 "MSRIndex": "0x1a6,0x1a7", ··· 389 349 }, 390 350 { 391 351 "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.", 352 + "Counter": "0,1", 392 353 "EventCode": "0xB7", 393 354 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", 394 355 "MSRIndex": "0x1a6,0x1a7", ··· 399 358 }, 400 359 { 401 360 "BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.", 361 + "Counter": "0,1", 402 362 "EventCode": "0xB7", 403 363 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", 404 364 "MSRIndex": "0x1a6,0x1a7", ··· 409 367 }, 410 368 { 411 369 "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 370 + "Counter": "0,1", 412 371 "EventCode": "0xB7", 413 372 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 414 373 "MSRIndex": "0x1a6,0x1a7", ··· 419 376 }, 420 377 { 421 378 "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.", 379 + "Counter": "0,1", 422 380 "EventCode": "0xB7", 423 381 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", 424 382 "MSRIndex": "0x1a6,0x1a7", ··· 429 385 }, 430 386 { 431 387 "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", 388 + "Counter": "0,1", 432 389 "EventCode": "0xB7", 433 390 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", 434 391 "MSRIndex": "0x1a6", ··· 439 394 }, 440 395 { 441 396 "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.", 397 + "Counter": "0,1", 442 398 "EventCode": "0xB7", 443 399 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", 444 400 "MSRIndex": "0x1a6,0x1a7", ··· 449 403 }, 450 404 { 451 405 "BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.", 406 + "Counter": "0,1", 452 407 "EventCode": "0xB7", 453 408 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", 454 409 "MSRIndex": "0x1a6,0x1a7", ··· 459 412 }, 460 413 { 461 414 "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 415 + "Counter": "0,1", 462 416 "EventCode": "0xB7", 463 417 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", 464 418 "MSRIndex": "0x1a6,0x1a7", ··· 469 421 }, 470 422 { 471 423 "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.", 424 + "Counter": "0,1", 472 425 "EventCode": "0xB7", 473 426 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", 474 427 "MSRIndex": "0x1a6,0x1a7", ··· 479 430 }, 480 431 { 481 432 "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", 433 + "Counter": "0,1", 482 434 "EventCode": "0xB7", 483 435 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", 484 436 "MSRIndex": "0x1a6", ··· 489 439 }, 490 440 { 491 441 "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.", 442 + "Counter": "0,1", 492 443 "EventCode": "0xB7", 493 444 "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", 494 445 "MSRIndex": "0x1a6,0x1a7", ··· 499 448 }, 500 449 { 501 450 "BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.", 451 + "Counter": "0,1", 502 452 "EventCode": "0xB7", 503 453 "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", 504 454 "MSRIndex": "0x1a6,0x1a7", ··· 509 457 }, 510 458 { 511 459 "BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.", 460 + "Counter": "0,1", 512 461 "EventCode": "0xB7", 513 462 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", 514 463 "MSRIndex": "0x1a6,0x1a7", ··· 519 466 }, 520 467 { 521 468 "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.", 469 + "Counter": "0,1", 522 470 "EventCode": "0xB7", 523 471 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", 524 472 "MSRIndex": "0x1a6,0x1a7", ··· 529 475 }, 530 476 { 531 477 "BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.", 478 + "Counter": "0,1", 532 479 "EventCode": "0xB7", 533 480 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", 534 481 "MSRIndex": "0x1a6,0x1a7", ··· 539 484 }, 540 485 { 541 486 "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 487 + "Counter": "0,1", 542 488 "EventCode": "0xB7", 543 489 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 544 490 "MSRIndex": "0x1a6,0x1a7", ··· 549 493 }, 550 494 { 551 495 "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.", 496 + "Counter": "0,1", 552 497 "EventCode": "0xB7", 553 498 "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", 554 499 "MSRIndex": "0x1a6,0x1a7", ··· 559 502 }, 560 503 { 561 504 "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.", 505 + "Counter": "0,1", 562 506 "EventCode": "0xB7", 563 507 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", 564 508 "MSRIndex": "0x1a6,0x1a7", ··· 569 511 }, 570 512 { 571 513 "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 514 + "Counter": "0,1", 572 515 "EventCode": "0xB7", 573 516 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 574 517 "MSRIndex": "0x1a6,0x1a7", ··· 579 520 }, 580 521 { 581 522 "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.", 523 + "Counter": "0,1", 582 524 "EventCode": "0xB7", 583 525 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", 584 526 "MSRIndex": "0x1a6,0x1a7", ··· 589 529 }, 590 530 { 591 531 "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.", 532 + "Counter": "0,1", 592 533 "EventCode": "0xB7", 593 534 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", 594 535 "MSRIndex": "0x1a6,0x1a7", ··· 599 538 }, 600 539 { 601 540 "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", 541 + "Counter": "0,1", 602 542 "EventCode": "0xB7", 603 543 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", 604 544 "MSRIndex": "0x1a6,0x1a7", ··· 609 547 }, 610 548 { 611 549 "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 550 + "Counter": "0,1", 612 551 "EventCode": "0xB7", 613 552 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", 614 553 "MSRIndex": "0x1a6,0x1a7", ··· 619 556 }, 620 557 { 621 558 "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.", 559 + "Counter": "0,1", 622 560 "EventCode": "0xB7", 623 561 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", 624 562 "MSRIndex": "0x1a6,0x1a7", ··· 629 565 }, 630 566 { 631 567 "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.", 568 + "Counter": "0,1", 632 569 "EventCode": "0xB7", 633 570 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", 634 571 "MSRIndex": "0x1a6,0x1a7", ··· 639 574 }, 640 575 { 641 576 "BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", 577 + "Counter": "0,1", 642 578 "EventCode": "0xB7", 643 579 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", 644 580 "MSRIndex": "0x1a6,0x1a7", ··· 649 583 }, 650 584 { 651 585 "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", 586 + "Counter": "0,1", 652 587 "EventCode": "0xB7", 653 588 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", 654 589 "MSRIndex": "0x1a6,0x1a7", ··· 659 592 }, 660 593 { 661 594 "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.", 595 + "Counter": "0,1", 662 596 "EventCode": "0xB7", 663 597 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", 664 598 "MSRIndex": "0x1a6,0x1a7", ··· 669 601 }, 670 602 { 671 603 "BriefDescription": "Counts streaming store that miss L2.", 604 + "Counter": "0,1", 672 605 "EventCode": "0xB7", 673 606 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", 674 607 "MSRIndex": "0x1a6,0x1a7", ··· 679 610 }, 680 611 { 681 612 "BriefDescription": "Any reissued load uops", 613 + "Counter": "0,1", 682 614 "EventCode": "0x03", 683 615 "EventName": "REHABQ.ANY_LD", 684 616 "PublicDescription": "This event counts the number of load uops reissued from Rehabq.", ··· 688 618 }, 689 619 { 690 620 "BriefDescription": "Any reissued store uops", 621 + "Counter": "0,1", 691 622 "EventCode": "0x03", 692 623 "EventName": "REHABQ.ANY_ST", 693 624 "PublicDescription": "This event counts the number of store uops reissued from Rehabq.", ··· 697 626 }, 698 627 { 699 628 "BriefDescription": "Loads blocked due to store data not ready", 629 + "Counter": "0,1", 700 630 "EventCode": "0x03", 701 631 "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", 702 632 "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.", ··· 706 634 }, 707 635 { 708 636 "BriefDescription": "Loads blocked due to store forward restriction", 637 + "Counter": "0,1", 709 638 "EventCode": "0x03", 710 639 "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", 711 640 "PEBS": "1", ··· 716 643 }, 717 644 { 718 645 "BriefDescription": "Load uops that split cache line boundary", 646 + "Counter": "0,1", 719 647 "EventCode": "0x03", 720 648 "EventName": "REHABQ.LD_SPLITS", 721 649 "PEBS": "1", ··· 726 652 }, 727 653 { 728 654 "BriefDescription": "Uops with lock semantics", 655 + "Counter": "0,1", 729 656 "EventCode": "0x03", 730 657 "EventName": "REHABQ.LOCK", 731 658 "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).", ··· 735 660 }, 736 661 { 737 662 "BriefDescription": "Store address buffer full", 663 + "Counter": "0,1", 738 664 "EventCode": "0x03", 739 665 "EventName": "REHABQ.STA_FULL", 740 666 "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.", ··· 744 668 }, 745 669 { 746 670 "BriefDescription": "Store uops that split cache line boundary", 671 + "Counter": "0,1", 747 672 "EventCode": "0x03", 748 673 "EventName": "REHABQ.ST_SPLITS", 749 674 "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.",

+7

tools/perf/pmu-events/arch/x86/silvermont/counter.json

··· 1 + [ 2 + { 3 + "Unit": "core", 4 + "CountersNumFixed": "4", 5 + "CountersNumGeneric": "2" 6 + } 7 + ]

+1

tools/perf/pmu-events/arch/x86/silvermont/floating-point.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Stalls due to FP assists", 4 + "Counter": "0,1", 4 5 "EventCode": "0xC3", 5 6 "EventName": "MACHINE_CLEARS.FP_ASSIST", 6 7 "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.",

+8

tools/perf/pmu-events/arch/x86/silvermont/frontend.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Counts the number of baclears", 4 + "Counter": "0,1", 4 5 "EventCode": "0xE6", 5 6 "EventName": "BACLEARS.ALL", 6 7 "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch.", ··· 10 9 }, 11 10 { 12 11 "BriefDescription": "Counts the number of JCC baclears", 12 + "Counter": "0,1", 13 13 "EventCode": "0xE6", 14 14 "EventName": "BACLEARS.COND", 15 15 "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Conditional Code) baclears.", ··· 19 17 }, 20 18 { 21 19 "BriefDescription": "Counts the number of RETURN baclears", 20 + "Counter": "0,1", 22 21 "EventCode": "0xE6", 23 22 "EventName": "BACLEARS.RETURN", 24 23 "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears.", ··· 28 25 }, 29 26 { 30 27 "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction", 28 + "Counter": "0,1", 31 29 "EventCode": "0xE9", 32 30 "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", 33 31 "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.", ··· 37 33 }, 38 34 { 39 35 "BriefDescription": "Instruction fetches", 36 + "Counter": "0,1", 40 37 "EventCode": "0x80", 41 38 "EventName": "ICACHE.ACCESSES", 42 39 "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.", ··· 46 41 }, 47 42 { 48 43 "BriefDescription": "Instruction fetches from Icache", 44 + "Counter": "0,1", 49 45 "EventCode": "0x80", 50 46 "EventName": "ICACHE.HIT", 51 47 "PublicDescription": "This event counts all instruction fetches from the instruction cache.", ··· 55 49 }, 56 50 { 57 51 "BriefDescription": "Icache miss", 52 + "Counter": "0,1", 58 53 "EventCode": "0x80", 59 54 "EventName": "ICACHE.MISSES", 60 55 "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", ··· 64 57 }, 65 58 { 66 59 "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count.", 60 + "Counter": "0,1", 67 61 "EventCode": "0xE7", 68 62 "EventName": "MS_DECODED.MS_ENTRY", 69 63 "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.",

+1

tools/perf/pmu-events/arch/x86/silvermont/memory.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Stalls due to Memory ordering", 4 + "Counter": "0,1", 4 5 "EventCode": "0xC3", 5 6 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 6 7 "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.",

+2

tools/perf/pmu-events/arch/x86/silvermont/other.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Cycles code-fetch stalled due to any reason.", 4 + "Counter": "0,1", 4 5 "EventCode": "0x86", 5 6 "EventName": "FETCH_STALL.ALL", 6 7 "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", ··· 10 9 }, 11 10 { 12 11 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.", 12 + "Counter": "0,1", 13 13 "EventCode": "0x86", 14 14 "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", 15 15 "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",

+34

tools/perf/pmu-events/arch/x86/silvermont/pipeline.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Counts the number of branch instructions retired...", 4 + "Counter": "0,1", 4 5 "EventCode": "0xC4", 5 6 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 6 7 "PEBS": "1", ··· 10 9 }, 11 10 { 12 11 "BriefDescription": "Counts the number of taken branch instructions retired", 12 + "Counter": "0,1", 13 13 "EventCode": "0xC4", 14 14 "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", 15 15 "PEBS": "2", ··· 20 18 }, 21 19 { 22 20 "BriefDescription": "Counts the number of near CALL branch instructions retired", 21 + "Counter": "0,1", 23 22 "EventCode": "0xC4", 24 23 "EventName": "BR_INST_RETIRED.CALL", 25 24 "PEBS": "1", ··· 30 27 }, 31 28 { 32 29 "BriefDescription": "Counts the number of far branch instructions retired", 30 + "Counter": "0,1", 33 31 "EventCode": "0xC4", 34 32 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 35 33 "PEBS": "1", ··· 40 36 }, 41 37 { 42 38 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired", 39 + "Counter": "0,1", 43 40 "EventCode": "0xC4", 44 41 "EventName": "BR_INST_RETIRED.IND_CALL", 45 42 "PEBS": "1", ··· 50 45 }, 51 46 { 52 47 "BriefDescription": "Counts the number of JCC branch instructions retired", 48 + "Counter": "0,1", 53 49 "EventCode": "0xC4", 54 50 "EventName": "BR_INST_RETIRED.JCC", 55 51 "PEBS": "1", ··· 60 54 }, 61 55 { 62 56 "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired", 57 + "Counter": "0,1", 63 58 "EventCode": "0xC4", 64 59 "EventName": "BR_INST_RETIRED.NON_RETURN_IND", 65 60 "PEBS": "1", ··· 70 63 }, 71 64 { 72 65 "BriefDescription": "Counts the number of near relative CALL branch instructions retired", 66 + "Counter": "0,1", 73 67 "EventCode": "0xC4", 74 68 "EventName": "BR_INST_RETIRED.REL_CALL", 75 69 "PEBS": "1", ··· 80 72 }, 81 73 { 82 74 "BriefDescription": "Counts the number of near RET branch instructions retired", 75 + "Counter": "0,1", 83 76 "EventCode": "0xC4", 84 77 "EventName": "BR_INST_RETIRED.RETURN", 85 78 "PEBS": "1", ··· 90 81 }, 91 82 { 92 83 "BriefDescription": "Counts the number of taken JCC branch instructions retired", 84 + "Counter": "0,1", 93 85 "EventCode": "0xC4", 94 86 "EventName": "BR_INST_RETIRED.TAKEN_JCC", 95 87 "PEBS": "1", ··· 100 90 }, 101 91 { 102 92 "BriefDescription": "Counts the number of mispredicted branch instructions retired", 93 + "Counter": "0,1", 103 94 "EventCode": "0xC5", 104 95 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 105 96 "PEBS": "1", ··· 109 98 }, 110 99 { 111 100 "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired", 101 + "Counter": "0,1", 112 102 "EventCode": "0xC5", 113 103 "EventName": "BR_MISP_RETIRED.IND_CALL", 114 104 "PEBS": "1", ··· 119 107 }, 120 108 { 121 109 "BriefDescription": "Counts the number of mispredicted JCC branch instructions retired", 110 + "Counter": "0,1", 122 111 "EventCode": "0xC5", 123 112 "EventName": "BR_MISP_RETIRED.JCC", 124 113 "PEBS": "1", ··· 129 116 }, 130 117 { 131 118 "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired", 119 + "Counter": "0,1", 132 120 "EventCode": "0xC5", 133 121 "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", 134 122 "PEBS": "1", ··· 139 125 }, 140 126 { 141 127 "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired", 128 + "Counter": "0,1", 142 129 "EventCode": "0xC5", 143 130 "EventName": "BR_MISP_RETIRED.RETURN", 144 131 "PEBS": "1", ··· 149 134 }, 150 135 { 151 136 "BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired", 137 + "Counter": "0,1", 152 138 "EventCode": "0xC5", 153 139 "EventName": "BR_MISP_RETIRED.TAKEN_JCC", 154 140 "PEBS": "1", ··· 159 143 }, 160 144 { 161 145 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 146 + "Counter": "Fixed counter 2", 162 147 "EventName": "CPU_CLK_UNHALTED.CORE", 163 148 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", 164 149 "SampleAfterValue": "2000003", ··· 167 150 }, 168 151 { 169 152 "BriefDescription": "Core cycles when core is not halted", 153 + "Counter": "0,1", 170 154 "EventCode": "0x3C", 171 155 "EventName": "CPU_CLK_UNHALTED.CORE_P", 172 156 "PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.", ··· 175 157 }, 176 158 { 177 159 "BriefDescription": "Reference cycles when core is not halted", 160 + "Counter": "0,1", 178 161 "EventCode": "0x3C", 179 162 "EventName": "CPU_CLK_UNHALTED.REF", 180 163 "PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.", ··· 184 165 }, 185 166 { 186 167 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", 168 + "Counter": "Fixed counter 3", 187 169 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 188 170 "PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", 189 171 "SampleAfterValue": "2000003", ··· 192 172 }, 193 173 { 194 174 "BriefDescription": "Cycles the divider is busy. Does not imply a stall waiting for the divider.", 175 + "Counter": "0,1", 195 176 "EventCode": "0xCD", 196 177 "EventName": "CYCLES_DIV_BUSY.ALL", 197 178 "PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.", ··· 201 180 }, 202 181 { 203 182 "BriefDescription": "Fixed Counter: Counts the number of instructions retired", 183 + "Counter": "Fixed counter 1", 204 184 "EventName": "INST_RETIRED.ANY", 205 185 "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", 206 186 "SampleAfterValue": "2000003", ··· 209 187 }, 210 188 { 211 189 "BriefDescription": "Instructions retired", 190 + "Counter": "0,1", 212 191 "EventCode": "0xC0", 213 192 "EventName": "INST_RETIRED.ANY_P", 214 193 "PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.", ··· 217 194 }, 218 195 { 219 196 "BriefDescription": "Counts all machine clears", 197 + "Counter": "0,1", 220 198 "EventCode": "0xC3", 221 199 "EventName": "MACHINE_CLEARS.ALL", 222 200 "PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions \"older\" than this one will be allowed to finish. This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.", ··· 226 202 }, 227 203 { 228 204 "BriefDescription": "Self-Modifying Code detected", 205 + "Counter": "0,1", 229 206 "EventCode": "0xC3", 230 207 "EventName": "MACHINE_CLEARS.SMC", 231 208 "PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.", ··· 235 210 }, 236 211 { 237 212 "BriefDescription": "Counts the number of cycles when no uops are allocated for any reason.", 213 + "Counter": "0,1", 238 214 "EventCode": "0xCA", 239 215 "EventName": "NO_ALLOC_CYCLES.ALL", 240 216 "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.", ··· 244 218 }, 245 219 { 246 220 "BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted", 221 + "Counter": "0,1", 247 222 "EventCode": "0xCA", 248 223 "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", 249 224 "PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted.", ··· 253 226 }, 254 227 { 255 228 "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.", 229 + "Counter": "0,1", 256 230 "EventCode": "0xCA", 257 231 "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", 258 232 "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth.", ··· 262 234 }, 263 235 { 264 236 "BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted.", 237 + "Counter": "0,1", 265 238 "EventCode": "0xCA", 266 239 "EventName": "NO_ALLOC_CYCLES.RAT_STALL", 267 240 "SampleAfterValue": "200003", ··· 270 241 }, 271 242 { 272 243 "BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)", 244 + "Counter": "0,1", 273 245 "EventCode": "0xCA", 274 246 "EventName": "NO_ALLOC_CYCLES.ROB_FULL", 275 247 "PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available).", ··· 279 249 }, 280 250 { 281 251 "BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.", 252 + "Counter": "0,1", 282 253 "EventCode": "0xCB", 283 254 "EventName": "RS_FULL_STALL.ALL", 284 255 "SampleAfterValue": "200003", ··· 287 256 }, 288 257 { 289 258 "BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M", 259 + "Counter": "0,1", 290 260 "EventCode": "0xCB", 291 261 "EventName": "RS_FULL_STALL.MEC", 292 262 "PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M.", ··· 296 264 }, 297 265 { 298 266 "BriefDescription": "Micro-ops retired", 267 + "Counter": "0,1", 299 268 "EventCode": "0xC2", 300 269 "EventName": "UOPS_RETIRED.ALL", 301 270 "PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops.", ··· 305 272 }, 306 273 { 307 274 "BriefDescription": "MSROM micro-ops retired", 275 + "Counter": "0,1", 308 276 "EventCode": "0xC2", 309 277 "EventName": "UOPS_RETIRED.MS", 310 278 "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",

+7

tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json

··· 1 1 [ 2 2 { 3 3 "BriefDescription": "Loads missed DTLB", 4 + "Counter": "0,1", 4 5 "EventCode": "0x04", 5 6 "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 6 7 "PEBS": "1", ··· 11 10 }, 12 11 { 13 12 "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)", 13 + "Counter": "0,1", 14 14 "EventCode": "0x05", 15 15 "EventName": "PAGE_WALKS.CYCLES", 16 16 "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", ··· 20 18 }, 21 19 { 22 20 "BriefDescription": "Duration of D-side page-walks in core cycles", 21 + "Counter": "0,1", 23 22 "EventCode": "0x05", 24 23 "EventName": "PAGE_WALKS.D_SIDE_CYCLES", 25 24 "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", ··· 29 26 }, 30 27 { 31 28 "BriefDescription": "D-side page-walks", 29 + "Counter": "0,1", 32 30 "EdgeDetect": "1", 33 31 "EventCode": "0x05", 34 32 "EventName": "PAGE_WALKS.D_SIDE_WALKS", ··· 39 35 }, 40 36 { 41 37 "BriefDescription": "Duration of I-side page-walks in core cycles", 38 + "Counter": "0,1", 42 39 "EventCode": "0x05", 43 40 "EventName": "PAGE_WALKS.I_SIDE_CYCLES", 44 41 "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", ··· 48 43 }, 49 44 { 50 45 "BriefDescription": "I-side page-walks", 46 + "Counter": "0,1", 51 47 "EdgeDetect": "1", 52 48 "EventCode": "0x05", 53 49 "EventName": "PAGE_WALKS.I_SIDE_WALKS", ··· 58 52 }, 59 53 { 60 54 "BriefDescription": "Total page walks that are completed (I-side and D-side)", 55 + "Counter": "0,1", 61 56 "EdgeDetect": "1", 62 57 "EventCode": "0x05", 63 58 "EventName": "PAGE_WALKS.WALKS",

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