+19

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

reviewed

··· 233 233 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) 234 234 return; 235 235 236 236 + if ((!pe->adev->df.funcs) || 237 237 + (!pe->adev->df.funcs->pmc_start)) 238 238 + return; 239 239 + 236 240 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); 237 241 hwc->state = 0; 238 242 ··· 272 268 pmu); 273 269 u64 count, prev; 274 270 271 271 + if ((!pe->adev->df.funcs) || 272 272 + (!pe->adev->df.funcs->pmc_get_count)) 273 273 + return; 274 274 + 275 275 do { 276 276 prev = local64_read(&hwc->prev_count); 277 277 ··· 303 295 pmu); 304 296 305 297 if (hwc->state & PERF_HES_UPTODATE) 298 298 + return; 299 299 + 300 300 + if ((!pe->adev->df.funcs) || 301 301 + (!pe->adev->df.funcs->pmc_stop)) 306 302 return; 307 303 308 304 switch (hwc->config_base) { ··· 337 325 struct amdgpu_pmu_entry *pe = container_of(event->pmu, 338 326 struct amdgpu_pmu_entry, 339 327 pmu); 328 328 + 329 329 + if ((!pe->adev->df.funcs) || 330 330 + (!pe->adev->df.funcs->pmc_start)) 331 331 + return -EINVAL; 340 332 341 333 switch (pe->pmu_perf_type) { 342 334 case AMDGPU_PMU_PERF_TYPE_DF: ··· 387 371 struct amdgpu_pmu_entry *pe = container_of(event->pmu, 388 372 struct amdgpu_pmu_entry, 389 373 pmu); 374 374 + if ((!pe->adev->df.funcs) || 375 375 + (!pe->adev->df.funcs->pmc_stop)) 376 376 + return; 390 377 391 378 amdgpu_perf_stop(event, PERF_EF_UPDATE); 392 379

+5

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

reviewed

··· 265 265 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 266 266 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 267 267 268 268 + if ((!adev->df.funcs) || 269 269 + (!adev->df.funcs->get_fica) || 270 270 + (!adev->df.funcs->set_fica)) 271 271 + return -EINVAL; 272 272 + 268 273 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 269 274 if (fica_out != 0x1f) 270 275 pr_err("xGMI error counters not enabled!\n");

+7 -4

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

reviewed

··· 1294 1294 if (!amdgpu_sriov_vf(adev) && 1295 1295 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1296 1296 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1297 1297 - if (adev->df.funcs->enable_ecc_force_par_wr_rmw) 1297 1297 + if (adev->df.funcs && 1298 1298 + adev->df.funcs->enable_ecc_force_par_wr_rmw) 1298 1299 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1299 1300 } 1300 1301 } ··· 1506 1505 chansize = 64; 1507 1506 else 1508 1507 chansize = 128; 1509 1509 - 1510 1510 - numchan = adev->df.funcs->get_hbm_channel_number(adev); 1511 1511 - adev->gmc.vram_width = numchan * chansize; 1508 1508 + if (adev->df.funcs && 1509 1509 + adev->df.funcs->get_hbm_channel_number) { 1510 1510 + numchan = adev->df.funcs->get_hbm_channel_number(adev); 1511 1511 + adev->gmc.vram_width = numchan * chansize; 1512 1512 + } 1512 1513 } 1513 1514 1514 1515 adev->gmc.vram_type = vram_type;

+7 -2

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 1238 1238 if (amdgpu_sriov_vf(adev)) 1239 1239 xgpu_ai_mailbox_add_irq_id(adev); 1240 1240 1241 1241 - adev->df.funcs->sw_init(adev); 1241 1241 + if (adev->df.funcs && 1242 1242 + adev->df.funcs->sw_init) 1243 1243 + adev->df.funcs->sw_init(adev); 1242 1244 1243 1245 return 0; 1244 1246 } ··· 1252 1250 if (adev->nbio.ras_funcs && 1253 1251 adev->nbio.ras_funcs->ras_fini) 1254 1252 adev->nbio.ras_funcs->ras_fini(adev); 1255 1255 - adev->df.funcs->sw_fini(adev); 1253 1253 + 1254 1254 + if (adev->df.funcs && 1255 1255 + adev->df.funcs->sw_fini) 1256 1256 + adev->df.funcs->sw_fini(adev); 1256 1257 return 0; 1257 1258 } 1258 1259