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drm/amdgpu/gfx12: add CU mask support for compute MQD initialization

Extend the GFX12 compute MQD initialization to support
Compute Unit (CU) masking for fine-grained resource allocation.
This allows compute queues to be limited to specific CUs for
performance isolation and debugging purposes.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jesse.Zhang and committed by
Alex Deucher cb9a5ff7 d68c4e48

+33
+33
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 3109 3109 return gfx_v12_0_cp_gfx_start(adev); 3110 3110 } 3111 3111 3112 + static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, 3113 + struct v12_compute_mqd *mqd, 3114 + struct amdgpu_mqd_prop *prop) 3115 + { 3116 + uint32_t se_mask[8] = {0}; 3117 + uint32_t wa_mask; 3118 + bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | 3119 + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); 3120 + 3121 + if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) 3122 + return; 3123 + 3124 + if (has_wa_flag) { 3125 + wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? 3126 + 0xffff : 0xffffffff; 3127 + mqd->compute_static_thread_mgmt_se0 = wa_mask; 3128 + mqd->compute_static_thread_mgmt_se1 = wa_mask; 3129 + mqd->compute_static_thread_mgmt_se2 = wa_mask; 3130 + mqd->compute_static_thread_mgmt_se3 = wa_mask; 3131 + return; 3132 + } 3133 + 3134 + amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, 3135 + prop->cu_mask_count, se_mask); 3136 + 3137 + mqd->compute_static_thread_mgmt_se0 = se_mask[0]; 3138 + mqd->compute_static_thread_mgmt_se1 = se_mask[1]; 3139 + mqd->compute_static_thread_mgmt_se2 = se_mask[2]; 3140 + mqd->compute_static_thread_mgmt_se3 = se_mask[3]; 3141 + } 3142 + 3112 3143 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 3113 3144 struct amdgpu_mqd_prop *prop) 3114 3145 { ··· 3273 3242 /* set UQ fenceaddress */ 3274 3243 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3275 3244 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3245 + /* set CU mask */ 3246 + gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop); 3276 3247 3277 3248 return 0; 3278 3249 }