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drm/amdgpu/gfx11: add CU mask support for compute MQD initialization

Extend the GFX11 compute MQD initialization to support
Compute Unit (CU) masking for fine-grained resource allocation.
This allows compute queues to be limited to specific CUs for
performance isolation and debugging purposes.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jesse.Zhang and committed by
Alex Deucher d68c4e48 0ea55604

+33
+33
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 4238 4238 return gfx_v11_0_cp_gfx_start(adev); 4239 4239 } 4240 4240 4241 + static void gfx_v11_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, 4242 + struct v11_compute_mqd *mqd, 4243 + struct amdgpu_mqd_prop *prop) 4244 + { 4245 + uint32_t se_mask[8] = {0}; 4246 + uint32_t wa_mask; 4247 + bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | 4248 + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); 4249 + 4250 + if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) 4251 + return; 4252 + 4253 + if (has_wa_flag) { 4254 + wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? 4255 + 0xffff : 0xffffffff; 4256 + mqd->compute_static_thread_mgmt_se0 = wa_mask; 4257 + mqd->compute_static_thread_mgmt_se1 = wa_mask; 4258 + mqd->compute_static_thread_mgmt_se2 = wa_mask; 4259 + mqd->compute_static_thread_mgmt_se3 = wa_mask; 4260 + return; 4261 + } 4262 + 4263 + amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, 4264 + prop->cu_mask_count, se_mask); 4265 + 4266 + mqd->compute_static_thread_mgmt_se0 = se_mask[0]; 4267 + mqd->compute_static_thread_mgmt_se1 = se_mask[1]; 4268 + mqd->compute_static_thread_mgmt_se2 = se_mask[2]; 4269 + mqd->compute_static_thread_mgmt_se3 = se_mask[3]; 4270 + } 4271 + 4241 4272 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 4242 4273 struct amdgpu_mqd_prop *prop) 4243 4274 { ··· 4403 4372 /* set UQ fenceaddress */ 4404 4373 mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4405 4374 mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4375 + /* set CU mask */ 4376 + gfx_v11_0_compute_mqd_set_cu_mask(adev, mqd, prop); 4406 4377 4407 4378 return 0; 4408 4379 }