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drm/i915/vga: Avoid VGA arbiter during intel_vga_disable() for iGPUs

Avoid using the VGA arbiter during intel_vga_get() for iGPUs because
that will clobber the VGA routing for whatever external GPU is the
current VGA device. That will cause all reads from VGA memory to
come back as 0xff/white, and thus we get a white rectangle on screen
when the external GPU switches from vgacon to fbcon.

The iGPU has the highest VGA decode priority so it will steal all
VGA register accesses whenever its IO decoding is enabled. We'll only
keep the IO decode enabled for a short time so hopefully we don't
end up eating too many unrelated VGA register accesses.

For discrete GPUs we need all the bridges to have their VGA forwarding
bits correctly configured so we can't really avoid the VGA arbiter
there. Although we only do this stuff on dGPUs when the VGA plane was
actaully enabled, so the dGPU should be the current VGA device
and thus have VGA routed to it already anyway.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251208182637.334-8-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>

+50 -4
+50 -4
drivers/gpu/drm/i915/display/intel_vga.c
··· 58 58 return DISPLAY_VER(display) < 7; 59 59 } 60 60 61 + static bool intel_pci_set_io_decode(struct pci_dev *pdev, bool enable) 62 + { 63 + u16 old = 0, cmd; 64 + 65 + pci_read_config_word(pdev, PCI_COMMAND, &old); 66 + cmd = old & ~PCI_COMMAND_IO; 67 + if (enable) 68 + cmd |= PCI_COMMAND_IO; 69 + pci_write_config_word(pdev, PCI_COMMAND, cmd); 70 + 71 + return old & PCI_COMMAND_IO; 72 + } 73 + 74 + static bool intel_vga_get(struct intel_display *display) 75 + { 76 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 77 + 78 + /* WaEnableVGAAccessThroughIOPort:ctg+ */ 79 + 80 + /* 81 + * Bypass the VGA arbiter on the iGPU and just enable 82 + * IO decode by hand. This avoids clobbering the VGA 83 + * routing for an external GPU when it's the current 84 + * VGA device, and thus prevents the all 0xff/white 85 + * readout from VGA memory when taking over from vgacon. 86 + * 87 + * The iGPU has the highest VGA decode priority so it will 88 + * grab any VGA IO access when IO decode is enabled, regardless 89 + * of how any other VGA routing bits are configured. 90 + */ 91 + if (display->platform.dgfx) 92 + vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 93 + 94 + return intel_pci_set_io_decode(pdev, true); 95 + } 96 + 97 + static void intel_vga_put(struct intel_display *display, bool io_decode) 98 + { 99 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 100 + 101 + /* see intel_vga_get() */ 102 + intel_pci_set_io_decode(pdev, io_decode); 103 + 104 + if (display->platform.dgfx) 105 + vga_put(pdev, VGA_RSRC_LEGACY_IO); 106 + } 107 + 61 108 /* Disable the VGA plane that we never use */ 62 109 void intel_vga_disable(struct intel_display *display) 63 110 { 64 - struct pci_dev *pdev = to_pci_dev(display->drm->dev); 65 111 i915_reg_t vga_reg = intel_vga_cntrl_reg(display); 112 + bool io_decode; 66 113 u8 msr, sr1; 67 114 u32 tmp; 68 115 ··· 153 106 goto reset_vgacntr; 154 107 } 155 108 156 - /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ 157 - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 109 + io_decode = intel_vga_get(display); 158 110 159 111 outb(0x01, VGA_SEQ_I); 160 112 sr1 = inb(VGA_SEQ_D); ··· 175 129 msr &= ~VGA_MIS_COLOR; 176 130 outb(msr, VGA_MIS_W); 177 131 178 - vga_put(pdev, VGA_RSRC_LEGACY_IO); 132 + intel_vga_put(display, io_decode); 179 133 180 134 udelay(300); 181 135