Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_urgent_for_v5.13_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Borislav Petkov:
"The three SEV commits are not really urgent material. But we figured
since getting them in now will avoid a huge amount of conflicts
between future SEV changes touching tip, the kvm and probably other
trees, sending them to you now would be best.
The idea is that the tip, kvm etc branches for 5.14 will all base
ontop of -rc2 and thus everything will be peachy. What is more, those
changes are purely mechanical and defines movement so they should be
fine to go now (famous last words).
Summary:
- Enable -Wundef for the compressed kernel build stage
- Reorganize SEV code to streamline and simplify future development"
* tag 'x86_urgent_for_v5.13_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/boot/compressed: Enable -Wundef
x86/msr: Rename MSR_K8_SYSCFG to MSR_AMD64_SYSCFG
x86/sev: Move GHCB MSR protocol and NAE definitions in a common header
x86/sev-es: Rename sev-es.{ch} to sev.{ch}
+123
-112
+1
-1
Documentation/virt/kvm/amd-memory-encryption.rst
+1
-1
Documentation/virt/kvm/amd-memory-encryption.rst
···
22
22
[ecx]:
23
23
Bits[31:0] Number of encrypted guests supported simultaneously
24
24
25
-
If support for SEV is present, MSR 0xc001_0010 (MSR_K8_SYSCFG) and MSR 0xc001_0015
25
+
If support for SEV is present, MSR 0xc001_0010 (MSR_AMD64_SYSCFG) and MSR 0xc001_0015
26
26
(MSR_K7_HWCR) can be used to determine if it can be enabled::
27
27
28
28
0xc001_0010:
+3
-3
Documentation/x86/amd-memory-encryption.rst
+3
-3
Documentation/x86/amd-memory-encryption.rst
···
53
53
system physical addresses, not guest physical
54
54
addresses)
55
55
56
-
If support for SME is present, MSR 0xc00100010 (MSR_K8_SYSCFG) can be used to
56
+
If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
57
57
determine if SME is enabled and/or to enable memory encryption::
58
58
59
59
0xc0010010:
···
79
79
The CPU supports SME (determined through CPUID instruction).
80
80
81
81
- Enabled:
82
-
Supported and bit 23 of MSR_K8_SYSCFG is set.
82
+
Supported and bit 23 of MSR_AMD64_SYSCFG is set.
83
83
84
84
- Active:
85
85
Supported, Enabled and the Linux kernel is actively applying
···
89
89
SME can also be enabled and activated in the BIOS. If SME is enabled and
90
90
activated in the BIOS, then all memory accesses will be encrypted and it will
91
91
not be necessary to activate the Linux memory encryption support. If the BIOS
92
-
merely enables SME (sets bit 23 of the MSR_K8_SYSCFG), then Linux can activate
92
+
merely enables SME (sets bit 23 of the MSR_AMD64_SYSCFG), then Linux can activate
93
93
memory encryption by default (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) or
94
94
by supplying mem_encrypt=on on the kernel command line. However, if BIOS does
95
95
not enable SME, then Linux will not be able to activate memory encryption, even
+4
-3
arch/x86/boot/compressed/Makefile
+4
-3
arch/x86/boot/compressed/Makefile
···
30
30
31
31
KBUILD_CFLAGS := -m$(BITS) -O2
32
32
KBUILD_CFLAGS += -fno-strict-aliasing -fPIE
33
+
KBUILD_CFLAGS += -Wundef
33
34
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
34
35
cflags-$(CONFIG_X86_32) := -march=i386
35
36
cflags-$(CONFIG_X86_64) := -mcmodel=small -mno-red-zone
···
49
48
KBUILD_CFLAGS += -include $(srctree)/include/linux/hidden.h
50
49
KBUILD_CFLAGS += $(CLANG_FLAGS)
51
50
52
-
# sev-es.c indirectly inludes inat-table.h which is generated during
51
+
# sev.c indirectly inludes inat-table.h which is generated during
53
52
# compilation and stored in $(objtree). Add the directory to the includes so
54
53
# that the compiler finds it even with out-of-tree builds (make O=/some/path).
55
-
CFLAGS_sev-es.o += -I$(objtree)/arch/x86/lib/
54
+
CFLAGS_sev.o += -I$(objtree)/arch/x86/lib/
56
55
57
56
KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__
58
57
GCOV_PROFILE := n
···
94
93
vmlinux-objs-y += $(obj)/idt_64.o $(obj)/idt_handlers_64.o
95
94
vmlinux-objs-y += $(obj)/mem_encrypt.o
96
95
vmlinux-objs-y += $(obj)/pgtable_64.o
97
-
vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/sev-es.o
96
+
vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/sev.o
98
97
endif
99
98
100
99
vmlinux-objs-$(CONFIG_ACPI) += $(obj)/acpi.o
+1
-1
arch/x86/boot/compressed/misc.c
+1
-1
arch/x86/boot/compressed/misc.c
+1
-1
arch/x86/boot/compressed/misc.h
+1
-1
arch/x86/boot/compressed/misc.h
+2
-2
arch/x86/boot/compressed/sev-es.c
arch/x86/boot/compressed/sev.c
+2
-2
arch/x86/boot/compressed/sev-es.c
arch/x86/boot/compressed/sev.c
···
13
13
#include "misc.h"
14
14
15
15
#include <asm/pgtable_types.h>
16
-
#include <asm/sev-es.h>
16
+
#include <asm/sev.h>
17
17
#include <asm/trapnr.h>
18
18
#include <asm/trap_pf.h>
19
19
#include <asm/msr-index.h>
···
117
117
#include "../../lib/insn.c"
118
118
119
119
/* Include code for early handlers */
120
-
#include "../../kernel/sev-es-shared.c"
120
+
#include "../../kernel/sev-shared.c"
121
121
122
122
static bool early_setup_sev_es(void)
123
123
{
+3
-3
arch/x86/include/asm/msr-index.h
+3
-3
arch/x86/include/asm/msr-index.h
···
537
537
/* K8 MSRs */
538
538
#define MSR_K8_TOP_MEM1 0xc001001a
539
539
#define MSR_K8_TOP_MEM2 0xc001001d
540
-
#define MSR_K8_SYSCFG 0xc0010010
541
-
#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23
542
-
#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
540
+
#define MSR_AMD64_SYSCFG 0xc0010010
541
+
#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
542
+
#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
543
543
#define MSR_K8_INT_PENDING_MSG 0xc0010055
544
544
/* C1E active bits in int pending message */
545
545
#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
+62
arch/x86/include/asm/sev-common.h
+62
arch/x86/include/asm/sev-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* AMD SEV header common between the guest and the hypervisor.
4
+
*
5
+
* Author: Brijesh Singh <brijesh.singh@amd.com>
6
+
*/
7
+
8
+
#ifndef __ASM_X86_SEV_COMMON_H
9
+
#define __ASM_X86_SEV_COMMON_H
10
+
11
+
#define GHCB_MSR_INFO_POS 0
12
+
#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1)
13
+
14
+
#define GHCB_MSR_SEV_INFO_RESP 0x001
15
+
#define GHCB_MSR_SEV_INFO_REQ 0x002
16
+
#define GHCB_MSR_VER_MAX_POS 48
17
+
#define GHCB_MSR_VER_MAX_MASK 0xffff
18
+
#define GHCB_MSR_VER_MIN_POS 32
19
+
#define GHCB_MSR_VER_MIN_MASK 0xffff
20
+
#define GHCB_MSR_CBIT_POS 24
21
+
#define GHCB_MSR_CBIT_MASK 0xff
22
+
#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
23
+
((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \
24
+
(((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \
25
+
(((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \
26
+
GHCB_MSR_SEV_INFO_RESP)
27
+
#define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
28
+
#define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK)
29
+
#define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK)
30
+
31
+
#define GHCB_MSR_CPUID_REQ 0x004
32
+
#define GHCB_MSR_CPUID_RESP 0x005
33
+
#define GHCB_MSR_CPUID_FUNC_POS 32
34
+
#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
35
+
#define GHCB_MSR_CPUID_VALUE_POS 32
36
+
#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
37
+
#define GHCB_MSR_CPUID_REG_POS 30
38
+
#define GHCB_MSR_CPUID_REG_MASK 0x3
39
+
#define GHCB_CPUID_REQ_EAX 0
40
+
#define GHCB_CPUID_REQ_EBX 1
41
+
#define GHCB_CPUID_REQ_ECX 2
42
+
#define GHCB_CPUID_REQ_EDX 3
43
+
#define GHCB_CPUID_REQ(fn, reg) \
44
+
(GHCB_MSR_CPUID_REQ | \
45
+
(((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \
46
+
(((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))
47
+
48
+
#define GHCB_MSR_TERM_REQ 0x100
49
+
#define GHCB_MSR_TERM_REASON_SET_POS 12
50
+
#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
51
+
#define GHCB_MSR_TERM_REASON_POS 16
52
+
#define GHCB_MSR_TERM_REASON_MASK 0xff
53
+
#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \
54
+
(((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \
55
+
((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS))
56
+
57
+
#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
58
+
#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
59
+
60
+
#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
61
+
62
+
#endif
+4
-26
arch/x86/include/asm/sev-es.h
arch/x86/include/asm/sev.h
+4
-26
arch/x86/include/asm/sev-es.h
arch/x86/include/asm/sev.h
···
10
10
11
11
#include <linux/types.h>
12
12
#include <asm/insn.h>
13
+
#include <asm/sev-common.h>
13
14
14
-
#define GHCB_SEV_INFO 0x001UL
15
-
#define GHCB_SEV_INFO_REQ 0x002UL
16
-
#define GHCB_INFO(v) ((v) & 0xfffUL)
17
-
#define GHCB_PROTO_MAX(v) (((v) >> 48) & 0xffffUL)
18
-
#define GHCB_PROTO_MIN(v) (((v) >> 32) & 0xffffUL)
19
-
#define GHCB_PROTO_OUR 0x0001UL
20
-
#define GHCB_SEV_CPUID_REQ 0x004UL
21
-
#define GHCB_CPUID_REQ_EAX 0
22
-
#define GHCB_CPUID_REQ_EBX 1
23
-
#define GHCB_CPUID_REQ_ECX 2
24
-
#define GHCB_CPUID_REQ_EDX 3
25
-
#define GHCB_CPUID_REQ(fn, reg) (GHCB_SEV_CPUID_REQ | \
26
-
(((unsigned long)reg & 3) << 30) | \
27
-
(((unsigned long)fn) << 32))
15
+
#define GHCB_PROTO_OUR 0x0001UL
16
+
#define GHCB_PROTOCOL_MAX 1ULL
17
+
#define GHCB_DEFAULT_USAGE 0ULL
28
18
29
-
#define GHCB_PROTOCOL_MAX 0x0001UL
30
-
#define GHCB_DEFAULT_USAGE 0x0000UL
31
-
32
-
#define GHCB_SEV_CPUID_RESP 0x005UL
33
-
#define GHCB_SEV_TERMINATE 0x100UL
34
-
#define GHCB_SEV_TERMINATE_REASON(reason_set, reason_val) \
35
-
(((((u64)reason_set) & 0x7) << 12) | \
36
-
((((u64)reason_val) & 0xff) << 16))
37
-
#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
38
-
#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
39
-
40
-
#define GHCB_SEV_GHCB_RESP_CODE(v) ((v) & 0xfff)
41
19
#define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); }
42
20
43
21
enum es_result {
+3
-3
arch/x86/kernel/Makefile
+3
-3
arch/x86/kernel/Makefile
···
20
20
CFLAGS_REMOVE_ftrace.o = -pg
21
21
CFLAGS_REMOVE_early_printk.o = -pg
22
22
CFLAGS_REMOVE_head64.o = -pg
23
-
CFLAGS_REMOVE_sev-es.o = -pg
23
+
CFLAGS_REMOVE_sev.o = -pg
24
24
endif
25
25
26
26
KASAN_SANITIZE_head$(BITS).o := n
···
28
28
KASAN_SANITIZE_dumpstack_$(BITS).o := n
29
29
KASAN_SANITIZE_stacktrace.o := n
30
30
KASAN_SANITIZE_paravirt.o := n
31
-
KASAN_SANITIZE_sev-es.o := n
31
+
KASAN_SANITIZE_sev.o := n
32
32
33
33
# With some compiler versions the generated code results in boot hangs, caused
34
34
# by several compilation units. To be safe, disable all instrumentation.
···
148
148
obj-$(CONFIG_UNWINDER_FRAME_POINTER) += unwind_frame.o
149
149
obj-$(CONFIG_UNWINDER_GUESS) += unwind_guess.o
150
150
151
-
obj-$(CONFIG_AMD_MEM_ENCRYPT) += sev-es.o
151
+
obj-$(CONFIG_AMD_MEM_ENCRYPT) += sev.o
152
152
###
153
153
# 64 bit specific files
154
154
ifeq ($(CONFIG_X86_64),y)
+2
-2
arch/x86/kernel/cpu/amd.c
+2
-2
arch/x86/kernel/cpu/amd.c
···
593
593
*/
594
594
if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
595
595
/* Check if memory encryption is enabled */
596
-
rdmsrl(MSR_K8_SYSCFG, msr);
597
-
if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
596
+
rdmsrl(MSR_AMD64_SYSCFG, msr);
597
+
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
598
598
goto clear_all;
599
599
600
600
/*
+1
-1
arch/x86/kernel/cpu/mtrr/cleanup.c
+1
-1
arch/x86/kernel/cpu/mtrr/cleanup.c
···
836
836
if (boot_cpu_data.x86 < 0xf)
837
837
return 0;
838
838
/* In case some hypervisor doesn't pass SYSCFG through: */
839
-
if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
839
+
if (rdmsr_safe(MSR_AMD64_SYSCFG, &l, &h) < 0)
840
840
return 0;
841
841
/*
842
842
* Memory between 4GB and top of mem is forced WB by this magic bit.
+2
-2
arch/x86/kernel/cpu/mtrr/generic.c
+2
-2
arch/x86/kernel/cpu/mtrr/generic.c
···
53
53
(boot_cpu_data.x86 >= 0x0f)))
54
54
return;
55
55
56
-
rdmsr(MSR_K8_SYSCFG, lo, hi);
56
+
rdmsr(MSR_AMD64_SYSCFG, lo, hi);
57
57
if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
58
58
pr_err(FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
59
59
" not cleared by BIOS, clearing this bit\n",
60
60
smp_processor_id());
61
61
lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
62
-
mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
62
+
mtrr_wrmsr(MSR_AMD64_SYSCFG, lo, hi);
63
63
}
64
64
}
65
65
+1
-1
arch/x86/kernel/head64.c
+1
-1
arch/x86/kernel/head64.c
+1
-1
arch/x86/kernel/mmconf-fam10h_64.c
+1
-1
arch/x86/kernel/mmconf-fam10h_64.c
+1
-1
arch/x86/kernel/nmi.c
+1
-1
arch/x86/kernel/nmi.c
+2
-2
arch/x86/kernel/sev-es.c
arch/x86/kernel/sev.c
+2
-2
arch/x86/kernel/sev-es.c
arch/x86/kernel/sev.c
···
22
22
23
23
#include <asm/cpu_entry_area.h>
24
24
#include <asm/stacktrace.h>
25
-
#include <asm/sev-es.h>
25
+
#include <asm/sev.h>
26
26
#include <asm/insn-eval.h>
27
27
#include <asm/fpu/internal.h>
28
28
#include <asm/processor.h>
···
459
459
}
460
460
461
461
/* Include code shared with pre-decompression boot stage */
462
-
#include "sev-es-shared.c"
462
+
#include "sev-shared.c"
463
463
464
464
void noinstr __sev_es_nmi_complete(void)
465
465
{
+2
-2
arch/x86/kvm/svm/svm.c
+2
-2
arch/x86/kvm/svm/svm.c
···
863
863
return;
864
864
865
865
/* If memory encryption is not enabled, use existing mask */
866
-
rdmsrl(MSR_K8_SYSCFG, msr);
867
-
if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
866
+
rdmsrl(MSR_AMD64_SYSCFG, msr);
867
+
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
868
868
return;
869
869
870
870
enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
+3
-33
arch/x86/kvm/svm/svm.h
+3
-33
arch/x86/kvm/svm/svm.h
···
20
20
#include <linux/bits.h>
21
21
22
22
#include <asm/svm.h>
23
+
#include <asm/sev-common.h>
23
24
24
25
#define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
25
26
···
526
525
527
526
/* sev.c */
528
527
529
-
#define GHCB_VERSION_MAX 1ULL
530
-
#define GHCB_VERSION_MIN 1ULL
528
+
#define GHCB_VERSION_MAX 1ULL
529
+
#define GHCB_VERSION_MIN 1ULL
531
530
532
-
#define GHCB_MSR_INFO_POS 0
533
-
#define GHCB_MSR_INFO_MASK (BIT_ULL(12) - 1)
534
-
535
-
#define GHCB_MSR_SEV_INFO_RESP 0x001
536
-
#define GHCB_MSR_SEV_INFO_REQ 0x002
537
-
#define GHCB_MSR_VER_MAX_POS 48
538
-
#define GHCB_MSR_VER_MAX_MASK 0xffff
539
-
#define GHCB_MSR_VER_MIN_POS 32
540
-
#define GHCB_MSR_VER_MIN_MASK 0xffff
541
-
#define GHCB_MSR_CBIT_POS 24
542
-
#define GHCB_MSR_CBIT_MASK 0xff
543
-
#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
544
-
((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \
545
-
(((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \
546
-
(((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \
547
-
GHCB_MSR_SEV_INFO_RESP)
548
-
549
-
#define GHCB_MSR_CPUID_REQ 0x004
550
-
#define GHCB_MSR_CPUID_RESP 0x005
551
-
#define GHCB_MSR_CPUID_FUNC_POS 32
552
-
#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
553
-
#define GHCB_MSR_CPUID_VALUE_POS 32
554
-
#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
555
-
#define GHCB_MSR_CPUID_REG_POS 30
556
-
#define GHCB_MSR_CPUID_REG_MASK 0x3
557
-
558
-
#define GHCB_MSR_TERM_REQ 0x100
559
-
#define GHCB_MSR_TERM_REASON_SET_POS 12
560
-
#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
561
-
#define GHCB_MSR_TERM_REASON_POS 16
562
-
#define GHCB_MSR_TERM_REASON_MASK 0xff
563
531
564
532
extern unsigned int max_sev_asid;
565
533
+1
-1
arch/x86/kvm/x86.c
+1
-1
arch/x86/kvm/x86.c
+1
-1
arch/x86/mm/extable.c
+1
-1
arch/x86/mm/extable.c
+3
-3
arch/x86/mm/mem_encrypt_identity.c
+3
-3
arch/x86/mm/mem_encrypt_identity.c
···
529
529
/*
530
530
* No SME if Hypervisor bit is set. This check is here to
531
531
* prevent a guest from trying to enable SME. For running as a
532
-
* KVM guest the MSR_K8_SYSCFG will be sufficient, but there
532
+
* KVM guest the MSR_AMD64_SYSCFG will be sufficient, but there
533
533
* might be other hypervisors which emulate that MSR as non-zero
534
534
* or even pass it through to the guest.
535
535
* A malicious hypervisor can still trick a guest into this
···
542
542
return;
543
543
544
544
/* For SME, check the SYSCFG MSR */
545
-
msr = __rdmsr(MSR_K8_SYSCFG);
546
-
if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
545
+
msr = __rdmsr(MSR_AMD64_SYSCFG);
546
+
if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
547
547
return;
548
548
} else {
549
549
/* SEV state cannot be controlled by a command line option */
+1
-1
arch/x86/pci/amd_bus.c
+1
-1
arch/x86/pci/amd_bus.c
+1
-1
arch/x86/platform/efi/efi_64.c
+1
-1
arch/x86/platform/efi/efi_64.c
+1
-1
arch/x86/realmode/init.c
+1
-1
arch/x86/realmode/init.c
+2
-2
arch/x86/realmode/rm/trampoline_64.S
+2
-2
arch/x86/realmode/rm/trampoline_64.S
+1
-1
drivers/edac/amd64_edac.c
+1
-1
drivers/edac/amd64_edac.c
···
3083
3083
edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
3084
3084
3085
3085
/* Check first whether TOP_MEM2 is enabled: */
3086
-
rdmsrl(MSR_K8_SYSCFG, msr_val);
3086
+
rdmsrl(MSR_AMD64_SYSCFG, msr_val);
3087
3087
if (msr_val & BIT(21)) {
3088
3088
rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
3089
3089
edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
+3
-3
tools/arch/x86/include/asm/msr-index.h
+3
-3
tools/arch/x86/include/asm/msr-index.h
···
537
537
/* K8 MSRs */
538
538
#define MSR_K8_TOP_MEM1 0xc001001a
539
539
#define MSR_K8_TOP_MEM2 0xc001001d
540
-
#define MSR_K8_SYSCFG 0xc0010010
541
-
#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23
542
-
#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
540
+
#define MSR_AMD64_SYSCFG 0xc0010010
541
+
#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
542
+
#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
543
543
#define MSR_K8_INT_PENDING_MSG 0xc0010055
544
544
/* C1E active bits in int pending message */
545
545
#define K8_INTP_C1E_ACTIVE_MASK 0x18000000