Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Add read backlight interface
[Why & How]
Add read backlight interface to get ABM data.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Yongqiang Sun
and committed by
Alex Deucher
ccc87505
6ee90e88
+18
-4
+1
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+1
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+11
-1
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+11
-1
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
···
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SR(BL1_PWM_USER_LEVEL), \
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SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
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SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
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+
SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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SR(DC_ABM1_ACE_THRES_12), \
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SR(BIOS_SCRATCH_2)
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#define ABM_DCN10_REG_LIST(id)\
···
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define ABM_DCN20_REG_LIST() \
···
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SR(BL1_PWM_USER_LEVEL), \
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SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
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SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
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SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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SR(DC_ABM1_ACE_THRES_12), \
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NBIO_SR(BIOS_SCRATCH_2)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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-
#define ABM_DCN301_REG_LIST(id)\
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#define ABM_DCN30_REG_LIST(id)\
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ABM_COMMON_REG_LIST_DCE_BASE(), \
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SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
···
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SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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NBIO_SR(BIOS_SCRATCH_2)
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#endif
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···
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uint32_t BL1_PWM_USER_LEVEL;
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uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
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uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
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uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
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uint32_t DC_ABM1_ACE_THRES_12;
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uint32_t MASTER_COMM_CNTL_REG;
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uint32_t MASTER_COMM_CMD_REG;
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uint32_t MASTER_COMM_DATA_REG1;
+4
-2
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+4
-2
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
···
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#define FN(reg_name, field_name) \
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dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
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static unsigned int calculate_16_bit_backlight_from_pwm(struct dce_panel_cntl *dce_panel_cntl)
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static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
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{
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uint64_t current_backlight;
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uint32_t round_result;
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uint32_t pwm_period_cntl, bl_period, bl_int_count;
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uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
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uint32_t bl_period_mask, bl_pwm_mask;
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
···
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REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_LOCK, 0);
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-
current_backlight = calculate_16_bit_backlight_from_pwm(dce_panel_cntl);
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current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
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return current_backlight;
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}
···
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.is_panel_powered_on = dce_is_panel_powered_on,
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.store_backlight_level = dce_store_backlight_level,
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.driver_set_backlight = dce_driver_set_backlight,
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.get_current_backlight = dce_get_16_bit_backlight_from_pwm,
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};
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void dce_panel_cntl_construct(
+1
-1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+1
drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h
+1
drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h