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dt-bindings: phy: Add Sophgo CV1800 USB phy

The USB phy of Sophgo CV18XX series SoC needs to sense a pin called
"VBUS_DET" to get the right operation mode. If this pin is not
connected, it only supports setting the mode manually.

Add USB phy bindings for Sophgo CV18XX/SG200X series SoC.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250708063038.497473-2-inochiama@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Inochi Amaoto and committed by
Vinod Koul cdb2511b 2c27aaee

+54
+54
Documentation/devicetree/bindings/phy/sophgo,cv1800b-usb2-phy.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/sophgo,cv1800b-usb2-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Sophgo CV18XX/SG200X USB 2.0 PHY 8 + 9 + maintainers: 10 + - Inochi Amaoto <inochiama@gmail.com> 11 + 12 + properties: 13 + compatible: 14 + const: sophgo,cv1800b-usb2-phy 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + "#phy-cells": 20 + const: 0 21 + 22 + clocks: 23 + items: 24 + - description: PHY app clock 25 + - description: PHY stb clock 26 + - description: PHY lpm clock 27 + 28 + clock-names: 29 + items: 30 + - const: app 31 + - const: stb 32 + - const: lpm 33 + 34 + resets: 35 + maxItems: 1 36 + 37 + required: 38 + - compatible 39 + - "#phy-cells" 40 + - clocks 41 + - clock-names 42 + 43 + additionalProperties: false 44 + 45 + examples: 46 + - | 47 + phy@48 { 48 + compatible = "sophgo,cv1800b-usb2-phy"; 49 + reg = <0x48 0x4>; 50 + #phy-cells = <0>; 51 + clocks = <&clk 93>, <&clk 94>, <&clk 95>; 52 + clock-names = "app", "stb", "lpm"; 53 + resets = <&rst 58>; 54 + };