tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'imx-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree changes for 6.13:

- New device support: Boundary Device Nitrogen8MP, Kontron OSM-S i.MX8MP
SoM and BL carrier board, Verdin Ivy carrier board, DHCOM SoM on DRC02
and PicoITX, Gateworks GW82XX-2X, etc.
- A series from Carlos Song to add LPSPI alias for i.MX8 and i.MX9 SoCs
- A couple of changes from Ciprian Marian Costea to improve S32G uSDHC
and SD/eMMC support
- A couple of changes from Francesco Dolcini to improve SD regulator
startup delay for Verdin devices
- A bunch of changes from Frank Li to add I3C overlay for imx93-9x9-qsb,
enable PCIe and SATA for imx8qm-mek, add various devices for imx8qxp-mek,
fix dt-schema warnings, etc.
- A series from João Paulo Gonçalves to improve i.MX8 Apalis and i.MX8M
Verdin board support
- A set of changes from Laurentiu Mihalcea to enable dsp node for rproc
usage in audio subsystem
- A set of changes from Peng Fan to improve i.MX95 support, adding SCMI,
thermal zone, cooling device, idle states, etc.
- A series from Richard Zhu to add PCIe and SATA support for imx8dxl-evk
- A series from Shengjiu Wang to enable audio features on imx93-9x9-qsb
and imx8ulp-evk board
- Other small and random changes

* tag 'imx-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (92 commits)
arm64: dts: freescale: imx8mp-verdin: Fix SD regulator startup delay
arm64: dts: freescale: imx8mm-verdin: Fix SD regulator startup delay
arm64: dts: imx8mp-verdin: add single-master property to all i2c nodes
arm64: dts: imx8mm-verdin: add single-master property to all i2c nodes
arm64: dts: imx95: Add missing vendor string to SCMI property
arm64: dts: imx8mp-navqp: Add HDMI support
arm64: dts: imx8qm-ss-hsio: fix PCI and SATA clock indices
arm64: dts: imx8qm-ss-hsio: fix interrupt-map indent under pci* nodes
arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0
arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and output-high in GPIO
arm64: dts: layerscape: remove en25s64 and only keep jedec,spi-nor compatible string
arm64: dts: imx8mp-kontron-dl: change touchscreen power-supply to AVDD28-supply
arm64: dts: imx8mp: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board
arm64: dts: imx8: move samsung,burst-clock-frequency to imx8mn and imx8mm mba8mx board file
arm64: dts: mba8mx: remove undocumented 'data-lanes' at panel
arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support
arm64: dts: imx8ulp-evk: Add spdif sound card support
arm64: dts: imx8ulp-evk: Add bt-sco sound card support
arm64: dts: imx8ulp: Add audio device nodes
arm64: dts: imx8qm-mek: enable dsp node for rproc usage
...

Link: https://lore.kernel.org/r/20241104090055.1881860-5-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann cdc9f8bd 430851a9

+8095 -109
+25
arch/arm64/boot/dts/freescale/Makefile
··· 136 136 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb 137 137 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb 138 138 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb 139 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb 139 140 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb 140 141 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb 141 142 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb 142 143 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb 144 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb 143 145 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb 144 146 dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb 145 147 ··· 169 167 dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb 170 168 dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb 171 169 dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb 170 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb 172 171 dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb 173 172 dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb 173 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb 174 174 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb 175 175 dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb 176 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb 177 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb 178 + 179 + imx8mp-kontron-dl-dtbs += imx8mp-kontron-bl-osm-s.dtb imx8mp-kontron-dl.dtbo 180 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb 181 + 182 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb 176 183 dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb 177 184 dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb 185 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb 178 186 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb 179 187 imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo 180 188 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb ··· 199 187 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb 200 188 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb 201 189 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb 190 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb 202 191 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb 203 192 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb 193 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-ivy.dtb 204 194 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb 205 195 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb 206 196 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb 207 197 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb 198 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb 208 199 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb 209 200 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb 210 201 211 202 imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo 203 + imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo 212 204 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb 205 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb 213 206 214 207 imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo 215 208 imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo ··· 257 240 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb 258 241 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb 259 242 dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb 243 + 244 + imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo 245 + dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb 246 + 260 247 dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb 261 248 dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb 262 249 dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb ··· 269 248 dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb 270 249 dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb 271 250 dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb 251 + 252 + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo 253 + 254 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb 272 255 273 256 imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo 274 257 imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
··· 87 87 flash@2 { 88 88 #address-cells = <1>; 89 89 #size-cells = <1>; 90 - compatible = "en25s64", "jedec,spi-nor"; 90 + compatible = "jedec,spi-nor"; 91 91 spi-cpol; 92 92 spi-cpha; 93 93 reg = <2>;
-2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
··· 19 19 20 20 pwm-fan { 21 21 compatible = "pwm-fan"; 22 - cooling-min-state = <0>; 23 - cooling-max-state = <3>; 24 22 #cooling-cells = <2>; 25 23 pwms = <&sl28cpld_pwm0 0 4000000>; 26 24 cooling-levels = <1 128 192 255>;
+1 -1
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
··· 69 69 flash@2 { 70 70 #address-cells = <1>; 71 71 #size-cells = <1>; 72 - compatible = "en25s64", "jedec,spi-nor"; 72 + compatible = "jedec,spi-nor"; 73 73 spi-cpol; 74 74 spi-cpha; 75 75 reg = <2>;
-3
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
··· 94 94 fan-temperature-ctrlr@18 { 95 95 compatible = "ti,amc6821"; 96 96 reg = <0x18>; 97 - cooling-min-state = <0>; 98 - cooling-max-state = <9>; 99 - #cooling-cells = <2>; 100 97 }; 101 98 }; 102 99
+169
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + // 3 + // Device Tree file for LX2160 REV2 4 + // 5 + // Copyright 2025 NXP 6 + 7 + /dts-v1/; 8 + 9 + #include "fsl-lx2160a.dtsi" 10 + 11 + &pcie1 { 12 + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; 13 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 14 + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 15 + reg-names = "regs", "config"; 16 + 17 + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 18 + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; 19 + 20 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 21 + interrupt-names = "intr"; 22 + 23 + /delete-property/ apio-wins; 24 + /delete-property/ ppio-wins; 25 + }; 26 + 27 + &pcie2 { 28 + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; 29 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 30 + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 31 + reg-names = "regs", "config"; 32 + 33 + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 34 + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; 35 + 36 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 37 + interrupt-names = "intr"; 38 + 39 + /delete-property/ apio-wins; 40 + /delete-property/ ppio-wins; 41 + }; 42 + 43 + &pcie3 { 44 + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; 45 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 46 + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 47 + reg-names = "regs", "config"; 48 + 49 + ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000 50 + 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; 51 + 52 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 53 + interrupt-names = "intr"; 54 + 55 + /delete-property/ apio-wins; 56 + /delete-property/ ppio-wins; 57 + }; 58 + 59 + 60 + &pcie4 { 61 + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; 62 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 63 + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 64 + reg-names = "regs", "config"; 65 + 66 + ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000 67 + 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; 68 + 69 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 70 + interrupt-names = "intr"; 71 + 72 + /delete-property/ apio-wins; 73 + /delete-property/ ppio-wins; 74 + }; 75 + 76 + &pcie5 { 77 + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; 78 + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 79 + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 80 + reg-names = "regs", "config"; 81 + 82 + ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000 83 + 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; 84 + 85 + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 86 + interrupt-names = "intr"; 87 + 88 + /delete-property/ apio-wins; 89 + /delete-property/ ppio-wins; 90 + }; 91 + 92 + &pcie6 { 93 + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; 94 + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 95 + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 96 + reg-names = "regs", "config"; 97 + 98 + ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000 99 + 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; 100 + 101 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 102 + interrupt-names = "intr"; 103 + 104 + /delete-property/ apio-wins; 105 + /delete-property/ ppio-wins; 106 + }; 107 + 108 + &soc { 109 + pcie_ep1: pcie-ep@3400000 { 110 + compatible = "fsl,lx2160ar2-pcie-ep"; 111 + reg = <0x00 0x03400000 0x0 0x00100000 112 + 0x80 0x00000000 0x8 0x00000000>; 113 + reg-names = "regs", "addr_space"; 114 + num-ob-windows = <8>; 115 + num-ib-windows = <8>; 116 + status = "disabled"; 117 + }; 118 + 119 + pcie_ep2: pcie-ep@3500000 { 120 + compatible = "fsl,lx2160ar2-pcie-ep"; 121 + reg = <0x00 0x03500000 0x0 0x00100000 122 + 0x88 0x00000000 0x8 0x00000000>; 123 + reg-names = "regs", "addr_space"; 124 + num-ob-windows = <8>; 125 + num-ib-windows = <8>; 126 + status = "disabled"; 127 + }; 128 + 129 + pcie_ep3: pcie-ep@3600000 { 130 + compatible = "fsl,lx2160ar2-pcie-ep"; 131 + reg = <0x00 0x03600000 0x0 0x00100000 132 + 0x90 0x00000000 0x8 0x00000000>; 133 + reg-names = "regs", "addr_space"; 134 + num-ob-windows = <256>; 135 + num-ib-windows = <24>; 136 + status = "disabled"; 137 + }; 138 + 139 + pcie_ep4: pcie-ep@3700000 { 140 + compatible = "fsl,lx2160ar2-pcie-ep"; 141 + reg = <0x00 0x03700000 0x0 0x00100000 142 + 0x98 0x00000000 0x8 0x00000000>; 143 + reg-names = "regs", "addr_space"; 144 + num-ob-windows = <8>; 145 + num-ib-windows = <8>; 146 + status = "disabled"; 147 + }; 148 + 149 + 150 + pcie_ep5: pcie-ep@3800000 { 151 + compatible = "fsl,lx2160ar2-pcie-ep"; 152 + reg = <0x00 0x03800000 0x0 0x00100000 153 + 0xa0 0x00000000 0x8 0x00000000>; 154 + reg-names = "regs", "addr_space"; 155 + num-ob-windows = <256>; 156 + num-ib-windows = <24>; 157 + status = "disabled"; 158 + }; 159 + 160 + pcie_ep6: pcie-ep@3900000 { 161 + compatible = "fsl,lx2160ar2-pcie-ep"; 162 + reg = <0x00 0x03900000 0x0 0x00100000 163 + 0xa8 0x00000000 0x8 0x00000000>; 164 + reg-names = "regs", "addr_space"; 165 + num-ob-windows = <8>; 166 + num-ib-windows = <8>; 167 + status = "disabled"; 168 + }; 169 + };
+1 -1
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
··· 614 614 }; 615 615 }; 616 616 617 - soc { 617 + soc: soc { 618 618 compatible = "simple-bus"; 619 619 #address-cells = <2>; 620 620 #size-cells = <2>;
+69
arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi
··· 51 51 regulator-name = "5V_SW_CAN2"; 52 52 startup-delay-us = <10000>; 53 53 }; 54 + 55 + sound-carrier { 56 + compatible = "simple-audio-card"; 57 + simple-audio-card,bitclock-master = <&codec_dai>; 58 + simple-audio-card,format = "i2s"; 59 + simple-audio-card,frame-master = <&codec_dai>; 60 + simple-audio-card,name = "apalis-nau8822"; 61 + simple-audio-card,routing = 62 + "Headphones", "LHP", 63 + "Headphones", "RHP", 64 + "Speaker", "LSPK", 65 + "Speaker", "RSPK", 66 + "Line Out", "AUXOUT1", 67 + "Line Out", "AUXOUT2", 68 + "LAUX", "Line In", 69 + "RAUX", "Line In", 70 + "LMICP", "Mic In", 71 + "RMICP", "Mic In"; 72 + simple-audio-card,widgets = 73 + "Headphones", "Headphones", 74 + "Line Out", "Line Out", 75 + "Speaker", "Speaker", 76 + "Microphone", "Mic In", 77 + "Line", "Line In"; 78 + 79 + codec_dai: simple-audio-card,codec { 80 + sound-dai = <&nau8822_1a>; 81 + system-clock-frequency = <12288000>; 82 + }; 83 + 84 + simple-audio-card,cpu { 85 + sound-dai = <&sai0>; 86 + }; 87 + }; 54 88 }; 55 89 56 90 /* Apalis CAN1 */ ··· 103 69 &i2c2 { 104 70 status = "okay"; 105 71 72 + /* Audio Codec */ 73 + nau8822_1a: audio-codec@1a { 74 + compatible = "nuvoton,nau8822"; 75 + reg = <0x1a>; 76 + #sound-dai-cells = <0>; 77 + }; 78 + 106 79 /* Power/Current Measurement Sensor */ 107 80 hwmon@40 { 108 81 compatible = "ti,ina219"; ··· 126 85 compatible = "st,24c02", "atmel,24c02"; 127 86 reg = <0x57>; 128 87 }; 88 + }; 89 + 90 + &sai0 { 91 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 92 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 93 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 94 + <&sai0_lpcg IMX_LPCG_CLK_0>; 95 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 96 + pinctrl-names = "default"; 97 + pinctrl-0 = <&pinctrl_sai0>; 98 + #sound-dai-cells = <0>; 99 + status = "okay"; 129 100 }; 130 101 131 102 /* Apalis MMC1 */ ··· 158 105 }; 159 106 160 107 &iomuxc { 108 + pinctrl-0 = <&pinctrl_cam1_gpios>, 109 + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, 110 + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>, 111 + <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, 112 + <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, 113 + <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, 114 + <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>, 115 + <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, 116 + <&pinctrl_usdhc1_gpios>; 161 117 162 118 pinctrl_enable_3v3_mmc: enable3v3mmcgrp { 163 119 fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148 */ ··· 182 120 183 121 pinctrl_enable_can2_power: enablecan2powergrp { 184 122 fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>; /* MXM3_156 */ 123 + }; 124 + 125 + pinctrl_sai0: sai0grp { 126 + fsl,pins = <IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0xc600006c>, /* MXM3_196 */ 127 + <IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0xc600004c>, /* MXM3_200 */ 128 + <IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0xc600004c>, /* MXM3_202 */ 129 + <IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0xc600004c>; /* MXM3_204 */ 185 130 }; 186 131 };
+25 -6
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
··· 22 22 status = "okay"; 23 23 }; 24 24 25 - /* TODO: Audio Mixer */ 25 + &amix { 26 + status = "okay"; 27 + }; 26 28 27 - /* TODO: Asynchronous Sample Rate Converter (ASRC) */ 29 + &asrc0 { 30 + status = "okay"; 31 + }; 28 32 29 33 /* TODO: Display Controller */ 30 34 ··· 108 104 109 105 /* TODO: Apalis BKL1_PWM */ 110 106 111 - /* TODO: Apalis DAP1 */ 107 + /* Apalis DAP1 */ 108 + &sai1 { 109 + status = "okay"; 110 + }; 112 111 113 - /* TODO: Apalis Analogue Audio */ 112 + &sai5 { 113 + status = "okay"; 114 + }; 115 + 116 + &sai5_lpcg { 117 + status = "okay"; 118 + }; 114 119 115 120 /* TODO: Apalis SATA1 */ 116 121 117 - /* TODO: Apalis SPDIF1 */ 122 + /* Apalis SPDIF1 */ 123 + &spdif0 { 124 + status = "okay"; 125 + }; 118 126 119 127 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 120 128 ··· 135 119 status = "okay"; 136 120 }; 137 121 138 - /* TODO: Apalis USBH4 SuperSpeed */ 122 + /* Apalis USBH4 SuperSpeed */ 123 + &usbotg3_cdns3 { 124 + status = "okay"; 125 + };
+25 -6
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
··· 62 62 status = "okay"; 63 63 }; 64 64 65 - /* TODO: Audio Mixer */ 65 + &amix { 66 + status = "okay"; 67 + }; 66 68 67 - /* TODO: Asynchronous Sample Rate Converter (ASRC) */ 69 + &asrc0 { 70 + status = "okay"; 71 + }; 68 72 69 73 /* TODO: Display Controller */ 70 74 ··· 195 191 196 192 /* TODO: Apalis BKL1_PWM */ 197 193 198 - /* TODO: Apalis DAP1 */ 194 + /* Apalis DAP1 */ 195 + &sai1 { 196 + status = "okay"; 197 + }; 199 198 200 - /* TODO: Apalis Analogue Audio */ 199 + &sai5 { 200 + status = "okay"; 201 + }; 202 + 203 + &sai5_lpcg { 204 + status = "okay"; 205 + }; 201 206 202 207 /* TODO: Apalis SATA1 */ 203 208 204 - /* TODO: Apalis SPDIF1 */ 209 + /* Apalis SPDIF1 */ 210 + &spdif0 { 211 + status = "okay"; 212 + }; 205 213 206 214 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 207 215 ··· 222 206 status = "okay"; 223 207 }; 224 208 225 - /* TODO: Apalis USBH4 SuperSpeed */ 209 + /* Apalis USBH4 SuperSpeed */ 210 + &usbotg3_cdns3 { 211 + status = "okay"; 212 + }; 226 213 227 214 /* Apalis MMC1 */ 228 215 &usdhc2 {
+25 -6
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
··· 94 94 status = "okay"; 95 95 }; 96 96 97 - /* TODO: Audio Mixer */ 97 + &amix { 98 + status = "okay"; 99 + }; 98 100 99 - /* TODO: Asynchronous Sample Rate Converter (ASRC) */ 101 + &asrc0 { 102 + status = "okay"; 103 + }; 100 104 101 105 /* TODO: Display Controller */ 102 106 ··· 244 240 245 241 /* TODO: Apalis BKL1_PWM */ 246 242 247 - /* TODO: Apalis DAP1 */ 243 + /* Apalis DAP1 */ 244 + &sai1 { 245 + status = "okay"; 246 + }; 248 247 249 - /* TODO: Apalis Analogue Audio */ 248 + &sai5 { 249 + status = "okay"; 250 + }; 251 + 252 + &sai5_lpcg { 253 + status = "okay"; 254 + }; 250 255 251 256 /* TODO: Apalis SATA1 */ 252 257 253 - /* TODO: Apalis SPDIF1 */ 258 + /* Apalis SPDIF1 */ 259 + &spdif0 { 260 + status = "okay"; 261 + }; 254 262 255 263 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 256 264 ··· 271 255 status = "okay"; 272 256 }; 273 257 274 - /* TODO: Apalis USBH4 SuperSpeed */ 258 + /* Apalis USBH4 SuperSpeed */ 259 + &usbotg3_cdns3 { 260 + status = "okay"; 261 + }; 275 262 276 263 /* Apalis MMC1 */ 277 264 &usdhc2 {
+126 -9
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
··· 126 126 regulator-name = "usb-phy-dummy"; 127 127 }; 128 128 129 + reg_vref_1v8: regulator-vref-1v8 { 130 + compatible = "regulator-fixed"; 131 + regulator-name = "+V1.8"; 132 + regulator-min-microvolt = <1800000>; 133 + regulator-max-microvolt = <1800000>; 134 + }; 135 + 129 136 reserved-memory { 130 137 #address-cells = <2>; 131 138 #size-cells = <2>; ··· 205 198 }; 206 199 }; 207 200 208 - /* TODO: Apalis Analogue Audio */ 201 + sound { 202 + compatible = "simple-audio-card"; 203 + simple-audio-card,bitclock-master = <&dailink_master>; 204 + simple-audio-card,format = "i2s"; 205 + simple-audio-card,frame-master = <&dailink_master>; 206 + simple-audio-card,name = "apalis-imx8qm"; 207 + 208 + simple-audio-card,cpu { 209 + sound-dai = <&sai1>; 210 + }; 211 + 212 + dailink_master: simple-audio-card,codec { 213 + sound-dai = <&sgtl5000>; 214 + }; 215 + }; 209 216 210 217 /* TODO: HDMI Audio */ 211 218 212 - /* TODO: Apalis SPDIF1 */ 219 + /* Apalis SPDIF1 */ 220 + sound-spdif { 221 + compatible = "fsl,imx-audio-spdif"; 222 + model = "imx-spdif"; 223 + spdif-controller = <&spdif0>; 224 + spdif-in; 225 + spdif-out; 226 + }; 213 227 214 228 touchscreen: touchscreen { 215 229 compatible = "toradex,vf50-touchscreen"; ··· 255 227 256 228 }; 257 229 230 + &asrc0 { 231 + fsl,asrc-rate = <48000>; 232 + }; 233 + 258 234 &adc0 { 259 235 pinctrl-names = "default"; 260 236 pinctrl-0 = <&pinctrl_adc0>; ··· 270 238 }; 271 239 272 240 /* TODO: Asynchronous Sample Rate Converter (ASRC) */ 241 + 242 + &cpu_alert0 { 243 + temperature = <95000>; 244 + }; 245 + 246 + &cpu_alert1 { 247 + temperature = <95000>; 248 + }; 249 + 250 + &cpu_crit0 { 251 + temperature = <105000>; 252 + }; 253 + 254 + &cpu_crit1 { 255 + temperature = <105000>; 256 + }; 257 + 258 + &drc_alert0 { 259 + temperature = <95000>; 260 + }; 261 + 262 + &drc_crit0 { 263 + temperature = <105000>; 264 + }; 273 265 274 266 /* Apalis ETH1 */ 275 267 &fec1 { ··· 341 285 342 286 /* TODO: Apalis HDMI1 */ 343 287 288 + &gpu_alert0 { 289 + temperature = <95000>; 290 + }; 291 + 292 + &gpu_alert1 { 293 + temperature = <95000>; 294 + }; 295 + 296 + &gpu_crit0 { 297 + temperature = <105000>; 298 + }; 299 + 300 + &gpu_crit1 { 301 + temperature = <105000>; 302 + }; 303 + 344 304 /* On-module I2C */ 345 305 &i2c1 { 346 306 pinctrl-names = "default"; ··· 365 293 #size-cells = <0>; 366 294 clock-frequency = <100000>; 367 295 status = "okay"; 368 - 369 - /* TODO: Audio Codec */ 370 296 371 297 /* USB3503A */ 372 298 usb-hub@8 { ··· 377 307 intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; 378 308 refclk-frequency = <25000000>; 379 309 reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; 310 + }; 311 + 312 + /* On Module Audio Codec */ 313 + sgtl5000: audio-codec@a { 314 + compatible = "fsl,sgtl5000"; 315 + reg = <0x0a>; 316 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 317 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 318 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 319 + <&mclkout0_lpcg IMX_LPCG_CLK_0>; 320 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 321 + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 322 + pinctrl-names = "default"; 323 + pinctrl-0 = <&pinctrl_sgtl5000>; 324 + #sound-dai-cells = <0>; 325 + VDDA-supply = <&reg_module_3v3_avdd>; 326 + VDDD-supply = <&reg_vref_1v8>; 327 + VDDIO-supply = <&reg_module_3v3>; 380 328 }; 381 329 }; 382 330 ··· 777 689 778 690 /* TODO: Apalis BKL1_PWM */ 779 691 780 - /* TODO: Apalis DAP1 */ 781 - 782 - /* TODO: Analogue Audio */ 692 + /* Apalis DAP1 */ 693 + &sai1 { 694 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 695 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 696 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 697 + <&sai1_lpcg IMX_LPCG_CLK_0>; 698 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 699 + pinctrl-names = "default"; 700 + pinctrl-0 = <&pinctrl_sai1>; 701 + #sound-dai-cells = <0>; 702 + status = "okay"; 703 + }; 783 704 784 705 /* TODO: Apalis SATA1 */ 785 706 786 - /* TODO: Apalis SPDIF1 */ 707 + /* Apalis SPDIF1 */ 708 + &spdif0 { 709 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 710 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 711 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; 712 + assigned-clock-rates = <786432000>, <49152000>, <12288000>; 713 + pinctrl-names = "default"; 714 + pinctrl-0 = <&pinctrl_spdif0>; 715 + status = "okay"; 716 + }; 787 717 788 718 /* TODO: Thermal Zones */ 789 719 790 720 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 791 721 792 - /* TODO: Apalis USBH4 */ 722 + /* Apalis USBH4 */ 723 + &usb3_phy { 724 + status = "okay"; 725 + }; 726 + 727 + &usbotg3 { 728 + status = "okay"; 729 + }; 730 + 731 + &usbotg3_cdns3 { 732 + dr_mode = "host"; 733 + }; 793 734 794 735 /* Apalis USBO1 */ 795 736 &usbphy1 {
+8 -11
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
··· 431 431 }; 432 432 433 433 dsp: dsp@596e8000 { 434 - compatible = "fsl,imx8qxp-dsp"; 434 + compatible = "fsl,imx8qxp-hifi4"; 435 435 reg = <0x596e8000 0x88000>; 436 436 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 437 437 <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 438 438 <&dsp_lpcg IMX_LPCG_CLK_7>; 439 439 clock-names = "ipg", "ocram", "core"; 440 - power-domains = <&pd IMX_SC_R_MU_13A>, 441 - <&pd IMX_SC_R_MU_13B>, 442 - <&pd IMX_SC_R_DSP>, 443 - <&pd IMX_SC_R_DSP_RAM>; 444 - mbox-names = "txdb0", "txdb1", 445 - "rxdb0", "rxdb1"; 446 - mboxes = <&lsio_mu13 2 0>, 447 - <&lsio_mu13 2 1>, 448 - <&lsio_mu13 3 0>, 449 - <&lsio_mu13 3 1>; 440 + power-domains = <&pd IMX_SC_R_MU_13B>, 441 + <&pd IMX_SC_R_MU_2A>; 442 + mbox-names = "tx", "rx", "rxdb"; 443 + mboxes = <&lsio_mu13 0 0>, 444 + <&lsio_mu13 1 0>, 445 + <&lsio_mu13 3 0>; 446 + firmware-name = "imx/dsp/hifi4.bin"; 450 447 status = "disabled"; 451 448 }; 452 449
+1 -1
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
··· 350 350 power-domains = <&pd IMX_SC_R_NAND>; 351 351 }; 352 352 353 - gpmi: nand-controller@5b812000{ 353 + gpmi: nand-controller@5b812000 { 354 354 compatible = "fsl,imx8qxp-gpmi-nand"; 355 355 reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; 356 356 reg-names = "gpmi-nand", "bch";
+123
arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright 2024 NXP 4 + * 5 + * Richard Zhu <hongxing.zhu@nxp.com> 6 + */ 7 + #include <dt-bindings/phy/phy.h> 8 + 9 + hsio_axi_clk: clock-hsio-axi { 10 + compatible = "fixed-clock"; 11 + #clock-cells = <0>; 12 + clock-frequency = <400000000>; 13 + clock-output-names = "hsio_axi_clk"; 14 + }; 15 + 16 + hsio_per_clk: clock-hsio-per { 17 + compatible = "fixed-clock"; 18 + #clock-cells = <0>; 19 + clock-frequency = <133333333>; 20 + clock-output-names = "hsio_per_clk"; 21 + }; 22 + 23 + hsio_refa_clk: clock-hsio-refa { 24 + compatible = "gpio-gate-clock"; 25 + clocks = <&xtal100m>; 26 + #clock-cells = <0>; 27 + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; 28 + }; 29 + 30 + hsio_refb_clk: clock-hsio-refb { 31 + compatible = "gpio-gate-clock"; 32 + clocks = <&xtal100m>; 33 + #clock-cells = <0>; 34 + enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; 35 + }; 36 + 37 + xtal100m: clock-xtal100m { 38 + compatible = "fixed-clock"; 39 + #clock-cells = <0>; 40 + clock-frequency = <100000000>; 41 + clock-output-names = "xtal_100MHz"; 42 + }; 43 + 44 + hsio_subsys: bus@5f000000 { 45 + compatible = "simple-bus"; 46 + ranges = <0x5f000000 0x0 0x5f000000 0x01000000>, 47 + <0x80000000 0x0 0x70000000 0x10000000>; 48 + #address-cells = <1>; 49 + #size-cells = <1>; 50 + dma-ranges = <0x80000000 0 0x80000000 0x80000000>; 51 + 52 + pcieb: pcie@5f010000 { 53 + compatible = "fsl,imx8q-pcie"; 54 + reg = <0x5f010000 0x10000>, 55 + <0x8ff00000 0x80000>; 56 + reg-names = "dbi", "config"; 57 + ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, 58 + <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; 59 + #interrupt-cells = <1>; 60 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 61 + interrupt-names = "msi"; 62 + #address-cells = <3>; 63 + #size-cells = <2>; 64 + clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, 65 + <&pcieb_lpcg IMX_LPCG_CLK_4>, 66 + <&pcieb_lpcg IMX_LPCG_CLK_5>; 67 + clock-names = "dbi", "mstr", "slv"; 68 + bus-range = <0x00 0xff>; 69 + device_type = "pci"; 70 + interrupt-map = <0 0 0 1 &gic 0 105 4>, 71 + <0 0 0 2 &gic 0 106 4>, 72 + <0 0 0 3 &gic 0 107 4>, 73 + <0 0 0 4 &gic 0 108 4>; 74 + interrupt-map-mask = <0 0 0 0x7>; 75 + num-lanes = <1>; 76 + num-viewport = <4>; 77 + power-domains = <&pd IMX_SC_R_PCIE_B>; 78 + fsl,max-link-speed = <3>; 79 + status = "disabled"; 80 + }; 81 + 82 + pcieb_lpcg: clock-controller@5f060000 { 83 + compatible = "fsl,imx8qxp-lpcg"; 84 + reg = <0x5f060000 0x10000>; 85 + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; 86 + #clock-cells = <1>; 87 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; 88 + clock-output-names = "hsio_pcieb_mstr_axi_clk", 89 + "hsio_pcieb_slv_axi_clk", 90 + "hsio_pcieb_dbi_axi_clk"; 91 + power-domains = <&pd IMX_SC_R_PCIE_B>; 92 + }; 93 + 94 + phyx1_crr1_lpcg: clock-controller@5f0b0000 { 95 + compatible = "fsl,imx8qxp-lpcg"; 96 + reg = <0x5f0b0000 0x10000>; 97 + clocks = <&hsio_per_clk>; 98 + #clock-cells = <1>; 99 + clock-indices = <IMX_LPCG_CLK_4>; 100 + clock-output-names = "hsio_phyx1_per_clk"; 101 + power-domains = <&pd IMX_SC_R_SERDES_1>; 102 + }; 103 + 104 + pcieb_crr3_lpcg: clock-controller@5f0d0000 { 105 + compatible = "fsl,imx8qxp-lpcg"; 106 + reg = <0x5f0d0000 0x10000>; 107 + clocks = <&hsio_per_clk>; 108 + #clock-cells = <1>; 109 + clock-indices = <IMX_LPCG_CLK_4>; 110 + clock-output-names = "hsio_pcieb_per_clk"; 111 + power-domains = <&pd IMX_SC_R_PCIE_B>; 112 + }; 113 + 114 + misc_crr5_lpcg: clock-controller@5f0f0000 { 115 + compatible = "fsl,imx8qxp-lpcg"; 116 + reg = <0x5f0f0000 0x10000>; 117 + clocks = <&hsio_per_clk>; 118 + #clock-cells = <1>; 119 + clock-indices = <IMX_LPCG_CLK_4>; 120 + clock-output-names = "hsio_misc_per_clk"; 121 + power-domains = <&pd IMX_SC_R_HSIO_GPIO>; 122 + }; 123 + };
+33
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
··· 182 182 regulator-always-on; 183 183 }; 184 184 185 + reg_pcieb: regulator-pcieb { 186 + compatible = "regulator-fixed"; 187 + regulator-max-microvolt = <3300000>; 188 + regulator-min-microvolt = <3300000>; 189 + regulator-name = "reg_pcieb"; 190 + gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; 191 + enable-active-high; 192 + }; 193 + 185 194 bt_sco_codec: audio-codec-bt { 186 195 compatible = "linux,bt-sco"; 187 196 #sound-dai-cells = <1>; ··· 576 567 status = "okay"; 577 568 }; 578 569 570 + &hsio_phy { 571 + fsl,hsio-cfg = "pciea-x2-pcieb"; 572 + fsl,refclk-pad-mode = "output"; 573 + status = "okay"; 574 + }; 575 + 579 576 &cm40_intmux { 580 577 status = "disabled"; 581 578 }; ··· 597 582 }; 598 583 599 584 &lsio_gpio5 { 585 + status = "okay"; 586 + }; 587 + 588 + &pcieb { 589 + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 590 + phy-names = "pcie-phy"; 591 + pinctrl-0 = <&pinctrl_pcieb>; 592 + pinctrl-names = "default"; 593 + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 594 + vpcie-supply = <&reg_pcieb>; 600 595 status = "okay"; 601 596 }; 602 597 ··· 890 865 IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 891 866 IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 892 867 IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 868 + >; 869 + }; 870 + 871 + pinctrl_pcieb: pcieagrp { 872 + fsl,pins = < 873 + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 874 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 875 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 893 876 >; 894 877 }; 895 878
+4
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
··· 138 138 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 139 139 }; 140 140 141 + &usbphy1 { 142 + compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; 143 + }; 144 + 141 145 &usdhc1 { 142 146 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 143 147 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+51
arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright 2024 NXP 4 + */ 5 + 6 + &hsio_subsys { 7 + phyx1_lpcg: clock-controller@5f090000 { 8 + compatible = "fsl,imx8qxp-lpcg"; 9 + reg = <0x5f090000 0x10000>; 10 + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, 11 + <&hsio_per_clk>, <&hsio_per_clk>; 12 + #clock-cells = <1>; 13 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 14 + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>; 15 + clock-output-names = "hsio_phyx1_pclk", 16 + "hsio_phyx1_epcs_tx_clk", 17 + "hsio_phyx1_epcs_rx_clk", 18 + "hsio_phyx1_apb_clk"; 19 + power-domains = <&pd IMX_SC_R_SERDES_1>; 20 + }; 21 + 22 + hsio_phy: phy@5f1a0000 { 23 + compatible = "fsl,imx8qxp-hsio"; 24 + reg = <0x5f1a0000 0x10000>, 25 + <0x5f120000 0x10000>, 26 + <0x5f140000 0x10000>, 27 + <0x5f160000 0x10000>; 28 + reg-names = "reg", "phy", "ctrl", "misc"; 29 + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, 30 + <&phyx1_lpcg IMX_LPCG_CLK_4>, 31 + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, 32 + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, 33 + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; 34 + clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", 35 + "misc_crr"; 36 + #phy-cells = <3>; 37 + power-domains = <&pd IMX_SC_R_SERDES_1>; 38 + status = "disabled"; 39 + }; 40 + }; 41 + 42 + &pcieb { 43 + #interrupt-cells = <1>; 44 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 45 + interrupt-names = "msi"; 46 + interrupt-map = <0 0 0 1 &gic 0 47 4>, 47 + <0 0 0 2 &gic 0 48 4>, 48 + <0 0 0 3 &gic 0 49 4>, 49 + <0 0 0 4 &gic 0 50 4>; 50 + interrupt-map-mask = <0 0 0 0x7>; 51 + };
+6
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
··· 30 30 gpio6 = &lsio_gpio6; 31 31 gpio7 = &lsio_gpio7; 32 32 mu1 = &lsio_mu1; 33 + spi0 = &lpspi0; 34 + spi1 = &lpspi1; 35 + spi2 = &lpspi2; 36 + spi3 = &lpspi3; 33 37 }; 34 38 35 39 cpus: cpus { ··· 241 237 #include "imx8-ss-conn.dtsi" 242 238 #include "imx8-ss-ddr.dtsi" 243 239 #include "imx8-ss-lsio.dtsi" 240 + #include "imx8-ss-hsio.dtsi" 244 241 }; 245 242 246 243 #include "imx8dxl-ss-adma.dtsi" 247 244 #include "imx8dxl-ss-conn.dtsi" 248 245 #include "imx8dxl-ss-lsio.dtsi" 249 246 #include "imx8dxl-ss-ddr.dtsi" 247 + #include "imx8dxl-ss-hsio.dtsi" 250 248 251 249 &cm40_intmux { 252 250 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+335
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
··· 1 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 /* 3 3 * Copyright 2023 Emtop Embedded Solutions 4 + * 5 + * Author: Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> 6 + * Author: Tarang Raval <tarang.raval@siliconsignals.io> 4 7 */ 5 8 6 9 /dts-v1/; ··· 14 11 model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1"; 15 12 compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som", 16 13 "fsl,imx8mm"; 14 + 15 + connector { 16 + compatible = "usb-c-connector"; 17 + label = "USB-C"; 18 + pinctrl-names = "default"; 19 + pinctrl-0 = <&pinctrl_usb_otg>; 20 + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 21 + 22 + port { 23 + high_speed_ep: endpoint { 24 + remote-endpoint = <&usb_hs_ep>; 25 + }; 26 + }; 27 + }; 28 + 29 + leds { 30 + compatible = "gpio-leds"; 31 + pinctrl-names = "default"; 32 + pinctrl-0 = <&pinctrl_gpio_led>; 33 + 34 + led-1 { 35 + label = "buzzer"; 36 + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 37 + default-state = "off"; 38 + }; 39 + }; 40 + 41 + osc_can: clock-osc-can { 42 + compatible = "fixed-clock"; 43 + #clock-cells = <0>; 44 + clock-frequency = <16000000>; 45 + clock-output-names = "osc-can"; 46 + }; 47 + 48 + reg_audio: regulator-audio { 49 + compatible = "regulator-fixed"; 50 + regulator-name = "wm8904_supply"; 51 + regulator-min-microvolt = <1800000>; 52 + regulator-max-microvolt = <1800000>; 53 + regulator-always-on; 54 + }; 55 + 56 + reg_wifi_vmmc: regulator-wifi-vmmc { 57 + compatible = "regulator-fixed"; 58 + regulator-name = "vmmc"; 59 + regulator-min-microvolt = <3300000>; 60 + regulator-max-microvolt = <3300000>; 61 + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; 62 + enable-active-high; 63 + startup-delay-us = <100>; 64 + off-on-delay-us = <20000>; 65 + }; 66 + 67 + sound-wm8904 { 68 + compatible = "simple-audio-card"; 69 + simple-audio-card,bitclock-master = <&dailink_master>; 70 + simple-audio-card,format = "i2s"; 71 + simple-audio-card,frame-master = <&dailink_master>; 72 + simple-audio-card,name = "wm8904-audio"; 73 + simple-audio-card,mclk-fs = <256>; 74 + simple-audio-card,routing = 75 + "Headphone Jack", "HPOUTL", 76 + "Headphone Jack", "HPOUTR", 77 + "IN2L", "Line In Jack", 78 + "IN2R", "Line In Jack", 79 + "Headphone Jack", "MICBIAS", 80 + "IN1L", "Headphone Jack"; 81 + 82 + simple-audio-card,widgets = 83 + "Microphone","Headphone Jack", 84 + "Headphone", "Headphone Jack", 85 + "Line", "Line In Jack"; 86 + 87 + dailink_master: simple-audio-card,codec { 88 + sound-dai = <&wm8904>; 89 + }; 90 + 91 + simple-audio-card,cpu { 92 + sound-dai = <&sai3>; 93 + }; 94 + }; 95 + 96 + sound-spdif { 97 + compatible = "fsl,imx-audio-spdif"; 98 + model = "imx-spdif"; 99 + spdif-controller = <&spdif1>; 100 + spdif-out; 101 + spdif-in; 102 + }; 103 + }; 104 + 105 + /* CAN BUS */ 106 + &ecspi2 { 107 + pinctrl-names = "default"; 108 + pinctrl-0 = <&pinctrl_ecspi2>; 109 + status = "okay"; 110 + 111 + can: can@0 { 112 + compatible = "microchip,mcp2515"; 113 + reg = <0>; 114 + pinctrl-names = "default"; 115 + pinctrl-0 = <&pinctrl_canbus>; 116 + clocks = <&osc_can>; 117 + interrupt-parent = <&gpio1>; 118 + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 119 + spi-max-frequency = <10000000>; 120 + }; 17 121 }; 18 122 19 123 &fec1 { ··· 150 40 }; 151 41 }; 152 42 43 + &i2c3 { 44 + clock-frequency = <100000>; 45 + pinctrl-names = "default"; 46 + pinctrl-0 = <&pinctrl_i2c3>; 47 + status = "okay"; 48 + 49 + wm8904: audio-codec@1a { 50 + compatible = "wlf,wm8904"; 51 + reg = <0x1a>; 52 + #sound-dai-cells = <0>; 53 + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 54 + clock-names = "mclk"; 55 + DCVDD-supply = <&reg_audio>; 56 + DBVDD-supply = <&reg_audio>; 57 + AVDD-supply = <&reg_audio>; 58 + CPVDD-supply = <&reg_audio>; 59 + MICVDD-supply = <&reg_audio>; 60 + }; 61 + 62 + rtc@32 { 63 + compatible = "epson,rx8025"; 64 + reg = <0x32>; 65 + }; 66 + }; 67 + 68 + /* AUDIO */ 69 + &sai3 { 70 + pinctrl-names = "default"; 71 + pinctrl-0 = <&pinctrl_sai3>; 72 + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 73 + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 74 + assigned-clock-rates = <24576000>; 75 + status = "okay"; 76 + }; 77 + 78 + &spdif1 { 79 + pinctrl-names = "default"; 80 + pinctrl-0 = <&pinctrl_spdif1>; 81 + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; 82 + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 83 + assigned-clock-rates = <24576000>; 84 + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, 85 + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, 86 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 87 + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, 88 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 89 + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; 90 + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", 91 + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; 92 + status = "okay"; 93 + }; 94 + 95 + /* USBOTG */ 96 + &usbotg1 { 97 + dr_mode = "otg"; 98 + usb-role-switch; 99 + status = "okay"; 100 + 101 + port { 102 + usb_hs_ep: endpoint { 103 + remote-endpoint = <&high_speed_ep>; 104 + }; 105 + }; 106 + }; 107 + 108 + &usbotg2 { 109 + dr_mode = "host"; 110 + status = "okay"; 111 + }; 112 + 113 + /* Wifi */ 114 + &usdhc1 { 115 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 116 + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 117 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 118 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 119 + bus-width = <4>; 120 + vmmc-supply = <&reg_wifi_vmmc>; 121 + cap-power-off-card; 122 + keep-power-in-suspend; 123 + non-removable; 124 + #address-cells = <1>; 125 + #size-cells = <0>; 126 + status = "okay"; 127 + 128 + wifi: wifi@1 { 129 + compatible = "brcm,bcm4329-fmac"; 130 + reg = <1>; 131 + interrupt-parent = <&gpio2>; 132 + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 133 + interrupt-names = "host-wake"; 134 + }; 135 + }; 136 + 137 + /* SD-card */ 138 + &usdhc2 { 139 + pinctrl-names = "default"; 140 + pinctrl-0 = <&pinctrl_usdhc2>; 141 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 142 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 143 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 144 + bus-width = <4>; 145 + status = "okay"; 146 + }; 147 + 153 148 &iomuxc { 149 + 150 + pinctrl_canbus: canbusgrp { 151 + fsl,pins = < 152 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14 153 + >; 154 + }; 155 + 156 + pinctrl_ecspi2: ecspi2grp { 157 + fsl,pins = < 158 + MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 159 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 160 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 161 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 162 + >; 163 + }; 164 + 165 + pinctrl_usb_otg: usbotggrp { 166 + fsl,pins = < 167 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */ 168 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */ 169 + >; 170 + }; 171 + 154 172 pinctrl_fec1: fec1grp { 155 173 fsl,pins = < 156 174 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 ··· 297 59 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 298 60 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 299 61 >; 62 + }; 63 + 64 + pinctrl_i2c3: i2c3grp { 65 + fsl,pins = < 66 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 67 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 68 + >; 69 + }; 70 + 71 + pinctrl_sai3: sai3grp { 72 + fsl,pins = < 73 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 74 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 75 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 76 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 77 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 78 + >; 79 + }; 80 + 81 + pinctrl_spdif1: spdif1grp { 82 + fsl,pins = < 83 + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 84 + >; 85 + }; 86 + 87 + pinctrl_usdhc1: usdhc1grp { 88 + fsl,pins = < 89 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 90 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 91 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 92 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 93 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 94 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 95 + >; 96 + }; 97 + 98 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{ 99 + fsl,pins = < 100 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 101 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 102 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 103 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 104 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 105 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 106 + >; 107 + }; 108 + 109 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 110 + fsl,pins = < 111 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 112 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 113 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 114 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 115 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 116 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 117 + >; 118 + }; 119 + 120 + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { 121 + fsl,pins = < 122 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */ 123 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */ 124 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */ 125 + >; 126 + }; 127 + 128 + pinctrl_usdhc2: usdhc2grp { 129 + fsl,pins = < 130 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 131 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 132 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 133 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 134 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 135 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 136 + >; 137 + }; 138 + 139 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 140 + fsl,pins = < 141 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 142 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 143 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 144 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 145 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 146 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 147 + >; 148 + }; 149 + 150 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 151 + fsl,pins = < 152 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 153 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 154 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 155 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 156 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 157 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 158 + >; 300 159 }; 301 160 };
+131
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
··· 25 25 clock-output-names = "osc-can"; 26 26 }; 27 27 28 + hdmi-out { 29 + compatible = "hdmi-connector"; 30 + type = "a"; 31 + 32 + port { 33 + hdmi_in_conn: endpoint { 34 + remote-endpoint = <&bridge_out_conn>; 35 + }; 36 + }; 37 + }; 38 + 28 39 leds { 29 40 compatible = "gpio-leds"; 30 41 pinctrl-names = "default"; ··· 143 132 }; 144 133 }; 145 134 135 + &gpio4 { 136 + pinctrl-names = "default"; 137 + pinctrl-0 = <&pinctrl_gpio4>; 138 + 139 + dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog { 140 + gpio-hog; 141 + gpios = <14 GPIO_ACTIVE_HIGH>; 142 + output-high; 143 + line-name = "dsi-mux-sel"; 144 + }; 145 + 146 + dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog { 147 + gpio-hog; 148 + gpios = <14 GPIO_ACTIVE_HIGH>; 149 + output-low; 150 + line-name = "dsi-mux-sel"; 151 + status = "disabled"; 152 + }; 153 + 154 + dsi-mux-oe-hog { 155 + gpio-hog; 156 + gpios = <15 GPIO_ACTIVE_LOW>; 157 + output-high; 158 + line-name = "dsi-mux-oe"; 159 + }; 160 + }; 161 + 162 + &i2c3 { 163 + clock-frequency = <400000>; 164 + pinctrl-names = "default"; 165 + pinctrl-0 = <&pinctrl_i2c3>; 166 + status = "okay"; 167 + 168 + lvds: bridge@2c { 169 + compatible = "ti,sn65dsi84"; 170 + reg = <0x2c>; 171 + enable-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 172 + pinctrl-names = "default"; 173 + pinctrl-0 = <&pinctrl_sn65dsi84>; 174 + status = "disabled"; 175 + }; 176 + 177 + hdmi: hdmi@39 { 178 + compatible = "adi,adv7535"; 179 + reg = <0x39>; 180 + pinctrl-names = "default"; 181 + pinctrl-0 = <&pinctrl_adv7535>; 182 + adi,dsi-lanes = <4>; 183 + interrupt-parent = <&gpio4>; 184 + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 185 + a2vdd-supply = <&reg_vdd_1v8>; 186 + avdd-supply = <&reg_vdd_1v8>; 187 + dvdd-supply = <&reg_vdd_1v8>; 188 + pvdd-supply = <&reg_vdd_1v8>; 189 + v1p2-supply = <&reg_vdd_1v8>; 190 + v3p3-supply = <&reg_vdd_3v3>; 191 + 192 + ports { 193 + #address-cells = <1>; 194 + #size-cells = <0>; 195 + 196 + port@0 { 197 + reg = <0>; 198 + 199 + bridge_in_dsi_hdmi: endpoint { 200 + remote-endpoint = <&mipi_dsi_out>; 201 + }; 202 + }; 203 + 204 + port@1 { 205 + reg = <1>; 206 + 207 + bridge_out_conn: endpoint { 208 + remote-endpoint = <&hdmi_in_conn>; 209 + }; 210 + }; 211 + }; 212 + }; 213 + }; 214 + 146 215 &i2c4 { 147 216 clock-frequency = <100000>; 148 217 pinctrl-names = "default"; ··· 233 142 compatible = "epson,rx8900"; 234 143 reg = <0x32>; 235 144 }; 145 + }; 146 + 147 + &lcdif { 148 + status = "okay"; 149 + }; 150 + 151 + &mipi_dsi { 152 + samsung,esc-clock-frequency = <54000000>; 153 + status = "okay"; 154 + }; 155 + 156 + &mipi_dsi_out { 157 + remote-endpoint = <&bridge_in_dsi_hdmi>; 236 158 }; 237 159 238 160 &pwm2 { ··· 310 206 &iomuxc { 311 207 pinctrl-names = "default"; 312 208 pinctrl-0 = <&pinctrl_gpio>; 209 + 210 + pinctrl_adv7535: adv7535grp { 211 + fsl,pins = < 212 + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 213 + >; 214 + }; 313 215 314 216 pinctrl_can: cangrp { 315 217 fsl,pins = < ··· 387 277 >; 388 278 }; 389 279 280 + pinctrl_gpio4: gpio4grp { 281 + fsl,pins = < 282 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 283 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 284 + >; 285 + }; 286 + 287 + pinctrl_i2c3: i2c3grp { 288 + fsl,pins = < 289 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 290 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 291 + >; 292 + }; 293 + 390 294 pinctrl_i2c4: i2c4grp { 391 295 fsl,pins = < 392 296 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 ··· 411 287 pinctrl_pwm2: pwm2grp { 412 288 fsl,pins = < 413 289 MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 290 + >; 291 + }; 292 + 293 + pinctrl_sn65dsi84: sn65dsi84grp { 294 + fsl,pins = < 295 + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 296 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 414 297 >; 415 298 }; 416 299
+189
arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright (C) 2024 Kontron Electronics GmbH 4 + */ 5 + 6 + /dts-v1/; 7 + /plugin/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include "imx8mm-pinfunc.h" 11 + 12 + &{/} { 13 + compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; 14 + 15 + backlight: backlight { 16 + compatible = "pwm-backlight"; 17 + pwms = <&pwm1 0 50000 0>; 18 + brightness-levels = <0 100>; 19 + num-interpolated-steps = <100>; 20 + default-brightness-level = <100>; 21 + }; 22 + 23 + panel { 24 + compatible = "jenson,bl-jt60050-01a", "panel-lvds"; 25 + pinctrl-names = "default"; 26 + pinctrl-0 = <&pinctrl_panel>; 27 + backlight = <&backlight>; 28 + data-mapping = "vesa-24"; 29 + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 30 + height-mm = <86>; 31 + width-mm = <154>; 32 + 33 + panel-timing { 34 + clock-frequency = <51200000>; 35 + hactive = <1024>; 36 + vactive = <600>; 37 + hsync-len = <1>; 38 + hfront-porch = <160>; 39 + hback-porch = <160>; 40 + vsync-len = <1>; 41 + vfront-porch = <12>; 42 + vback-porch = <23>; 43 + }; 44 + 45 + port { 46 + panel_out_bridge: endpoint { 47 + remote-endpoint = <&bridge_out_panel>; 48 + }; 49 + }; 50 + }; 51 + }; 52 + 53 + &dsi_mux_sel_hdmi { 54 + status = "disabled"; 55 + }; 56 + 57 + &dsi_mux_sel_lvds { 58 + status = "okay"; 59 + }; 60 + 61 + &mipi_dsi_out { 62 + remote-endpoint = <&bridge_in_dsi_lvds>; 63 + }; 64 + 65 + &gpio3 { 66 + pinctrl-names = "default"; 67 + pinctrl-0 = <&pinctrl_gpio3>; 68 + 69 + panel-rst-hog { 70 + gpio-hog; 71 + gpios = <20 GPIO_ACTIVE_HIGH>; 72 + output-high; 73 + line-name = "panel-reset"; 74 + }; 75 + 76 + panel-stby-hog { 77 + gpio-hog; 78 + gpios = <21 GPIO_ACTIVE_HIGH>; 79 + output-high; 80 + line-name = "panel-standby"; 81 + }; 82 + 83 + panel-hinv-hog { 84 + gpio-hog; 85 + gpios = <24 GPIO_ACTIVE_HIGH>; 86 + output-high; 87 + line-name = "panel-horizontal-invert"; 88 + }; 89 + 90 + panel-vinv-hog { 91 + gpio-hog; 92 + gpios = <25 GPIO_ACTIVE_HIGH>; 93 + output-low; 94 + line-name = "panel-vertical-invert"; 95 + }; 96 + }; 97 + 98 + &hdmi { 99 + status = "disabled"; 100 + }; 101 + 102 + &i2c2 { 103 + clock-frequency = <400000>; 104 + pinctrl-names = "default"; 105 + pinctrl-0 = <&pinctrl_i2c2>; 106 + #address-cells = <1>; 107 + #size-cells = <0>; 108 + status = "okay"; 109 + 110 + touchscreen@5d { 111 + compatible = "goodix,gt928"; 112 + reg = <0x5d>; 113 + pinctrl-names = "default"; 114 + pinctrl-0 = <&pinctrl_touch>; 115 + interrupt-parent = <&gpio3>; 116 + interrupts = <22 8>; 117 + reset-gpios = <&gpio3 23 0>; 118 + irq-gpios = <&gpio3 22 0>; 119 + }; 120 + }; 121 + 122 + &lvds { 123 + status = "okay"; 124 + 125 + ports { 126 + #address-cells = <1>; 127 + #size-cells = <0>; 128 + 129 + port@0 { 130 + reg = <0>; 131 + 132 + bridge_in_dsi_lvds: endpoint { 133 + remote-endpoint = <&mipi_dsi_out>; 134 + data-lanes = <1 2>; 135 + }; 136 + }; 137 + 138 + port@2 { 139 + reg = <2>; 140 + 141 + bridge_out_panel: endpoint { 142 + remote-endpoint = <&panel_out_bridge>; 143 + }; 144 + }; 145 + }; 146 + }; 147 + 148 + &pwm1 { 149 + pinctrl-names = "default"; 150 + pinctrl-0 = <&pinctrl_pwm1>; 151 + status = "okay"; 152 + }; 153 + 154 + &iomuxc { 155 + pinctrl_gpio3: gpio3grp { 156 + fsl,pins = < 157 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 158 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 159 + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 160 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 161 + >; 162 + }; 163 + 164 + pinctrl_i2c2: i2c2grp { 165 + fsl,pins = < 166 + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 167 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 168 + >; 169 + }; 170 + 171 + pinctrl_panel: panelgrp { 172 + fsl,pins = < 173 + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 174 + >; 175 + }; 176 + 177 + pinctrl_pwm1: pwm1grp { 178 + fsl,pins = < 179 + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6 180 + >; 181 + }; 182 + 183 + pinctrl_touch: touchgrp { 184 + fsl,pins = < 185 + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 186 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 187 + >; 188 + }; 189 + };
+5
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
··· 75 75 }; 76 76 }; 77 77 78 + &mipi_dsi { 79 + samsung,burst-clock-frequency = <891000000>; 80 + samsung,esc-clock-frequency = <20000000>; 81 + }; 82 + 78 83 &pcie_phy { 79 84 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 80 85 fsl,clkreq-unsupported;
+6 -1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
··· 9 9 #include <dt-bindings/net/ti-dp83867.h> 10 10 11 11 / { 12 + aliases { 13 + rtc0 = &gsc_rtc; 14 + rtc1 = &snvs_rtc; 15 + }; 16 + 12 17 memory@40000000 { 13 18 device_type = "memory"; 14 19 reg = <0x0 0x40000000 0 0x80000000>; ··· 297 292 pagesize = <16>; 298 293 }; 299 294 300 - rtc@68 { 295 + gsc_rtc: rtc@68 { 301 296 compatible = "dallas,ds1672"; 302 297 reg = <0x68>; 303 298 };
-4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso
··· 15 15 /dts-v1/; 16 16 /plugin/; 17 17 18 - &{/} { 19 - compatible = "gw,imx8mm-gw73xx-0x"; 20 - }; 21 - 22 18 &gpio4 { 23 19 rs485-en-hog { 24 20 gpio-hog;
-4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso
··· 18 18 /dts-v1/; 19 19 /plugin/; 20 20 21 - &{/} { 22 - compatible = "gw,imx8mm-gw73xx-0x"; 23 - }; 24 - 25 21 &gpio4 { 26 22 rs485-en-hog { 27 23 gpio-hog;
-4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso
··· 18 18 /dts-v1/; 19 19 /plugin/; 20 20 21 - &{/} { 22 - compatible = "gw,imx8mm-gw73xx-0x"; 23 - }; 24 - 25 21 &gpio4 { 26 22 rs485-en-hog { 27 23 gpio-hog;
+16
arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
··· 116 116 pinctrl-0 = <&pinctrl_i2c2>; 117 117 status = "okay"; 118 118 119 + accelerometer@19 { 120 + compatible = "st,lis2de12"; 121 + reg = <0x19>; 122 + pinctrl-names = "default"; 123 + pinctrl-0 = <&pinctrl_accel>; 124 + interrupt-parent = <&gpio5>; 125 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 126 + st,drdy-int-pin = <1>; 127 + }; 128 + 119 129 eeprom@52 { 120 130 compatible = "atmel,24c32"; 121 131 reg = <0x52>; ··· 205 195 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ 206 196 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ 207 197 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ 198 + >; 199 + }; 200 + 201 + pinctrl_accel: accelgrp { 202 + fsl,pins = < 203 + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x159 208 204 >; 209 205 }; 210 206
+3 -1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
··· 22 22 ethernet2 = &lan2; 23 23 ethernet3 = &lan3; 24 24 ethernet4 = &lan4; 25 + rtc0 = &gsc_rtc; 26 + rtc1 = &snvs_rtc; 25 27 usb0 = &usbotg1; 26 28 usb1 = &usbotg2; 27 29 }; ··· 499 497 pagesize = <16>; 500 498 }; 501 499 502 - rtc@68 { 500 + gsc_rtc: rtc@68 { 503 501 compatible = "dallas,ds1672"; 504 502 reg = <0x68>; 505 503 };
+3 -1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
··· 19 19 20 20 aliases { 21 21 ethernet1 = &eth1; 22 + rtc0 = &gsc_rtc; 23 + rtc1 = &snvs_rtc; 22 24 usb0 = &usbotg1; 23 25 usb1 = &usbotg2; 24 26 }; ··· 566 564 pagesize = <16>; 567 565 }; 568 566 569 - rtc@68 { 567 + gsc_rtc: rtc@68 { 570 568 compatible = "dallas,ds1672"; 571 569 reg = <0x68>; 572 570 };
+3 -1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
··· 18 18 19 19 aliases { 20 20 ethernet0 = &fec1; 21 + rtc0 = &gsc_rtc; 22 + rtc1 = &snvs_rtc; 21 23 usb0 = &usbotg1; 22 24 }; 23 25 ··· 396 394 pagesize = <16>; 397 395 }; 398 396 399 - rtc@68 { 397 + gsc_rtc: rtc@68 { 400 398 compatible = "dallas,ds1672"; 401 399 reg = <0x68>; 402 400 };
+6 -1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
··· 16 16 model = "Gateworks Venice GW7904 i.MX8MM board"; 17 17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; 18 18 19 + aliases { 20 + rtc0 = &gsc_rtc; 21 + rtc1 = &snvs_rtc; 22 + }; 23 + 19 24 chosen { 20 25 stdout-path = &uart2; 21 26 }; ··· 443 438 pagesize = <16>; 444 439 }; 445 440 446 - rtc@68 { 441 + gsc_rtc: rtc@68 { 447 442 compatible = "dallas,ds1672"; 448 443 reg = <0x68>; 449 444 };
+471
arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2024 Toradex 4 + * 5 + * Common dtsi for Verdin IMX8MM SoM on Ivy carrier board 6 + * 7 + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano 8 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board 9 + */ 10 + 11 + #include <dt-bindings/mux/mux.h> 12 + #include <dt-bindings/leds/common.h> 13 + 14 + / { 15 + /* AIN1 Voltage w/o AIN1_MODE gpio control */ 16 + ain1_voltage_unmanaged: voltage-divider-ain1 { 17 + compatible = "voltage-divider"; 18 + #io-channel-cells = <1>; 19 + io-channels = <&ivy_adc1 0>; 20 + full-ohms = <19>; 21 + output-ohms = <1>; 22 + }; 23 + 24 + /* AIN1 Current w/o AIN1_MODE gpio control */ 25 + ain1_current_unmanaged: current-sense-shunt-ain1 { 26 + compatible = "current-sense-shunt"; 27 + #io-channel-cells = <0>; 28 + io-channels = <&ivy_adc1 1>; 29 + shunt-resistor-micro-ohms = <100000000>; 30 + }; 31 + 32 + /* AIN1_MODE - SODIMM 216 */ 33 + ain1_mode_mux_ctrl: mux-controller-0 { 34 + compatible = "gpio-mux"; 35 + pinctrl-names = "default"; 36 + pinctrl-0 = <&pinctrl_gpio5>; 37 + #mux-control-cells = <0>; 38 + mux-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 39 + }; 40 + 41 + ain1-voltage { 42 + compatible = "io-channel-mux"; 43 + channels = "ain1_voltage", ""; 44 + io-channels = <&ain1_voltage_unmanaged 0>; 45 + io-channel-names = "parent"; 46 + mux-controls = <&ain1_mode_mux_ctrl>; 47 + settle-time-us = <1000>; 48 + }; 49 + 50 + ain1-current { 51 + compatible = "io-channel-mux"; 52 + channels = "", "ain1_current"; 53 + io-channels = <&ain1_current_unmanaged>; 54 + io-channel-names = "parent"; 55 + mux-controls = <&ain1_mode_mux_ctrl>; 56 + settle-time-us = <1000>; 57 + }; 58 + 59 + /* AIN2 Voltage w/o AIN2_MODE gpio control */ 60 + ain2_voltage_unmanaged: voltage-divider-ain2 { 61 + compatible = "voltage-divider"; 62 + #io-channel-cells = <1>; 63 + io-channels = <&ivy_adc2 0>; 64 + full-ohms = <19>; 65 + output-ohms = <1>; 66 + }; 67 + 68 + /* AIN2 Current w/o AIN2_MODE gpio control */ 69 + ain2_current_unmanaged: current-sense-shunt-ain2 { 70 + compatible = "current-sense-shunt"; 71 + #io-channel-cells = <0>; 72 + io-channels = <&ivy_adc2 1>; 73 + shunt-resistor-micro-ohms = <100000000>; 74 + }; 75 + 76 + /* AIN2_MODE - SODIMM 218 */ 77 + ain2_mode_mux_ctrl: mux-controller-1 { 78 + compatible = "gpio-mux"; 79 + pinctrl-names = "default"; 80 + pinctrl-0 = <&pinctrl_gpio6>; 81 + #mux-control-cells = <0>; 82 + mux-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 83 + }; 84 + 85 + ain2-voltage { 86 + compatible = "io-channel-mux"; 87 + channels = "ain2_voltage", ""; 88 + io-channels = <&ain2_voltage_unmanaged 0>; 89 + io-channel-names = "parent"; 90 + mux-controls = <&ain2_mode_mux_ctrl>; 91 + settle-time-us = <1000>; 92 + }; 93 + 94 + ain2-current { 95 + compatible = "io-channel-mux"; 96 + channels = "", "ain2_current"; 97 + io-channels = <&ain2_current_unmanaged>; 98 + io-channel-names = "parent"; 99 + mux-controls = <&ain2_mode_mux_ctrl>; 100 + settle-time-us = <1000>; 101 + }; 102 + 103 + leds { 104 + compatible = "gpio-leds"; 105 + pinctrl-names = "default"; 106 + pinctrl-0 = <&pinctrl_ivy_leds>; 107 + 108 + /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */ 109 + led-0 { 110 + color = <LED_COLOR_ID_BLUE>; 111 + default-state = "off"; 112 + function = LED_FUNCTION_STATUS; 113 + function-enumerator = <1>; 114 + gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 115 + }; 116 + 117 + /* D7 Green - SODIMM 32 - LEDs.GPIO2 */ 118 + led-1 { 119 + color = <LED_COLOR_ID_GREEN>; 120 + default-state = "off"; 121 + function = LED_FUNCTION_STATUS; 122 + function-enumerator = <1>; 123 + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 124 + }; 125 + 126 + /* D7 Red - SODIMM 34 - LEDs.GPIO3 */ 127 + led-2 { 128 + color = <LED_COLOR_ID_RED>; 129 + default-state = "off"; 130 + function = LED_FUNCTION_STATUS; 131 + function-enumerator = <1>; 132 + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 133 + }; 134 + 135 + /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */ 136 + led-3 { 137 + color = <LED_COLOR_ID_BLUE>; 138 + default-state = "off"; 139 + function = LED_FUNCTION_STATUS; 140 + function-enumerator = <2>; 141 + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; 142 + }; 143 + 144 + /* D8 Green - SODIMM 54 - LEDs.GPIO5 */ 145 + led-4 { 146 + color = <LED_COLOR_ID_GREEN>; 147 + default-state = "off"; 148 + function = LED_FUNCTION_STATUS; 149 + function-enumerator = <2>; 150 + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; 151 + }; 152 + 153 + /* D8 Red - SODIMM 44 - LEDs.GPIO6 */ 154 + led-5 { 155 + color = <LED_COLOR_ID_RED>; 156 + default-state = "off"; 157 + function = LED_FUNCTION_STATUS; 158 + function-enumerator = <2>; 159 + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 160 + }; 161 + 162 + /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */ 163 + led-6 { 164 + color = <LED_COLOR_ID_BLUE>; 165 + default-state = "off"; 166 + function = LED_FUNCTION_STATUS; 167 + function-enumerator = <3>; 168 + gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 169 + }; 170 + 171 + /* D9 Red - SODIMM 48 - LEDs.GPIO8 */ 172 + led-7 { 173 + color = <LED_COLOR_ID_RED>; 174 + default-state = "off"; 175 + function = LED_FUNCTION_STATUS; 176 + function-enumerator = <3>; 177 + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 178 + }; 179 + }; 180 + 181 + reg_3v2_ain1: regulator-3v2-ain1 { 182 + compatible = "regulator-fixed"; 183 + regulator-max-microvolt = <3200000>; 184 + regulator-min-microvolt = <3200000>; 185 + regulator-name = "+3V2_AIN1"; 186 + }; 187 + 188 + reg_3v2_ain2: regulator-3v2-ain2 { 189 + compatible = "regulator-fixed"; 190 + regulator-max-microvolt = <3200000>; 191 + regulator-min-microvolt = <3200000>; 192 + regulator-name = "+3V2_AIN2"; 193 + }; 194 + 195 + /* Ivy Power Supply Input Voltage */ 196 + ivy-input-voltage { 197 + compatible = "voltage-divider"; 198 + /* Verdin ADC_1 */ 199 + io-channels = <&verdin_som_adc 7>; 200 + full-ohms = <204700>; /* 200k + 4.7k */ 201 + output-ohms = <4700>; 202 + }; 203 + 204 + ivy-5v-voltage { 205 + compatible = "voltage-divider"; 206 + /* Verdin ADC_2 */ 207 + io-channels = <&verdin_som_adc 6>; 208 + full-ohms = <39000>; /* 27k + 12k */ 209 + output-ohms = <12000>; 210 + }; 211 + 212 + ivy-3v3-voltage { 213 + compatible = "voltage-divider"; 214 + /* Verdin ADC_3 */ 215 + io-channels = <&verdin_som_adc 5>; 216 + full-ohms = <54000>; /* 27k + 27k */ 217 + output-ohms = <27000>; 218 + }; 219 + 220 + ivy-1v8-voltage { 221 + compatible = "voltage-divider"; 222 + /* Verdin ADC_4 */ 223 + io-channels = <&verdin_som_adc 4>; 224 + full-ohms = <39000>; /* 12k + 27k */ 225 + output-ohms = <27000>; 226 + }; 227 + }; 228 + 229 + /* Verdin SPI_1 */ 230 + &ecspi2 { 231 + pinctrl-0 = <&pinctrl_ecspi2>, 232 + <&pinctrl_gpio1>, 233 + <&pinctrl_gpio4>; 234 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 235 + <&gpio3 4 GPIO_ACTIVE_LOW>, 236 + <&gpio5 27 GPIO_ACTIVE_LOW>; 237 + status = "okay"; 238 + 239 + tpm@1 { 240 + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 241 + reg = <1>; 242 + spi-max-frequency = <18500000>; 243 + }; 244 + 245 + fram@2 { 246 + compatible = "fujitsu,mb85rs256", "atmel,at25"; 247 + reg = <2>; 248 + address-width = <16>; 249 + size = <32768>; 250 + spi-max-frequency = <33000000>; 251 + pagesize = <1>; 252 + }; 253 + }; 254 + 255 + /* EEPROM on Ivy */ 256 + &eeprom_carrier_board { 257 + status = "okay"; 258 + }; 259 + 260 + /* Verdin ETH_1 */ 261 + &fec1 { 262 + status = "okay"; 263 + }; 264 + 265 + &gpio3 { 266 + gpio-line-names = 267 + "", /* 0 */ 268 + "", 269 + "REL3", /* SODIMM 64 */ 270 + "", 271 + "", 272 + "", 273 + "DIG_1", /* SODIMM 56 */ 274 + "DIG_2", /* SODIMM 58 */ 275 + "REL1", /* SODIMM 60 */ 276 + "REL2", /* SODIMM 62 */ 277 + "", /* 10 */ 278 + "", 279 + "", 280 + "", 281 + "REL4", /* SODIMM 66 */ 282 + "", 283 + "", 284 + "", 285 + "", 286 + "", 287 + "", /* 20 */ 288 + "", 289 + "", 290 + "", 291 + "", 292 + ""; 293 + }; 294 + 295 + &gpio5 { 296 + gpio-line-names = 297 + "", /* 0 */ 298 + "", 299 + "", 300 + "", 301 + "", 302 + "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */ 303 + "", 304 + "", 305 + "", 306 + "", 307 + "", /* 10 */ 308 + "", 309 + "", 310 + "", 311 + "", 312 + "", 313 + "", 314 + "", 315 + "", 316 + "", 317 + "", /* 20 */ 318 + "", 319 + "", 320 + "", 321 + "", 322 + "", 323 + "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */ 324 + "", 325 + "", 326 + ""; 327 + }; 328 + 329 + /* Temperature sensor on Ivy */ 330 + &hwmon_temp { 331 + compatible = "ti,tmp1075"; 332 + status = "okay"; 333 + }; 334 + 335 + /* Verdin I2C_4 CSI */ 336 + &i2c3 { 337 + status = "okay"; 338 + 339 + ivy_adc1: adc@40 { 340 + compatible = "ti,ads1119"; 341 + reg = <0x40>; 342 + pinctrl-names = "default"; 343 + pinctrl-0 = <&pinctrl_gpio7>; 344 + interrupt-parent = <&gpio1>; 345 + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 346 + avdd-supply = <&reg_3v2_ain1>; 347 + dvdd-supply = <&reg_3v2_ain1>; 348 + vref-supply = <&reg_3v2_ain1>; 349 + #address-cells = <1>; 350 + #io-channel-cells = <1>; 351 + #size-cells = <0>; 352 + 353 + /* AIN1 0-33V Voltage Input */ 354 + channel@0 { 355 + reg = <0>; 356 + diff-channels = <0 1>; 357 + }; 358 + 359 + /* AIN1 0-20mA Current Input */ 360 + channel@1 { 361 + reg = <1>; 362 + diff-channels = <2 3>; 363 + }; 364 + }; 365 + 366 + ivy_adc2: adc@41 { 367 + compatible = "ti,ads1119"; 368 + reg = <0x41>; 369 + pinctrl-names = "default"; 370 + pinctrl-0 = <&pinctrl_gpio8>; 371 + interrupt-parent = <&gpio1>; 372 + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 373 + avdd-supply = <&reg_3v2_ain2>; 374 + dvdd-supply = <&reg_3v2_ain2>; 375 + vref-supply = <&reg_3v2_ain2>; 376 + #address-cells = <1>; 377 + #io-channel-cells = <1>; 378 + #size-cells = <0>; 379 + 380 + /* AIN2 0-33V Voltage Input */ 381 + channel@0 { 382 + reg = <0>; 383 + diff-channels = <0 1>; 384 + }; 385 + 386 + /* AIN2 0-20mA Current Input */ 387 + channel@1 { 388 + reg = <1>; 389 + diff-channels = <2 3>; 390 + }; 391 + }; 392 + }; 393 + 394 + /* Verdin I2C_1 */ 395 + &i2c4 { 396 + status = "okay"; 397 + }; 398 + 399 + /* Verdin PCIE_1 */ 400 + &pcie0 { 401 + status = "okay"; 402 + }; 403 + 404 + &pcie_phy { 405 + status = "okay"; 406 + }; 407 + 408 + /* Verdin UART_3 */ 409 + &uart1 { 410 + status = "okay"; 411 + }; 412 + 413 + /* Verdin UART_1 */ 414 + &uart2 { 415 + status = "okay"; 416 + }; 417 + 418 + /* Verdin UART_2 */ 419 + &uart3 { 420 + linux,rs485-enabled-at-boot-time; 421 + rs485-rx-during-tx; 422 + status = "okay"; 423 + }; 424 + 425 + /* Verdin USB_1*/ 426 + &usbotg1 { 427 + status = "okay"; 428 + }; 429 + 430 + /* Verdin USB_2 */ 431 + &usbotg2 { 432 + status = "okay"; 433 + }; 434 + 435 + /* Verdin SD_1 */ 436 + &usdhc2 { 437 + status = "okay"; 438 + }; 439 + 440 + &iomuxc { 441 + 442 + pinctrl-names = "default"; 443 + pinctrl-0 = <&pinctrl_gpio2>, <&pinctrl_gpio3>, 444 + <&pinctrl_ivy_dig_inputs>, <&pinctrl_ivy_relays>; 445 + 446 + pinctrl_ivy_dig_inputs: ivydiginputsgrp { 447 + fsl,pins = 448 + <MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x96>, /* SODIMM 56 */ 449 + <MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x96>; /* SODIMM 58 */ 450 + }; 451 + 452 + pinctrl_ivy_leds: ivyledsgrp { 453 + fsl,pins = 454 + <MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x16>, /* SODIMM 30 */ 455 + <MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x16>, /* SODIMM 32 */ 456 + <MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x16>, /* SODIMM 34 */ 457 + <MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x16>, /* SODIMM 36 */ 458 + <MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x16>, /* SODIMM 44 */ 459 + <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16>, /* SODIMM 46 */ 460 + <MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x16>, /* SODIMM 48 */ 461 + <MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x16>; /* SODIMM 54 */ 462 + }; 463 + 464 + pinctrl_ivy_relays: ivyrelaysgrp { 465 + fsl,pins = 466 + <MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x16>, /* SODIMM 60 */ 467 + <MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x16>, /* SODIMM 62 */ 468 + <MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x16>, /* SODIMM 64 */ 469 + <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x16>; /* SODIMM 66 */ 470 + }; 471 + };
+18
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2024 Toradex 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mm-verdin.dtsi" 9 + #include "imx8mm-verdin-nonwifi.dtsi" 10 + #include "imx8mm-verdin-ivy.dtsi" 11 + 12 + / { 13 + model = "Toradex Verdin iMX8M Mini on Ivy"; 14 + compatible = "toradex,verdin-imx8mm-nonwifi-ivy", 15 + "toradex,verdin-imx8mm-nonwifi", 16 + "toradex,verdin-imx8mm", 17 + "fsl,imx8mm"; 18 + };
+18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2024 Toradex 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mm-verdin.dtsi" 9 + #include "imx8mm-verdin-wifi.dtsi" 10 + #include "imx8mm-verdin-ivy.dtsi" 11 + 12 + / { 13 + model = "Toradex Verdin iMX8M Mini WB on Ivy"; 14 + compatible = "toradex,verdin-imx8mm-wifi-ivy", 15 + "toradex,verdin-imx8mm-wifi", 16 + "toradex,verdin-imx8mm", 17 + "fsl,imx8mm"; 18 + };
+7 -2
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
··· 162 162 regulator-max-microvolt = <3300000>; 163 163 regulator-min-microvolt = <3300000>; 164 164 regulator-name = "+V3.3_SD"; 165 - startup-delay-us = <2000>; 165 + startup-delay-us = <20000>; 166 166 }; 167 167 168 168 reserved-memory { ··· 367 367 pinctrl-1 = <&pinctrl_i2c1_gpio>; 368 368 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 369 369 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 370 + single-master; 370 371 status = "okay"; 371 372 372 373 pca9450: pmic@25 { ··· 484 483 reg = <0x32>; 485 484 }; 486 485 487 - adc@49 { 486 + verdin_som_adc: adc@49 { 488 487 compatible = "ti,ads1015"; 489 488 reg = <0x49>; 490 489 #address-cells = <1>; 491 490 #size-cells = <0>; 491 + #io-channel-cells = <1>; 492 492 493 493 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 494 494 channel@0 { ··· 563 561 pinctrl-1 = <&pinctrl_i2c2_gpio>; 564 562 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 565 563 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 564 + single-master; 566 565 status = "disabled"; 567 566 }; 568 567 ··· 577 574 pinctrl-1 = <&pinctrl_i2c3_gpio>; 578 575 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 579 576 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 577 + single-master; 580 578 }; 581 579 582 580 /* Verdin I2C_1 */ ··· 588 584 pinctrl-1 = <&pinctrl_i2c4_gpio>; 589 585 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 590 586 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 587 + single-master; 591 588 592 589 gpio_expander_21: gpio-expander@21 { 593 590 compatible = "nxp,pcal6416";
+5 -3
arch/arm64/boot/dts/freescale/imx8mm.dtsi
··· 1375 1375 1376 1376 pcie0_ep: pcie-ep@33800000 { 1377 1377 compatible = "fsl,imx8mm-pcie-ep"; 1378 - reg = <0x33800000 0x400000>, 1379 - <0x18000000 0x8000000>; 1380 - reg-names = "dbi", "addr_space"; 1378 + reg = <0x33800000 0x100000>, 1379 + <0x18000000 0x8000000>, 1380 + <0x33900000 0x100000>, 1381 + <0x33b00000 0x100000>; 1382 + reg-names = "dbi", "addr_space", "dbi2", "atu"; 1381 1383 num-lanes = <1>; 1382 1384 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1383 1385 interrupt-names = "dma";
+27 -2
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso
··· 29 29 }; 30 30 }; 31 31 32 + /* 33 + * rst_usb_hub_hog and sel_usb_hub_hog have property 'output-high', 34 + * dt overlay don't support /delete-property/. Both 'output-low' and 35 + * 'output-high' will be exist under hog nodes if overlay file set 36 + * 'output-low'. Workaround is disable these hog and create new hog with 37 + * 'output-low'. 38 + */ 39 + 32 40 &rst_usb_hub_hog { 33 - output-low; 41 + status = "disabled"; 42 + }; 43 + 44 + &expander0 { 45 + rst-usb-low-hub-hog { 46 + gpio-hog; 47 + gpios = <13 0>; 48 + output-low; 49 + line-name = "RST_USB_HUB#"; 50 + }; 34 51 }; 35 52 36 53 &sel_usb_hub_hog { 37 - output-low; 54 + status = "disabled"; 55 + }; 56 + 57 + &gpio2 { 58 + sel-usb-low-hub-hog { 59 + gpio-hog; 60 + gpios = <1 GPIO_ACTIVE_HIGH>; 61 + output-low; 62 + }; 38 63 }; 39 64 40 65 &usbotg1 {
+5
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts
··· 64 64 }; 65 65 }; 66 66 67 + &mipi_dsi { 68 + samsung,burst-clock-frequency = <891000000>; 69 + samsung,esc-clock-frequency = <20000000>; 70 + }; 71 + 67 72 &sai3 { 68 73 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 69 74 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
+3 -1
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
··· 17 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; 18 18 19 19 aliases { 20 + rtc0 = &gsc_rtc; 21 + rtc1 = &snvs_rtc; 20 22 usb0 = &usbotg1; 21 23 }; 22 24 ··· 564 562 pagesize = <16>; 565 563 }; 566 564 567 - rtc@68 { 565 + gsc_rtc: rtc@68 { 568 566 compatible = "dallas,ds1672"; 569 567 reg = <0x68>; 570 568 };
+255
arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (C) 2024 Marek Vasut <marex@denx.de> 4 + * 5 + * DHCOM iMX8MP variant: 6 + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2 7 + * DHCOM PCB number: 660-100 or newer 8 + * DRC02 PCB number: 568-100 or newer 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include <dt-bindings/leds/common.h> 14 + #include <dt-bindings/phy/phy-imx8-pcie.h> 15 + #include "imx8mp-dhcom-som.dtsi" 16 + 17 + / { 18 + model = "DH electronics i.MX8M Plus DHCOM on DRC02"; 19 + compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som", 20 + "fsl,imx8mp"; 21 + 22 + chosen { 23 + stdout-path = &uart1; 24 + }; 25 + }; 26 + 27 + &eqos { /* First ethernet */ 28 + pinctrl-0 = <&pinctrl_eqos_rmii>; 29 + phy-handle = <&ethphy0f>; 30 + phy-mode = "rmii"; 31 + 32 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 33 + <&clk IMX8MP_SYS_PLL2_100M>, 34 + <&clk IMX8MP_SYS_PLL2_50M>; 35 + assigned-clock-rates = <0>, <100000000>, <50000000>; 36 + }; 37 + 38 + &ethphy0g { /* Micrel KSZ9131RNXI */ 39 + status = "disabled"; 40 + }; 41 + 42 + &ethphy0f { /* SMSC LAN8740Ai */ 43 + status = "okay"; 44 + }; 45 + 46 + &fec { /* Second ethernet */ 47 + pinctrl-0 = <&pinctrl_fec_rmii>; 48 + phy-handle = <&ethphy1f>; 49 + phy-mode = "rmii"; 50 + status = "okay"; 51 + 52 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 53 + <&clk IMX8MP_SYS_PLL2_100M>, 54 + <&clk IMX8MP_SYS_PLL2_50M>, 55 + <&clk IMX8MP_SYS_PLL2_50M>; 56 + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; 57 + }; 58 + 59 + &ethphy1f { /* SMSC LAN8740Ai */ 60 + status = "okay"; 61 + }; 62 + 63 + &flexcan1 { 64 + status = "okay"; 65 + }; 66 + 67 + &flexcan2 { 68 + status = "okay"; 69 + }; 70 + 71 + &gpio1 { 72 + gpio-line-names = 73 + "DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0", 74 + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", 75 + "", "", "", "", "", "", "", "", 76 + "", "", "", "", "", "", "", ""; 77 + 78 + /* 79 + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate 80 + * GPIO line, however the i.MX8 UART driver assumes RX happens 81 + * during TX anyway and that it only controls drive enable DE 82 + * line. Hence, the RX is always enabled here. 83 + */ 84 + rs485-rx-en-hog { 85 + gpio-hog; 86 + gpios = <13 0>; /* GPIO Q */ 87 + line-name = "rs485-rx-en"; 88 + output-low; 89 + }; 90 + }; 91 + 92 + &gpio2 { 93 + gpio-line-names = 94 + "", "", "", "", "", "", "", "", 95 + "DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "", 96 + "", "", "", "", "DRC02-In2", "", "", "", 97 + "", "", "", "", "", "", "", ""; 98 + }; 99 + 100 + &gpio3 { 101 + gpio-line-names = 102 + "", "", "", "", "", "", "", "", 103 + "", "", "", "", "", "", "SOM-HW0", "", 104 + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", 105 + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; 106 + }; 107 + 108 + &gpio4 { 109 + gpio-line-names = 110 + "", "", "", "", "", "", "", "", 111 + "", "", "", "", "", "", "", "", 112 + "", "", "", "SOM-HW1", "", "", "", "", 113 + "", "", "", "DRC02-Out2", "", "", "", ""; 114 + }; 115 + 116 + &gpio5 { 117 + gpio-line-names = 118 + "", "", "DHCOM-C", "", "", "", "", "", 119 + "", "", "", "", "", "", "", "", 120 + "", "", "", "", "", "", "DHCOM-E", "DRC02-Out1", 121 + "", "", "", "", "", "", "", ""; 122 + }; 123 + 124 + /* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */ 125 + &hdmi_blk_ctrl { 126 + status = "disabled"; 127 + }; 128 + 129 + &hdmi_pvi { 130 + status = "disabled"; 131 + }; 132 + 133 + &hdmi_tx { 134 + status = "disabled"; 135 + }; 136 + 137 + &hdmi_tx_phy { 138 + status = "disabled"; 139 + }; 140 + 141 + &i2c3 { 142 + /* Resistive touch controller not populated on this one SoM variant. */ 143 + touchscreen@49 { 144 + status = "disabled"; 145 + }; 146 + }; 147 + 148 + &irqsteer_hdmi { 149 + status = "disabled"; 150 + }; 151 + 152 + &lcdif3 { 153 + status = "disabled"; 154 + }; 155 + 156 + &pcie_phy { 157 + status = "disabled"; 158 + }; 159 + 160 + &pcie { 161 + status = "disabled"; 162 + }; 163 + 164 + /* Console UART */ 165 + &pinctrl_uart1 { 166 + fsl,pins = < 167 + /* No pull-ups on DRC02, enable in-SoC pull-ups */ 168 + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x149 169 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x149 170 + >; 171 + }; 172 + 173 + &pinctrl_uart3 { 174 + fsl,pins = < 175 + /* No pull-ups on DRC02, enable in-SoC pull-ups */ 176 + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x149 177 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x149 178 + >; 179 + }; 180 + 181 + &uart1 { 182 + /* 183 + * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to 184 + * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs 185 + * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS. 186 + */ 187 + /delete-property/ uart-has-rtscts; 188 + cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */ 189 + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; 190 + pinctrl-names = "default"; 191 + rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ 192 + }; 193 + 194 + &uart3 { 195 + /* 196 + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is 197 + * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property 198 + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via 199 + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 200 + * node above. 201 + */ 202 + /delete-property/ uart-has-rtscts; 203 + linux,rs485-enabled-at-boot-time; 204 + pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>; 205 + pinctrl-names = "default"; 206 + rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */ 207 + }; 208 + 209 + /* No WiFi/BT chipset on this SoM variant. */ 210 + &uart2 { 211 + bluetooth { 212 + status = "disabled"; 213 + }; 214 + }; 215 + 216 + /* USB_OTG port is not routed out on DRC02. */ 217 + &usb3_0 { 218 + status = "disabled"; 219 + }; 220 + 221 + &usb_dwc3_0 { 222 + status = "disabled"; 223 + }; 224 + 225 + /* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ 226 + &usb3_1 { 227 + fsl,disable-port-power-control; 228 + fsl,permanently-attached; 229 + }; 230 + 231 + &usb_dwc3_1 { 232 + dr_mode = "host"; 233 + maximum-speed = "high-speed"; 234 + }; 235 + 236 + /* No WiFi/BT chipset on this SoM variant. */ 237 + &usdhc1 { 238 + status = "disabled"; 239 + }; 240 + 241 + &iomuxc { 242 + /* 243 + * GPIO I is connected to UART1_RTS 244 + * GPIO M is connected to UART1_CTS 245 + * GPIO P is connected to RS485_TX_En 246 + * GPIO Q is connected to RS485_RX_En 247 + */ 248 + pinctrl-0 = <&pinctrl_hog_base 249 + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 250 + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 251 + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j 252 + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n 253 + &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s 254 + &pinctrl_dhcom_int>; 255 + };
+176
arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (C) 2023-2024 Marek Vasut <marex@denx.de> 4 + * 5 + * DHCOM iMX8MP variant: 6 + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2 7 + * DHCOM PCB number: 660-200 or newer 8 + * PicoITX PCB number: 487-600 or newer 9 + */ 10 + 11 + /dts-v1/; 12 + 13 + #include <dt-bindings/leds/common.h> 14 + #include "imx8mp-dhcom-som.dtsi" 15 + 16 + / { 17 + model = "DH electronics i.MX8M Plus DHCOM PicoITX"; 18 + compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som", 19 + "fsl,imx8mp"; 20 + 21 + chosen { 22 + stdout-path = &uart1; 23 + }; 24 + 25 + led { 26 + compatible = "gpio-leds"; 27 + 28 + led-0 { 29 + color = <LED_COLOR_ID_YELLOW>; 30 + default-state = "off"; 31 + function = LED_FUNCTION_INDICATOR; 32 + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ 33 + pinctrl-0 = <&pinctrl_dhcom_i>; 34 + pinctrl-names = "default"; 35 + }; 36 + }; 37 + }; 38 + 39 + &eqos { /* First ethernet */ 40 + pinctrl-0 = <&pinctrl_eqos_rmii>; 41 + phy-handle = <&ethphy0f>; 42 + phy-mode = "rmii"; 43 + 44 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 45 + <&clk IMX8MP_SYS_PLL2_100M>, 46 + <&clk IMX8MP_SYS_PLL2_50M>; 47 + assigned-clock-rates = <0>, <100000000>, <50000000>; 48 + }; 49 + 50 + &ethphy0g { /* Micrel KSZ9131RNXI */ 51 + status = "disabled"; 52 + }; 53 + 54 + &ethphy0f { /* SMSC LAN8740Ai */ 55 + status = "okay"; 56 + }; 57 + 58 + &fec { 59 + status = "disabled"; 60 + }; 61 + 62 + &flexcan1 { 63 + status = "okay"; 64 + }; 65 + 66 + &gpio1 { 67 + gpio-line-names = 68 + "DHCOM-G", "", "", "", 69 + "", "DHCOM-I", "PicoITX-HW0", "PicoITX-HW2", 70 + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", 71 + "", "", "", "", "", "", "", "", 72 + "", "", "", "", "", "", "", ""; 73 + }; 74 + 75 + &gpio2 { 76 + gpio-line-names = 77 + "", "", "", "", "", "", "", "", 78 + "", "", "", "PicoITX-HW1", "", "", "", "", 79 + "", "", "", "", "DHCOM-INT", "", "", "", 80 + "", "", "", "", "", "", "", ""; 81 + }; 82 + 83 + &gpio4 { 84 + gpio-line-names = 85 + "", "", "", "", "", "", "", "", 86 + "", "", "", "", "", "", "", "", 87 + "", "", "", "SOM-HW1", "", "", "", "", 88 + "", "", "", "PicoITX-Out2", "", "", "", ""; 89 + }; 90 + 91 + &gpio5 { 92 + gpio-line-names = 93 + "", "", "PicoITX-In2", "", "", "", "", "", 94 + "", "", "", "", "", "", "", "", 95 + "", "", "", "", 96 + "", "", "PicoITX-In1", "PicoITX-Out1", 97 + "", "", "", "", "", "", "", ""; 98 + }; 99 + 100 + /* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */ 101 + &hdmi_blk_ctrl { 102 + status = "disabled"; 103 + }; 104 + 105 + &hdmi_pvi { 106 + status = "disabled"; 107 + }; 108 + 109 + &hdmi_tx { 110 + status = "disabled"; 111 + }; 112 + 113 + &hdmi_tx_phy { 114 + status = "disabled"; 115 + }; 116 + 117 + &irqsteer_hdmi { 118 + status = "disabled"; 119 + }; 120 + 121 + &lcdif3 { 122 + status = "disabled"; 123 + }; 124 + 125 + &pcie_phy { 126 + status = "disabled"; 127 + }; 128 + 129 + &pcie { 130 + status = "disabled"; 131 + }; 132 + 133 + /* No WiFi/BT chipset on this SoM variant. */ 134 + &uart2 { 135 + bluetooth { 136 + status = "disabled"; 137 + }; 138 + }; 139 + 140 + /* USB_OTG port is not routed out on PicoITX. */ 141 + &usb3_0 { 142 + status = "disabled"; 143 + }; 144 + 145 + &usb_dwc3_0 { 146 + status = "disabled"; 147 + }; 148 + 149 + &usb3_1 { 150 + fsl,over-current-active-low; 151 + }; 152 + 153 + &usb_dwc3_1 { 154 + dr_mode = "host"; 155 + maximum-speed = "high-speed"; 156 + }; 157 + 158 + /* No WiFi/BT chipset on this SoM variant. */ 159 + &usdhc1 { 160 + status = "disabled"; 161 + }; 162 + 163 + &iomuxc { 164 + /* 165 + * The following DHCOM GPIOs are used on this board. 166 + * Therefore, they have been removed from the list below. 167 + * I: yellow led 168 + */ 169 + pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 170 + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 171 + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j 172 + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_m 173 + &pinctrl_dhcom_n &pinctrl_dhcom_o &pinctrl_dhcom_p 174 + &pinctrl_dhcom_q &pinctrl_dhcom_r &pinctrl_dhcom_s 175 + &pinctrl_dhcom_int>; 176 + };
+17
arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2024 NXP 4 + */ 5 + 6 + /dts-v1/; 7 + /plugin/; 8 + 9 + &pcie { 10 + status = "disabled"; 11 + }; 12 + 13 + &pcie_ep { 14 + pinctrl-0 = <&pinctrl_pcie0>; 15 + pinctrl-names = "default"; 16 + status = "okay"; 17 + };
+423
arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Y Soft 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp.dtsi" 9 + 10 + / { 11 + compatible = "ysoft,imx8mp-iota2-lumpy", "fsl,imx8mp"; 12 + model = "Y Soft i.MX8MPlus IOTA2 Lumpy board"; 13 + 14 + beeper { 15 + compatible = "pwm-beeper"; 16 + pwms = <&pwm4 0 500000 0>; 17 + }; 18 + 19 + chosen { 20 + stdout-path = &uart2; 21 + }; 22 + 23 + gpio_keys: gpio-keys { 24 + compatible = "gpio-keys"; 25 + pinctrl-0 = <&pinctrl_gpio_keys>; 26 + pinctrl-names = "default"; 27 + 28 + button-reset { 29 + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 30 + label = "Factory RESET"; 31 + linux,code = <BTN_0>; 32 + }; 33 + }; 34 + 35 + reg_usb_host: regulator-usb-host { 36 + compatible = "regulator-fixed"; 37 + pinctrl-0 = <&pinctrl_usb_host_vbus>; 38 + pinctrl-names = "default"; 39 + regulator-max-microvolt = <5000000>; 40 + regulator-min-microvolt = <5000000>; 41 + regulator-name = "usb-host"; 42 + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 43 + enable-active-high; 44 + }; 45 + 46 + memory@40000000 { 47 + reg = <0x0 0x40000000 0 0x80000000>, 48 + <0x1 0x00000000 0 0x80000000>; 49 + device_type = "memory"; 50 + }; 51 + }; 52 + 53 + &A53_0 { 54 + cpu-supply = <&reg_arm>; 55 + }; 56 + 57 + &A53_1 { 58 + cpu-supply = <&reg_arm>; 59 + }; 60 + 61 + &A53_2 { 62 + cpu-supply = <&reg_arm>; 63 + }; 64 + 65 + &A53_3 { 66 + cpu-supply = <&reg_arm>; 67 + }; 68 + 69 + &eqos { 70 + phy-handle = <&ethphy0>; 71 + phy-mode = "rgmii-id"; 72 + pinctrl-0 = <&pinctrl_eqos>; 73 + pinctrl-names = "default"; 74 + status = "okay"; 75 + 76 + mdio { 77 + compatible = "snps,dwmac-mdio"; 78 + #address-cells = <1>; 79 + #size-cells = <0>; 80 + 81 + ethphy0: ethernet-phy@0 { 82 + reg = <0>; 83 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 84 + interrupt-parent = <&gpio3>; 85 + pinctrl-0 = <&pinctrl_ethphy0>; 86 + pinctrl-names = "default"; 87 + reset-assert-us = <1000>; 88 + reset-deassert-us = <1000>; 89 + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 90 + micrel,led-mode = <0>; 91 + }; 92 + }; 93 + }; 94 + 95 + &fec { 96 + fsl,magic-packet; 97 + phy-handle = <&ethphy1>; 98 + phy-mode = "rgmii-id"; 99 + pinctrl-0 = <&pinctrl_fec>; 100 + pinctrl-names = "default"; 101 + status = "okay"; 102 + 103 + mdio { 104 + #address-cells = <1>; 105 + #size-cells = <0>; 106 + 107 + ethphy1: ethernet-phy@0 { 108 + reg = <0>; 109 + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 110 + interrupt-parent = <&gpio3>; 111 + pinctrl-0 = <&pinctrl_ethphy1>; 112 + pinctrl-names = "default"; 113 + reset-assert-us = <1000>; 114 + reset-deassert-us = <1000>; 115 + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 116 + micrel,led-mode = <0>; 117 + }; 118 + }; 119 + }; 120 + 121 + &i2c1 { 122 + clock-frequency = <400000>; 123 + pinctrl-0 = <&pinctrl_i2c1>; 124 + pinctrl-names = "default"; 125 + status = "okay"; 126 + 127 + pmic@25 { 128 + compatible = "nxp,pca9450c"; 129 + reg = <0x25>; 130 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 131 + interrupt-parent = <&gpio1>; 132 + pinctrl-0 = <&pinctrl_pmic>; 133 + pinctrl-names = "default"; 134 + 135 + regulators { 136 + BUCK1 { 137 + regulator-always-on; 138 + regulator-boot-on; 139 + regulator-max-microvolt = <1000000>; 140 + regulator-min-microvolt = <720000>; 141 + regulator-name = "BUCK1"; 142 + regulator-ramp-delay = <3125>; 143 + }; 144 + 145 + reg_arm: BUCK2 { 146 + nxp,dvs-run-voltage = <950000>; 147 + nxp,dvs-standby-voltage = <850000>; 148 + regulator-always-on; 149 + regulator-boot-on; 150 + regulator-max-microvolt = <1025000>; 151 + regulator-min-microvolt = <720000>; 152 + regulator-name = "BUCK2"; 153 + regulator-ramp-delay = <3125>; 154 + }; 155 + 156 + BUCK4 { 157 + regulator-always-on; 158 + regulator-boot-on; 159 + regulator-max-microvolt = <3600000>; 160 + regulator-min-microvolt = <3000000>; 161 + regulator-name = "BUCK4"; 162 + }; 163 + 164 + BUCK5 { 165 + regulator-always-on; 166 + regulator-boot-on; 167 + regulator-max-microvolt = <1950000>; 168 + regulator-min-microvolt = <1650000>; 169 + regulator-name = "BUCK5"; 170 + }; 171 + 172 + BUCK6 { 173 + regulator-always-on; 174 + regulator-boot-on; 175 + regulator-max-microvolt = <1155000>; 176 + regulator-min-microvolt = <1045000>; 177 + regulator-name = "BUCK6"; 178 + }; 179 + 180 + LDO1 { 181 + regulator-always-on; 182 + regulator-boot-on; 183 + regulator-max-microvolt = <1950000>; 184 + regulator-min-microvolt = <1650000>; 185 + regulator-name = "LDO1"; 186 + }; 187 + 188 + LDO3 { 189 + regulator-always-on; 190 + regulator-boot-on; 191 + regulator-max-microvolt = <1890000>; 192 + regulator-min-microvolt = <1710000>; 193 + regulator-name = "LDO3"; 194 + }; 195 + 196 + LDO4 { 197 + regulator-always-on; 198 + regulator-boot-on; 199 + regulator-max-microvolt = <950000>; 200 + regulator-min-microvolt = <850000>; 201 + regulator-name = "LDO4"; 202 + }; 203 + 204 + LDO5 { 205 + regulator-always-on; 206 + regulator-boot-on; 207 + regulator-max-microvolt = <3300000>; 208 + regulator-min-microvolt = <1800000>; 209 + regulator-name = "LDO5"; 210 + }; 211 + }; 212 + }; 213 + }; 214 + 215 + &i2c2 { 216 + clock-frequency = <400000>; 217 + pinctrl-0 = <&pinctrl_i2c2>; 218 + pinctrl-names = "default"; 219 + status = "okay"; 220 + 221 + rtc: rtc@68 { 222 + compatible = "dallas,ds1341"; 223 + reg = <0x68>; 224 + }; 225 + }; 226 + 227 + &pwm4 { 228 + pinctrl-0 = <&pinctrl_pwm4>; 229 + pinctrl-names = "default"; 230 + status = "okay"; 231 + }; 232 + 233 + &uart2 { 234 + pinctrl-0 = <&pinctrl_uart2>; 235 + pinctrl-names = "default"; 236 + status = "okay"; 237 + }; 238 + 239 + &usb3_1 { 240 + status = "okay"; 241 + }; 242 + 243 + &usb3_phy1 { 244 + vbus-supply = <&reg_usb_host>; 245 + status = "okay"; 246 + }; 247 + 248 + &usb_dwc3_1 { 249 + dr_mode = "host"; 250 + status = "okay"; 251 + }; 252 + 253 + &usdhc3 { 254 + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 255 + assigned-clock-rates = <400000000>; 256 + pinctrl-0 = <&pinctrl_usdhc3>; 257 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 258 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 259 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 260 + bus-width = <8>; 261 + non-removable; 262 + status = "okay"; 263 + }; 264 + 265 + &wdog1 { 266 + pinctrl-0 = <&pinctrl_wdog>; 267 + pinctrl-names = "default"; 268 + fsl,ext-reset-output; 269 + status = "okay"; 270 + }; 271 + 272 + &iomuxc { 273 + pinctrl_eqos: eqosgrp { 274 + fsl,pins = < 275 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 276 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 277 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 278 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 279 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 280 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 281 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 282 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 283 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 284 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 285 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 286 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 287 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 288 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 289 + >; 290 + }; 291 + 292 + pinctrl_ethphy0: ethphy0grp { 293 + fsl,pins = < 294 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x10 295 + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x10 296 + >; 297 + }; 298 + 299 + pinctrl_ethphy1: ethphy1grp { 300 + fsl,pins = < 301 + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10 302 + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10 303 + >; 304 + }; 305 + 306 + pinctrl_fec: fecgrp { 307 + fsl,pins = < 308 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 309 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 310 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 311 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 312 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 313 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 314 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 315 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 316 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 317 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 318 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 319 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 320 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 321 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 322 + >; 323 + }; 324 + 325 + pinctrl_gpio_keys: gpiokeysgrp { 326 + fsl,pins = < 327 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80 328 + >; 329 + }; 330 + 331 + pinctrl_i2c1: i2c1grp { 332 + fsl,pins = < 333 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 334 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 335 + >; 336 + }; 337 + 338 + pinctrl_i2c2: i2c2grp { 339 + fsl,pins = < 340 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 341 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 342 + >; 343 + }; 344 + 345 + pinctrl_pmic: pmicgrp { 346 + fsl,pins = < 347 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 348 + >; 349 + }; 350 + 351 + pinctrl_pwm4: pwm4grp { 352 + fsl,pins = < 353 + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x102 354 + >; 355 + }; 356 + 357 + pinctrl_uart2: uart2grp { 358 + fsl,pins = < 359 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x0 360 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x0 361 + >; 362 + }; 363 + 364 + pinctrl_usb_host_vbus: usb1grp { 365 + fsl,pins = < 366 + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x0 367 + >; 368 + }; 369 + 370 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 371 + fsl,pins = < 372 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 373 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 374 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 375 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 376 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 377 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 378 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 379 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 380 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 381 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 382 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 383 + >; 384 + }; 385 + 386 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 387 + fsl,pins = < 388 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 389 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 390 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 391 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 392 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 393 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 394 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 395 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 396 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 397 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 398 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 399 + >; 400 + }; 401 + 402 + pinctrl_usdhc3: usdhc3grp { 403 + fsl,pins = < 404 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 405 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 406 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 407 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 408 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 409 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 410 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 411 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 412 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 413 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 414 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 415 + >; 416 + }; 417 + 418 + pinctrl_wdog: wdoggrp { 419 + fsl,pins = < 420 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 421 + >; 422 + }; 423 + };
+305
arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Copyright (C) 2022 Kontron Electronics GmbH 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp-kontron-osm-s.dtsi" 9 + 10 + / { 11 + model = "Kontron BL i.MX8MP OSM-S"; 12 + compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp"; 13 + 14 + aliases { 15 + ethernet0 = &fec; 16 + ethernet1 = &eqos; 17 + }; 18 + 19 + extcon_usbc: usbc { 20 + compatible = "linux,extcon-usb-gpio"; 21 + pinctrl-names = "default"; 22 + pinctrl-0 = <&pinctrl_usb1_id>; 23 + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 24 + }; 25 + 26 + leds { 27 + compatible = "gpio-leds"; 28 + 29 + led1 { 30 + label = "led1"; 31 + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 32 + linux,default-trigger = "heartbeat"; 33 + }; 34 + }; 35 + 36 + pwm-beeper { 37 + compatible = "pwm-beeper"; 38 + pwms = <&pwm2 0 5000 0>; 39 + }; 40 + 41 + reg_vcc_panel: regulator-vcc-panel { 42 + compatible = "regulator-fixed"; 43 + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; 44 + enable-active-high; 45 + regulator-max-microvolt = <3300000>; 46 + regulator-min-microvolt = <3300000>; 47 + regulator-name = "VCC_PANEL"; 48 + }; 49 + }; 50 + 51 + &ecspi2 { 52 + status = "okay"; 53 + 54 + eeram@0 { 55 + compatible = "microchip,48l640"; 56 + reg = <0>; 57 + spi-max-frequency = <20000000>; 58 + }; 59 + }; 60 + 61 + &eqos { /* Second ethernet (OSM-S ETH_B) */ 62 + pinctrl-names = "default"; 63 + pinctrl-0 = <&pinctrl_eqos_rgmii>; 64 + phy-mode = "rgmii-id"; 65 + phy-handle = <&ethphy1>; 66 + status = "okay"; 67 + 68 + mdio { 69 + compatible = "snps,dwmac-mdio"; 70 + #address-cells = <1>; 71 + #size-cells = <0>; 72 + 73 + ethphy1: ethernet-phy@1 { 74 + compatible = "ethernet-phy-id4f51.e91b"; 75 + reg = <1>; 76 + pinctrl-0 = <&pinctrl_ethphy1>; 77 + pinctrl-names = "default"; 78 + reset-assert-us = <10000>; 79 + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 80 + }; 81 + }; 82 + }; 83 + 84 + &fec { /* First ethernet (OSM-S ETH_A) */ 85 + pinctrl-names = "default"; 86 + pinctrl-0 = <&pinctrl_enet_rgmii>; 87 + phy-connection-type = "rgmii-id"; 88 + phy-handle = <&ethphy0>; 89 + status = "okay"; 90 + 91 + mdio { 92 + #address-cells = <1>; 93 + #size-cells = <0>; 94 + 95 + ethphy0: ethernet-phy@1 { 96 + compatible = "ethernet-phy-id4f51.e91b"; 97 + reg = <1>; 98 + pinctrl-0 = <&pinctrl_ethphy0>; 99 + pinctrl-names = "default"; 100 + reset-assert-us = <10000>; 101 + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 102 + }; 103 + }; 104 + }; 105 + 106 + &flexcan1 { 107 + status = "okay"; 108 + }; 109 + 110 + /* 111 + * Rename SoM signals according to board usage: 112 + * SDIO_A_PWR_EN -> CAN_ADDR2 113 + * SDIO_A_WP -> CAN_ADDR3 114 + */ 115 + &gpio2 { 116 + pinctrl-names = "default"; 117 + pinctrl-0 = <&pinctrl_gpio2>; 118 + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", 119 + "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", 120 + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2", 121 + "CAN_ADDR3"; 122 + }; 123 + 124 + /* 125 + * Rename SoM signals according to board usage: 126 + * SPI_A_WP -> CAN_ADDR0 127 + * SPI_A_HOLD -> CAN_ADDR1 128 + * GPIO_B_0 -> DIO1_OUT 129 + * GPIO_B_1 -> DIO2_OUT 130 + */ 131 + &gpio3 { 132 + gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5", 133 + "SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1", 134 + "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1", 135 + "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4", 136 + "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT", 137 + "DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1", 138 + "", "", "SDIO_B_CD", "SDIO_B_PWR_EN", 139 + "HDMI_CEC", "HDMI_HPD"; 140 + }; 141 + 142 + /* 143 + * Rename SoM signals according to board usage: 144 + * GPIO_B_5 -> DIO2_IN 145 + * GPIO_B_6 -> DIO3_IN 146 + * GPIO_B_7 -> DIO4_IN 147 + * GPIO_B_3 -> DIO4_OUT 148 + * GPIO_B_4 -> DIO1_IN 149 + * GPIO_B_2 -> DIO3_OUT 150 + */ 151 + &gpio4 { 152 + gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0", 153 + "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", 154 + "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", 155 + "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", 156 + "ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN", 157 + "DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS", 158 + "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX", 159 + "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; 160 + }; 161 + 162 + &hdmi_pvi { 163 + status = "okay"; 164 + }; 165 + 166 + &hdmi_tx { 167 + pinctrl-names = "default"; 168 + pinctrl-0 = <&pinctrl_hdmi>; 169 + ddc-i2c-bus = <&i2c2>; 170 + status = "okay"; 171 + }; 172 + 173 + &hdmi_tx_phy { 174 + status = "okay"; 175 + }; 176 + 177 + &i2c1 { 178 + status = "okay"; 179 + 180 + gpio_expander_dio: io-expander@20 { 181 + compatible = "ti,tca6408"; 182 + reg = <0x20>; 183 + gpio-controller; 184 + #gpio-cells = <2>; 185 + gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN", 186 + "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN"; 187 + interrupt-parent = <&gpio3>; 188 + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; 189 + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 190 + }; 191 + }; 192 + 193 + &i2c2 { 194 + status = "okay"; 195 + }; 196 + 197 + &i2c4 { 198 + status = "okay"; 199 + }; 200 + 201 + &lcdif3 { 202 + status = "okay"; 203 + }; 204 + 205 + &pwm2 { 206 + status = "okay"; 207 + }; 208 + 209 + &reg_usdhc2_vcc { 210 + status = "disabled"; 211 + }; 212 + 213 + &snvs_pwrkey { 214 + status = "okay"; 215 + }; 216 + 217 + &uart1 { 218 + uart-has-rtscts; 219 + status = "okay"; 220 + }; 221 + 222 + &uart4 { 223 + linux,rs485-enabled-at-boot-time; 224 + uart-has-rtscts; 225 + status = "okay"; 226 + }; 227 + 228 + &usb_dwc3_0 { 229 + adp-disable; 230 + hnp-disable; 231 + srp-disable; 232 + dr_mode = "otg"; 233 + extcon = <&extcon_usbc>; 234 + usb-role-switch; 235 + status = "okay"; 236 + }; 237 + 238 + &usb_dwc3_1 { 239 + pinctrl-names = "default"; 240 + pinctrl-0 = <&pinctrl_usb_hub>; 241 + #address-cells = <1>; 242 + #size-cells = <0>; 243 + dr_mode = "host"; 244 + status = "okay"; 245 + 246 + usb-hub@1 { 247 + compatible = "usb424,2514"; 248 + reg = <1>; 249 + reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; 250 + }; 251 + }; 252 + 253 + &usb3_0 { 254 + status = "okay"; 255 + }; 256 + 257 + &usb3_1 { 258 + fsl,disable-port-power-control; 259 + fsl,permanently-attached; 260 + status = "okay"; 261 + }; 262 + 263 + &usb3_phy0 { 264 + vbus-supply = <&reg_usb1_vbus>; 265 + status = "okay"; 266 + }; 267 + 268 + &usb3_phy1 { 269 + status = "okay"; 270 + }; 271 + 272 + &usdhc2 { 273 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 274 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 275 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 276 + vmmc-supply = <&reg_vdd_3v3>; 277 + status = "okay"; 278 + }; 279 + 280 + &iomuxc { 281 + pinctrl_ethphy0: ethphy0grp { 282 + fsl,pins = < 283 + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46 284 + >; 285 + }; 286 + 287 + pinctrl_ethphy1: ethphy1grp { 288 + fsl,pins = < 289 + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46 290 + >; 291 + }; 292 + 293 + pinctrl_gpio2: gpio2grp { 294 + fsl,pins = < 295 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x46 296 + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46 297 + >; 298 + }; 299 + 300 + pinctrl_usb_hub: usbhubgrp { 301 + fsl,pins = < 302 + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46 303 + >; 304 + }; 305 + };
+111
arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Copyright (C) 2023 Kontron Electronics GmbH 4 + */ 5 + 6 + /dts-v1/; 7 + /plugin/; 8 + 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include "imx8mp-pinfunc.h" 11 + 12 + &{/} { 13 + model = "Kontron DL i.MX8MP OSM-S"; 14 + compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp"; 15 + 16 + backlight: backlight { 17 + compatible = "pwm-backlight"; 18 + pwms = <&pwm1 0 50000 0>; 19 + brightness-levels = <0 100>; 20 + num-interpolated-steps = <100>; 21 + default-brightness-level = <100>; 22 + }; 23 + 24 + panel { 25 + compatible = "jenson,bl-jt60050-01a", "panel-lvds"; 26 + backlight = <&backlight>; 27 + data-mapping = "vesa-24"; 28 + enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 29 + power-supply = <&reg_vcc_panel>; 30 + height-mm = <86>; 31 + width-mm = <154>; 32 + 33 + panel-timing { 34 + clock-frequency = <50000000>; 35 + hactive = <1024>; 36 + hback-porch = <160>; 37 + hfront-porch = <160>; 38 + hsync-len = <1>; 39 + vactive = <600>; 40 + vback-porch = <23>; 41 + vfront-porch = <12>; 42 + vsync-len = <1>; 43 + }; 44 + 45 + port { 46 + panel_in_lvds0: endpoint { 47 + remote-endpoint = <&ldb_lvds_ch0>; 48 + }; 49 + }; 50 + }; 51 + }; 52 + 53 + &gpio4 { 54 + pinctrl-names = "default"; 55 + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_panel_stby>; 56 + 57 + panel-rst-hog { 58 + gpio-hog; 59 + gpios = <21 GPIO_ACTIVE_HIGH>; 60 + output-high; 61 + line-name = "panel-reset"; 62 + }; 63 + 64 + panel-stby-hog { 65 + gpio-hog; 66 + gpios = <28 GPIO_ACTIVE_HIGH>; 67 + output-high; 68 + line-name = "panel-standby"; 69 + }; 70 + }; 71 + 72 + &i2c1 { 73 + #address-cells = <1>; 74 + #size-cells = <0>; 75 + status = "okay"; 76 + 77 + touchscreen@5d { 78 + compatible = "goodix,gt928"; 79 + reg = <0x5d>; 80 + interrupt-parent = <&gpio1>; 81 + interrupts = <6 8>; 82 + irq-gpios = <&gpio1 6 0>; 83 + AVDD28-supply = <&reg_vcc_panel>; 84 + VDDIO-supply = <&reg_vcc_panel>; 85 + reset-gpios = <&gpio1 7 0>; 86 + }; 87 + }; 88 + 89 + &lcdif2 { 90 + status = "okay"; 91 + }; 92 + 93 + &ldb_lvds_ch0 { 94 + remote-endpoint = <&panel_in_lvds0>; 95 + }; 96 + 97 + &lvds_bridge { 98 + status = "okay"; 99 + }; 100 + 101 + &pwm1 { 102 + status = "okay"; 103 + }; 104 + 105 + &iomuxc { 106 + pinctrl_panel_stby: panelstbygrp { 107 + fsl,pins = < 108 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19 109 + >; 110 + }; 111 + };
+908
arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Copyright (C) 2022 Kontron Electronics GmbH 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/irq.h> 7 + #include "imx8mp.dtsi" 8 + 9 + / { 10 + model = "Kontron OSM-S i.MX8MP"; 11 + compatible = "kontron,imx8mp-osm-s", "fsl,imx8mp"; 12 + 13 + aliases { 14 + rtc0 = &rv3028; 15 + rtc1 = &snvs_rtc; 16 + }; 17 + 18 + memory@40000000 { 19 + device_type = "memory"; 20 + /* 21 + * There are multiple SoM flavors with different DDR sizes. 22 + * The smallest is 1GB. For larger sizes the bootloader will 23 + * update the reg property. 24 + */ 25 + reg = <0x0 0x40000000 0 0x80000000>; 26 + }; 27 + 28 + chosen { 29 + stdout-path = &uart3; 30 + }; 31 + 32 + reg_usb1_vbus: regulator-usb1-vbus { 33 + compatible = "regulator-fixed"; 34 + pinctrl-names = "default"; 35 + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; 36 + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 37 + enable-active-high; 38 + regulator-min-microvolt = <5000000>; 39 + regulator-max-microvolt = <5000000>; 40 + regulator-name = "VBUS_USB_A"; 41 + }; 42 + 43 + reg_usb2_vbus: regulator-usb2-vbus { 44 + compatible = "regulator-fixed"; 45 + pinctrl-names = "default"; 46 + pinctrl-0 = <&pinctrl_reg_usb2_vbus>; 47 + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 48 + enable-active-high; 49 + regulator-min-microvolt = <5000000>; 50 + regulator-max-microvolt = <5000000>; 51 + regulator-name = "VBUS_USB_B"; 52 + }; 53 + 54 + reg_usdhc2_vcc: regulator-usdhc2-vcc { 55 + compatible = "regulator-fixed"; 56 + pinctrl-names = "default"; 57 + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; 58 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 59 + enable-active-high; 60 + regulator-min-microvolt = <3300000>; 61 + regulator-max-microvolt = <3300000>; 62 + regulator-name = "VCC_SDIO_A"; 63 + }; 64 + 65 + reg_usdhc3_vcc: regulator-usdhc3-vcc { 66 + compatible = "regulator-fixed"; 67 + pinctrl-names = "default"; 68 + pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; 69 + gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; 70 + enable-active-high; 71 + regulator-min-microvolt = <3300000>; 72 + regulator-max-microvolt = <3300000>; 73 + regulator-name = "VCC_SDIO_B"; 74 + }; 75 + 76 + reg_vdd_carrier: regulator-vdd-carrier { 77 + compatible = "regulator-fixed"; 78 + pinctrl-names = "default"; 79 + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; 80 + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; 81 + enable-active-high; 82 + regulator-always-on; 83 + regulator-boot-on; 84 + regulator-name = "VDD_CARRIER"; 85 + 86 + regulator-state-standby { 87 + regulator-on-in-suspend; 88 + }; 89 + 90 + regulator-state-mem { 91 + regulator-off-in-suspend; 92 + }; 93 + 94 + regulator-state-disk { 95 + regulator-off-in-suspend; 96 + }; 97 + }; 98 + }; 99 + 100 + &A53_0 { 101 + cpu-supply = <&reg_vdd_arm>; 102 + }; 103 + 104 + &A53_1 { 105 + cpu-supply = <&reg_vdd_arm>; 106 + }; 107 + 108 + &A53_2 { 109 + cpu-supply = <&reg_vdd_arm>; 110 + }; 111 + 112 + &A53_3 { 113 + cpu-supply = <&reg_vdd_arm>; 114 + }; 115 + 116 + &ecspi1 { /* OSM-S SPI_A */ 117 + pinctrl-names = "default"; 118 + pinctrl-0 = <&pinctrl_ecspi1>; 119 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 120 + }; 121 + 122 + &ecspi2 { /* OSM-S SPI_B */ 123 + pinctrl-names = "default"; 124 + pinctrl-0 = <&pinctrl_ecspi2>; 125 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 126 + }; 127 + 128 + &flexcan1 { /* OSM-S CAN_A */ 129 + pinctrl-names = "default"; 130 + pinctrl-0 = <&pinctrl_flexcan1>; 131 + }; 132 + 133 + &flexcan2 { /* OSM-S CAN_B */ 134 + pinctrl-names = "default"; 135 + pinctrl-0 = <&pinctrl_flexcan2>; 136 + }; 137 + 138 + &gpio1 { 139 + pinctrl-names = "default"; 140 + pinctrl-0 = <&pinctrl_gpio1>; 141 + gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "", 142 + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", 143 + "GPIO_A_5", "USB_B_EN", "USB_A_ID", "USB_B_ID", 144 + "USB_A_EN", "USB_A_OC","CAM_MCK", "USB_B_OC", 145 + "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2", 146 + "ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK", 147 + "ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1", 148 + "ETH_B_RXD2", "ETH_B_RXD3"; 149 + }; 150 + 151 + &gpio2 { 152 + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", 153 + "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", 154 + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", 155 + "SDIO_A_WP"; 156 + }; 157 + 158 + &gpio3 { 159 + pinctrl-names = "default"; 160 + pinctrl-0 = <&pinctrl_gpio3>; 161 + gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5", 162 + "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD", 163 + "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1", 164 + "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4", 165 + "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_0", 166 + "GPIO_B_1", "", "BOOT_SEL0", "BOOT_SEL1", 167 + "", "", "SDIO_B_CD", "SDIO_B_PWR_EN", 168 + "HDMI_CEC", "HDMI_HPD"; 169 + }; 170 + 171 + &gpio4 { 172 + pinctrl-names = "default"; 173 + pinctrl-0 = <&pinctrl_gpio4>; 174 + gpio-line-names = "GPIO_B_5", "GPIO_B_6", "GPIO_B_7", "GPIO_C_0", 175 + "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", 176 + "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", 177 + "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", 178 + "ETH_A_TX_EN", "ETH_A_TX_CLK", "GPIO_B_3", "GPIO_B_4", 179 + "GPIO_B_2", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS", 180 + "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX", 181 + "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; 182 + }; 183 + 184 + &gpio5 { 185 + gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2", 186 + "PWM_1", "PWM_0", "SPI_A_SCK", "SPI_A_SDO", 187 + "SPI_A_SDI", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO", 188 + "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA", 189 + "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT", 190 + "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX", 191 + "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX", 192 + "UART_B_RX", "UART_B_TX"; 193 + }; 194 + 195 + &i2c1 { /* OSM-S I2C_A */ 196 + clock-frequency = <400000>; 197 + pinctrl-names = "default", "gpio"; 198 + pinctrl-0 = <&pinctrl_i2c1>; 199 + pinctrl-1 = <&pinctrl_i2c1_gpio>; 200 + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 201 + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 202 + }; 203 + 204 + &i2c2 { /* OSM-S I2C_B */ 205 + clock-frequency = <400000>; 206 + pinctrl-names = "default", "gpio"; 207 + pinctrl-0 = <&pinctrl_i2c2>; 208 + pinctrl-1 = <&pinctrl_i2c2_gpio>; 209 + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 210 + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 211 + }; 212 + 213 + &i2c3 { /* OSM-S PCIe SMDAT/SMCLK */ 214 + clock-frequency = <400000>; 215 + pinctrl-names = "default", "gpio"; 216 + pinctrl-0 = <&pinctrl_i2c3>; 217 + pinctrl-1 = <&pinctrl_i2c3_gpio>; 218 + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 219 + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 220 + }; 221 + 222 + &i2c4 { /* OSM-S I2C_CAM */ 223 + clock-frequency = <400000>; 224 + pinctrl-names = "default", "gpio"; 225 + pinctrl-0 = <&pinctrl_i2c4>; 226 + pinctrl-1 = <&pinctrl_i2c4_gpio>; 227 + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 228 + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 229 + }; 230 + 231 + &i2c5 { /* PMIC, EEPROM, RTC */ 232 + clock-frequency = <400000>; 233 + pinctrl-names = "default", "gpio"; 234 + pinctrl-0 = <&pinctrl_i2c5>; 235 + pinctrl-1 = <&pinctrl_i2c5_gpio>; 236 + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 237 + sda-gpios = <&gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 238 + status = "okay"; 239 + 240 + pca9450: pmic@25 { 241 + compatible = "nxp,pca9450c"; 242 + reg = <0x25>; 243 + pinctrl-names = "default"; 244 + pinctrl-0 = <&pinctrl_pmic>; 245 + interrupt-parent = <&gpio1>; 246 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 247 + nxp,i2c-lt-enable; 248 + 249 + regulators { 250 + reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */ 251 + regulator-name = "+0V8_VDD_SOC (BUCK1)"; 252 + regulator-min-microvolt = <850000>; 253 + regulator-max-microvolt = <950000>; 254 + regulator-boot-on; 255 + regulator-always-on; 256 + regulator-ramp-delay = <3125>; 257 + }; 258 + 259 + reg_vdd_arm: BUCK2 { 260 + regulator-name = "+0V9_VDD_ARM (BUCK2)"; 261 + regulator-min-microvolt = <850000>; 262 + regulator-max-microvolt = <950000>; 263 + regulator-boot-on; 264 + regulator-always-on; 265 + regulator-ramp-delay = <3125>; 266 + nxp,dvs-run-voltage = <950000>; 267 + nxp,dvs-standby-voltage = <850000>; 268 + }; 269 + 270 + reg_vdd_3v3: BUCK4 { 271 + regulator-name = "+3V3 (BUCK4)"; 272 + regulator-min-microvolt = <3300000>; 273 + regulator-max-microvolt = <3300000>; 274 + regulator-boot-on; 275 + regulator-always-on; 276 + }; 277 + 278 + reg_vdd_1v8: BUCK5 { 279 + regulator-name = "+1V8 (BUCK5)"; 280 + regulator-min-microvolt = <1800000>; 281 + regulator-max-microvolt = <1800000>; 282 + regulator-boot-on; 283 + regulator-always-on; 284 + }; 285 + 286 + reg_nvcc_dram: BUCK6 { 287 + regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; 288 + regulator-min-microvolt = <1100000>; 289 + regulator-max-microvolt = <1100000>; 290 + regulator-boot-on; 291 + regulator-always-on; 292 + }; 293 + 294 + reg_nvcc_snvs: LDO1 { 295 + regulator-name = "+1V8_NVCC_SNVS (LDO1)"; 296 + regulator-min-microvolt = <1800000>; 297 + regulator-max-microvolt = <1800000>; 298 + regulator-boot-on; 299 + regulator-always-on; 300 + }; 301 + 302 + reg_vdda: LDO3 { 303 + regulator-name = "+1V8_VDDA (LDO3)"; 304 + regulator-min-microvolt = <1800000>; 305 + regulator-max-microvolt = <1800000>; 306 + regulator-boot-on; 307 + regulator-always-on; 308 + }; 309 + 310 + reg_nvcc_sd: LDO5 { 311 + regulator-name = "NVCC_SD (LDO5)"; 312 + regulator-min-microvolt = <1800000>; 313 + regulator-max-microvolt = <3300000>; 314 + }; 315 + }; 316 + }; 317 + 318 + eeprom@50 { 319 + compatible = "onnn,n24s64b", "atmel,24c64"; 320 + reg = <0x50>; 321 + pagesize = <32>; 322 + size = <8192>; 323 + num-addresses = <1>; 324 + }; 325 + 326 + rv3028: rtc@52 { 327 + compatible = "microcrystal,rv3028"; 328 + reg = <0x52>; 329 + pinctrl-names = "default"; 330 + pinctrl-0 = <&pinctrl_rtc>; 331 + interrupts-extended = <&gpio3 24 IRQ_TYPE_LEVEL_LOW>; 332 + }; 333 + }; 334 + 335 + &pwm1 { /* OSM-S PWM_0 */ 336 + pinctrl-names = "default"; 337 + pinctrl-0 = <&pinctrl_pwm1>; 338 + }; 339 + 340 + &pwm2 { /* OSM-S PWM_1 */ 341 + pinctrl-names = "default"; 342 + pinctrl-0 = <&pinctrl_pwm2>; 343 + }; 344 + 345 + &pwm3 { /* OSM-S PWM_2 */ 346 + pinctrl-names = "default"; 347 + pinctrl-0 = <&pinctrl_pwm3>; 348 + }; 349 + 350 + &sai3 { /* OSM-S I2S_A */ 351 + pinctrl-names = "default"; 352 + pinctrl-0 = <&pinctrl_sai3>; 353 + }; 354 + 355 + &uart1 { /* OSM-S UART_A */ 356 + pinctrl-names = "default"; 357 + pinctrl-0 = <&pinctrl_uart1>; 358 + }; 359 + 360 + &uart2 { /* OSM-S UART_C */ 361 + pinctrl-names = "default"; 362 + pinctrl-0 = <&pinctrl_uart2>; 363 + }; 364 + 365 + &uart3 { /* OSM-S UART_CON */ 366 + pinctrl-names = "default"; 367 + pinctrl-0 = <&pinctrl_uart3>; 368 + status = "okay"; 369 + }; 370 + 371 + &uart4 { /* OSM-S UART_B */ 372 + pinctrl-names = "default"; 373 + pinctrl-0 = <&pinctrl_uart4>; 374 + }; 375 + 376 + &usb3_0 { /* OSM-S USB_A */ 377 + pinctrl-names = "default"; 378 + pinctrl-0 = <&pinctrl_usb1_oc>; 379 + fsl,over-current-active-low; 380 + }; 381 + 382 + &usb3_1 { /* OSM-S USB_B */ 383 + pinctrl-names = "default"; 384 + pinctrl-0 = <&pinctrl_usb2_oc>; 385 + fsl,over-current-active-low; 386 + }; 387 + 388 + &usdhc1 { /* eMMC */ 389 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 390 + pinctrl-0 = <&pinctrl_usdhc1>; 391 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 392 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 393 + vmmc-supply = <&reg_vdd_3v3>; 394 + vqmmc-supply = <&reg_vdd_1v8>; 395 + bus-width = <8>; 396 + non-removable; 397 + status = "okay"; 398 + }; 399 + 400 + &usdhc2 { /* OSM-S SDIO_A */ 401 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 402 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>; 403 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>; 404 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>; 405 + vmmc-supply = <&reg_usdhc2_vcc>; 406 + vqmmc-supply = <&reg_nvcc_sd>; 407 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 408 + }; 409 + 410 + &usdhc3 { /* OSM-S SDIO_B */ 411 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 412 + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; 413 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; 414 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; 415 + vmmc-supply = <&reg_usdhc3_vcc>; 416 + vqmmc-supply = <&reg_nvcc_sd>; 417 + cd-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 418 + wp-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; 419 + }; 420 + 421 + &wdog1 { 422 + pinctrl-names = "default"; 423 + pinctrl-0 = <&pinctrl_wdog>; 424 + fsl,ext-reset-output; 425 + status = "okay"; 426 + }; 427 + 428 + &iomuxc { 429 + pinctrl_csi_mck: csimckgrp { 430 + fsl,pins = < 431 + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 /* CAM_MCK */ 432 + >; 433 + }; 434 + 435 + pinctrl_ecspi1: ecspi1grp { 436 + fsl,pins = < 437 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 /* SPI_A_SDI_(IO0) */ 438 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 /* SPI_A_SDO_(IO1) */ 439 + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 /* SPI_A_SCK */ 440 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* SPI_A_CS0# */ 441 + >; 442 + }; 443 + 444 + pinctrl_ecspi2: ecspi2grp { 445 + fsl,pins = < 446 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 /* SPI_B_SDI */ 447 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 /* SPI_B_SDO */ 448 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 /* SPI_B_SCK */ 449 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* SPI_B_CS0# */ 450 + >; 451 + }; 452 + 453 + pinctrl_enet_rgmii: enetrgmiigrp { 454 + fsl,pins = < 455 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 /* ETH_MDC */ 456 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 /* ETH_MDIO */ 457 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ 458 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ 459 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ 460 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ 461 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ 462 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ 463 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ 464 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ 465 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ 466 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ 467 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ 468 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ 469 + >; 470 + }; 471 + 472 + pinctrl_eqos_rgmii: eqosrgmiigrp { 473 + fsl,pins = < 474 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 /* ETH_B_MDC */ 475 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 /* ETH_B_MDIO */ 476 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 /* ETH_B_(S)(R)(G)MII_RXD0 */ 477 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 /* ETH_B_(S)(R)(G)MII_RXD1 */ 478 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 /* ETH_B_(R)(G)MII_RXD2 */ 479 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 /* ETH_B_(R)(G)MII_RXD3 */ 480 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 /* ETH_B_(R)(G)MII_RX_CLK */ 481 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 /* ETH_B_(R)(G)MII_RX_DV(_ER) */ 482 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f /* ETH_B_(S)(R)(G)MII_TXD0 */ 483 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f /* ETH_B_(S)(R)(G)MII_TXD1 */ 484 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f /* ETH_B_(S)(R)(G)MII_TXD2 */ 485 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f /* ETH_B_(S)(R)(G)MII_TXD3 */ 486 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f /* ETH_B_(R)(G)MII_TX_CLK */ 487 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f /* ETH_B_(R)(G)MII_TX_EN(_ER) */ 488 + >; 489 + }; 490 + 491 + pinctrl_flexcan1: flexcan1grp { 492 + fsl,pins = < 493 + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN_A_TX */ 494 + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN_A_RX */ 495 + >; 496 + }; 497 + 498 + pinctrl_flexcan2: flexcan2grp { 499 + fsl,pins = < 500 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN_B_TX */ 501 + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 /* CAN_B_RX */ 502 + >; 503 + }; 504 + 505 + pinctrl_gpio1: gpio1grp { 506 + fsl,pins = < 507 + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x19 /* GPIO_A_0 */ 508 + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x19 /* GPIO_A_1 */ 509 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* GPIO_A_2 */ 510 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 /* GPIO_A_3 */ 511 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 /* GPIO_A_4 */ 512 + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 /* GPIO_A_5 */ 513 + >; 514 + }; 515 + 516 + pinctrl_gpio3: gpio3grp { 517 + fsl,pins = < 518 + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x19 /* GPIO_A_7 */ 519 + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x19 /* GPIO_B_0 */ 520 + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x19 /* GPIO_B_1 */ 521 + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x19 /* BOOT_SEL0# */ 522 + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x19 /* BOOT_SEL1# */ 523 + >; 524 + }; 525 + 526 + pinctrl_gpio4: gpio4grp { 527 + fsl,pins = < 528 + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* GPIO_B_5 */ 529 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 /* GPIO_B_6 */ 530 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 /* GPIO_B_7 */ 531 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x19 /* GPIO_C_0 */ 532 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 /* GPIO_B_3 */ 533 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 /* GPIO_B_4 */ 534 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x19 /* GPIO_B_2 */ 535 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19 /* GPIO_A_6 */ 536 + >; 537 + }; 538 + 539 + pinctrl_hdmi: hdmigrp { 540 + fsl,pins = < 541 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 /* HDMI_HPD */ 542 + >; 543 + }; 544 + 545 + pinctrl_i2c1: i2c1grp { 546 + fsl,pins = < 547 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 /* I2C_A_SCL */ 548 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 /* I2C_A_SDA */ 549 + >; 550 + }; 551 + 552 + pinctrl_i2c1_gpio: i2c1gpiogrp { 553 + fsl,pins = < 554 + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 /* I2C_A_SCL */ 555 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 /* I2C_A_SDA */ 556 + >; 557 + }; 558 + 559 + pinctrl_i2c2: i2c2grp { 560 + fsl,pins = < 561 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 /* I2C_B_SCL */ 562 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 /* I2C_B_SDA */ 563 + >; 564 + }; 565 + 566 + pinctrl_i2c2_gpio: i2c2gpiogrp { 567 + fsl,pins = < 568 + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 /* I2C_B_SCL */ 569 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 /* I2C_B_SDA */ 570 + >; 571 + }; 572 + 573 + pinctrl_i2c3: i2c3grp { 574 + fsl,pins = < 575 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 /* PCIe_SMCLK */ 576 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 /* PCIe_SMDAT */ 577 + >; 578 + }; 579 + 580 + pinctrl_i2c3_gpio: i2c3gpiogrp { 581 + fsl,pins = < 582 + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 /* PCIe_SMCLK */ 583 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 /* PCIe_SMDAT */ 584 + >; 585 + }; 586 + 587 + pinctrl_i2c4: i2c4grp { 588 + fsl,pins = < 589 + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 /* I2C_CAM_SCL/CSI_TX_P */ 590 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 /* I2C_CAM_SDA/CSI_TX_N */ 591 + >; 592 + }; 593 + 594 + pinctrl_i2c4_gpio: i2c4gpiogrp { 595 + fsl,pins = < 596 + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 /* I2C_CAM_SCL/CSI_TX_P */ 597 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 /* I2C_CAM_SDA/CSI_TX_N */ 598 + >; 599 + }; 600 + 601 + pinctrl_i2c5: i2c5grp { 602 + fsl,pins = < 603 + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x40000084 604 + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x40000084 605 + >; 606 + }; 607 + 608 + pinctrl_i2c5_gpio: i2c5gpiogrp { 609 + fsl,pins = < 610 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x84 611 + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x84 612 + >; 613 + }; 614 + 615 + pinctrl_pcie: pciegrp { 616 + fsl,pins = < 617 + MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x19 /* PCIe_CLKREQ# */ 618 + MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x19 /* PCIe_A_PERST# */ 619 + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x19 /* PCIe_WAKE# */ 620 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 /* PCIe_SM_ALERT */ 621 + >; 622 + }; 623 + 624 + pinctrl_pmic: pmicgrp { 625 + fsl,pins = < 626 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 627 + >; 628 + }; 629 + 630 + pinctrl_pwm1: pwm1grp { 631 + fsl,pins = < 632 + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6 /* PWM_0 */ 633 + >; 634 + }; 635 + 636 + pinctrl_pwm2: pwm2grp { 637 + fsl,pins = < 638 + MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x6 /* PWM_1 */ 639 + >; 640 + }; 641 + 642 + pinctrl_pwm3: pwm3grp { 643 + fsl,pins = < 644 + MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x6 /* PWM_2 */ 645 + >; 646 + }; 647 + 648 + pinctrl_reg_usb1_vbus: regusb1vbusgrp { 649 + fsl,pins = < 650 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 /* USB_A_EN */ 651 + >; 652 + }; 653 + 654 + pinctrl_reg_usb2_vbus: regusb2vbusgrp { 655 + fsl,pins = < 656 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 /* USB_B_EN */ 657 + >; 658 + }; 659 + 660 + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { 661 + fsl,pins = < 662 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ 663 + >; 664 + }; 665 + 666 + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { 667 + fsl,pins = < 668 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x19 /* SDIO_B_PWR_EN */ 669 + >; 670 + }; 671 + 672 + pinctrl_reg_vdd_carrier: regvddcarriergrp { 673 + fsl,pins = < 674 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x19 /* CARRIER_PWR_EN */ 675 + >; 676 + }; 677 + 678 + pinctrl_rtc: rtcgrp { 679 + fsl,pins = < 680 + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1c0 681 + >; 682 + }; 683 + 684 + pinctrl_sai3: sai3grp { 685 + fsl,pins = < 686 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 /* I2S_A_DATA_IN */ 687 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 /* I2S_A_DATA_OUT */ 688 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0xd6 /* I2S_B_DATA_IN */ 689 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0xd6 /* I2S_B_DATA_OUT */ 690 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 /* I2S_MCLK */ 691 + MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0xd6 /* I2S_LRCLK */ 692 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 /* I2S_BITCLK */ 693 + >; 694 + }; 695 + 696 + pinctrl_uart1: uart1grp { 697 + fsl,pins = < 698 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 /* UART_A_RX */ 699 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 /* UART_A_TX */ 700 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x140 /* UART_A_CTS */ 701 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x140 /* UART_A_RTS */ 702 + >; 703 + }; 704 + 705 + pinctrl_uart2: uart2grp { 706 + fsl,pins = < 707 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 /* UART_C_RX */ 708 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 /* UART_C_TX */ 709 + >; 710 + }; 711 + 712 + pinctrl_uart3: uart3grp { 713 + fsl,pins = < 714 + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* UART_CON_RX */ 715 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* UART_CON_TX */ 716 + >; 717 + }; 718 + 719 + pinctrl_uart4: uart4grp { 720 + fsl,pins = < 721 + MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x140 /* UART_B_RX */ 722 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART_B_TX */ 723 + MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x140 /* UART_B_CTS */ 724 + MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140 /* UART_B_RTS */ 725 + >; 726 + }; 727 + 728 + pinctrl_usb1_id: usb1idgrp { 729 + fsl,pins = < 730 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4 /* USB_A_ID */ 731 + >; 732 + }; 733 + 734 + pinctrl_usb1_oc: usb1ocgrp { 735 + fsl,pins = < 736 + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0 /* USB_A_OC# */ 737 + >; 738 + }; 739 + 740 + pinctrl_usb2_id: usb2idgrp { 741 + fsl,pins = < 742 + MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x1c4 /* USB_B_ID */ 743 + >; 744 + }; 745 + 746 + pinctrl_usb2_oc: usb2ocgrp { 747 + fsl,pins = < 748 + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0 /* USB_B_OC# */ 749 + >; 750 + }; 751 + 752 + pinctrl_usdhc1: usdhc1grp { 753 + fsl,pins = < 754 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 755 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 756 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 757 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 758 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 759 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 760 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d0 761 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d0 762 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d0 763 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d0 764 + MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141 765 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x190 766 + >; 767 + }; 768 + 769 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 770 + fsl,pins = < 771 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 772 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 773 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 774 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 775 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 776 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 777 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d4 778 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d4 779 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d4 780 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d4 781 + MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141 782 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x194 783 + >; 784 + }; 785 + 786 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 787 + fsl,pins = < 788 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 789 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 790 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 791 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 792 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 793 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 794 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d6 795 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d6 796 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d6 797 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d6 798 + MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141 799 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x196 800 + >; 801 + }; 802 + 803 + pinctrl_usdhc2: usdhc2grp { 804 + fsl,pins = < 805 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDIO_A_CLK */ 806 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ 807 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ 808 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ 809 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ 810 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ 811 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 812 + >; 813 + }; 814 + 815 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 816 + fsl,pins = < 817 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDIO_A_CLK */ 818 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ 819 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ 820 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ 821 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ 822 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ 823 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 824 + >; 825 + }; 826 + 827 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 828 + fsl,pins = < 829 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDIO_A_CLK */ 830 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ 831 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ 832 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ 833 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ 834 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ 835 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 836 + >; 837 + }; 838 + 839 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 840 + fsl,pins = < 841 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x19 /* SDIO_A_CD# */ 842 + >; 843 + }; 844 + 845 + pinctrl_usdhc2_wp: usdhc2wpgrp { 846 + fsl,pins = < 847 + MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x400000d6 /* SDIO_A_WP */ 848 + >; 849 + }; 850 + 851 + pinctrl_usdhc3: usdhc3grp { 852 + fsl,pins = < 853 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 /* SDIO_B_CLK */ 854 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 /* SDIO_B_CMD */ 855 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 /* SDIO_B_D0 */ 856 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 /* SDIO_B_D1 */ 857 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 /* SDIO_B_D2 */ 858 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 /* SDIO_B_D3 */ 859 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 /* SDIO_B_D4 */ 860 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 /* SDIO_B_D5 */ 861 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 /* SDIO_B_D6 */ 862 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 /* SDIO_B_D7 */ 863 + >; 864 + }; 865 + 866 + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 867 + fsl,pins = < 868 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 /* SDIO_B_CLK */ 869 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 /* SDIO_B_CMD */ 870 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 /* SDIO_B_D0 */ 871 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 /* SDIO_B_D1 */ 872 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 /* SDIO_B_D2 */ 873 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 /* SDIO_B_D3 */ 874 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 /* SDIO_B_D4 */ 875 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 /* SDIO_B_D5 */ 876 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 /* SDIO_B_D6 */ 877 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 /* SDIO_B_D7 */ 878 + >; 879 + }; 880 + 881 + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 882 + fsl,pins = < 883 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 /* SDIO_B_CLK */ 884 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 /* SDIO_B_CMD */ 885 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 /* SDIO_B_D0 */ 886 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 /* SDIO_B_D1 */ 887 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 /* SDIO_B_D2 */ 888 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 /* SDIO_B_D3 */ 889 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 /* SDIO_B_D4 */ 890 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 /* SDIO_B_D5 */ 891 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 /* SDIO_B_D6 */ 892 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 /* SDIO_B_D7 */ 893 + >; 894 + }; 895 + 896 + pinctrl_usdhc3_gpio: usdhc3gpiogrp { 897 + fsl,pins = < 898 + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x19 /* SDIO_B_CD# */ 899 + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19 /* SDIO_B_WP */ 900 + >; 901 + }; 902 + 903 + pinctrl_wdog: wdoggrp { 904 + fsl,pins = < 905 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 906 + >; 907 + }; 908 + };
+254
arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Copyright (C) 2024 Kontron Electronics GmbH 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include <dt-bindings/phy/phy-imx8-pcie.h> 9 + #include "imx8mp-kontron-smarc.dtsi" 10 + 11 + / { 12 + model = "Kontron SMARC Eval Carrier with i.MX8MP"; 13 + compatible = "kontron,imx8mp-smarc-eval-carrier", "kontron,imx8mp-smarc", 14 + "kontron,imx8mp-osm-s", "fsl,imx8mp"; 15 + 16 + backlight: backlight { 17 + compatible = "pwm-backlight"; 18 + pwms = <&pwm1 0 50000 0>; 19 + brightness-levels = <0 100>; 20 + num-interpolated-steps = <100>; 21 + default-brightness-level = <100>; 22 + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 23 + }; 24 + 25 + extcon_usbc: usbc { 26 + compatible = "linux,extcon-usb-gpio"; 27 + pinctrl-names = "default"; 28 + pinctrl-0 = <&pinctrl_usb1_id>; 29 + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 30 + }; 31 + 32 + sound { 33 + compatible = "simple-audio-card"; 34 + simple-audio-card,bitclock-master = <&codec_dai>; 35 + simple-audio-card,format = "i2s"; 36 + simple-audio-card,frame-master = <&codec_dai>; 37 + simple-audio-card,mclk-fs = <256>; 38 + simple-audio-card,name = "imx8mp-wm8904"; 39 + simple-audio-card,routing = 40 + "Headphone Jack", "HPOUTL", 41 + "Headphone Jack", "HPOUTR", 42 + "IN2L", "Line In Jack", 43 + "IN2R", "Line In Jack", 44 + "Headphone Jack", "MICBIAS", 45 + "IN1L", "Headphone Jack"; 46 + simple-audio-card,widgets = 47 + "Microphone", "Headphone Jack", 48 + "Headphone", "Headphone Jack", 49 + "Line", "Line In Jack"; 50 + 51 + codec_dai: simple-audio-card,codec { 52 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 53 + sound-dai = <&wm8904>; 54 + }; 55 + 56 + simple-audio-card,cpu { 57 + sound-dai = <&sai3>; 58 + }; 59 + }; 60 + 61 + regulator_can0: can0-regulator { 62 + compatible = "regulator-fixed"; 63 + regulator-name = "can0_en"; 64 + gpio = <&expander_pm_out 6 GPIO_ACTIVE_HIGH>; 65 + enable-active-high; 66 + }; 67 + 68 + regulator_can1: can1-regulator { 69 + compatible = "regulator-fixed"; 70 + regulator-name = "can1_en"; 71 + gpio = <&expander_pm_out 7 GPIO_ACTIVE_HIGH>; 72 + enable-active-high; 73 + }; 74 + }; 75 + 76 + &ecspi1 { 77 + status = "okay"; 78 + }; 79 + 80 + &ecspi2 { 81 + status = "okay"; 82 + }; 83 + 84 + &eqos { 85 + status = "okay"; 86 + }; 87 + 88 + &fec { 89 + status = "okay"; 90 + }; 91 + 92 + &flexcan1 { 93 + xceiver-supply = <&regulator_can0>; 94 + status = "okay"; 95 + }; 96 + 97 + &flexcan2 { 98 + xceiver-supply = <&regulator_can1>; 99 + status = "okay"; 100 + }; 101 + 102 + &hdmi_pvi { 103 + status = "okay"; 104 + }; 105 + 106 + &hdmi_tx { 107 + pinctrl-names = "default"; 108 + pinctrl-0 = <&pinctrl_hdmi>; 109 + ddc-i2c-bus = <&i2c3>; 110 + status = "okay"; 111 + }; 112 + 113 + &hdmi_tx_phy { 114 + status = "okay"; 115 + }; 116 + 117 + &i2c1 { 118 + status = "okay"; 119 + 120 + expander_pm_out: io-expander@22 { 121 + compatible = "nxp,pca9554"; 122 + reg = <0x22>; 123 + gpio-controller; 124 + #gpio-cells = <2>; 125 + gpio-line-names = "EN_5V0_S0", "EN_3V3_S0", "EN_1V8_S0", 126 + "EN_1V5_S0", "EN_12V0_PCIE", "EN_3V3_S5", 127 + "CAN0_EN", "CAN1_EN"; 128 + }; 129 + 130 + expander_pm_in: io-expander@24 { 131 + compatible = "nxp,pca9554"; 132 + reg = <0x24>; 133 + gpio-controller; 134 + #gpio-cells = <2>; 135 + gpio-line-names = "PG_5V0_3V3_S0", "PG_5V0_3V3_S5", "PG_1V8_S0", 136 + "PG_1V5_S0", "PG_BKLT_5V", "PG_BKLT_12V"; 137 + }; 138 + }; 139 + 140 + &i2c2 { 141 + status = "okay"; 142 + 143 + wm8904: audio-codec@1a { 144 + compatible = "wlf,wm8904"; 145 + reg = <0x1a>; 146 + #sound-dai-cells = <0>; 147 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 148 + clock-names = "mclk"; 149 + AVDD-supply = <&reg_vdd_1v8>; 150 + CPVDD-supply = <&reg_vdd_1v8>; 151 + DBVDD-supply = <&reg_vdd_1v8>; 152 + DCVDD-supply = <&reg_vdd_1v8>; 153 + MICVDD-supply = <&reg_vdd_3v3>; 154 + }; 155 + 156 + expander_audio: io-expander@20 { 157 + compatible = "nxp,pca9554"; 158 + reg = <0x20>; 159 + gpio-controller; 160 + #gpio-cells = <2>; 161 + gpio-line-names = "I2C_SEL_CODEC_LOOPBACK", "FPAH_PRESENCE", 162 + "CODEC_OPTION_SW_I2S_HDA", "LINE_IN_JD", 163 + "LINE_OUT_JD", "HEADPHONES_JD", "MIC_JD"; 164 + }; 165 + }; 166 + 167 + &i2c3 { 168 + status = "okay"; 169 + }; 170 + 171 + &i2c4 { 172 + status = "okay"; 173 + }; 174 + 175 + &lcdif3 { 176 + status = "okay"; 177 + }; 178 + 179 + &pcie_phy { 180 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 181 + fsl,clkreq-unsupported; 182 + clocks = <&hsio_blk_ctrl>; 183 + clock-names = "ref"; 184 + status = "okay"; 185 + }; 186 + 187 + &pcie { 188 + pinctrl-names = "default"; 189 + pinctrl-0 = <&pinctrl_pcie>; 190 + reset-gpio = <&gpio3 2 GPIO_ACTIVE_LOW>; 191 + status = "okay"; 192 + }; 193 + 194 + &pwm1 { 195 + status = "okay"; 196 + }; 197 + 198 + &sai3 { 199 + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 200 + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 201 + assigned-clock-rates = <24576000>; 202 + fsl,sai-mclk-direction-output; 203 + status = "okay"; 204 + }; 205 + 206 + &uart1 { 207 + uart-has-rtscts; 208 + status = "okay"; 209 + }; 210 + 211 + &uart2 { 212 + status = "okay"; 213 + }; 214 + 215 + &uart4 { 216 + uart-has-rtscts; 217 + status = "okay"; 218 + }; 219 + 220 + &usb_dwc3_0 { 221 + adp-disable; 222 + hnp-disable; 223 + srp-disable; 224 + dr_mode = "otg"; 225 + extcon = <&extcon_usbc>; 226 + usb-role-switch; 227 + status = "okay"; 228 + }; 229 + 230 + &usb_dwc3_1 { 231 + status = "okay"; 232 + }; 233 + 234 + &usb3_0 { 235 + status = "okay"; 236 + }; 237 + 238 + &usb3_1 { 239 + status = "okay"; 240 + }; 241 + 242 + &usb3_phy0 { 243 + vbus-supply = <&reg_usb1_vbus>; 244 + status = "okay"; 245 + }; 246 + 247 + &usb3_phy1 { 248 + status = "okay"; 249 + }; 250 + 251 + &usdhc2 { 252 + vmmc-supply = <&reg_vdd_3v3>; 253 + status = "okay"; 254 + };
+280
arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 + /* 3 + * Copyright (C) 2024 Kontron Electronics GmbH 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include "imx8mp-kontron-osm-s.dtsi" 8 + 9 + / { 10 + model = "Kontron SMARC i.MX8MP"; 11 + compatible = "kontron,imx8mp-smarc", "kontron,imx8mp-osm-s", "fsl,imx8mp"; 12 + 13 + leds { 14 + compatible = "gpio-leds"; 15 + 16 + led1 { 17 + label = "led1"; 18 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 19 + linux,default-trigger = "heartbeat"; 20 + }; 21 + }; 22 + }; 23 + 24 + &ecspi1 { 25 + status = "okay"; 26 + 27 + tpm@0 { 28 + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 29 + reg = <0>; 30 + spi-max-frequency = <18500000>; 31 + }; 32 + }; 33 + 34 + &eqos { /* Second ethernet (OSM-S ETH_B) */ 35 + pinctrl-names = "default"; 36 + pinctrl-0 = <&pinctrl_eqos_rgmii>; 37 + phy-mode = "rgmii-id"; 38 + phy-handle = <&ethphy1>; 39 + 40 + mdio { 41 + compatible = "snps,dwmac-mdio"; 42 + #address-cells = <1>; 43 + #size-cells = <0>; 44 + 45 + ethphy1: ethernet-phy@1 { 46 + compatible = "ethernet-phy-id4f51.e91b"; 47 + reg = <1>; 48 + pinctrl-0 = <&pinctrl_ethphy1>; 49 + pinctrl-names = "default"; 50 + reset-assert-us = <10000>; 51 + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 52 + }; 53 + }; 54 + }; 55 + 56 + &fec { /* First ethernet (OSM-S ETH_A) */ 57 + pinctrl-names = "default"; 58 + pinctrl-0 = <&pinctrl_enet_rgmii>; 59 + phy-connection-type = "rgmii-id"; 60 + phy-handle = <&ethphy0>; 61 + 62 + mdio { 63 + #address-cells = <1>; 64 + #size-cells = <0>; 65 + 66 + ethphy0: ethernet-phy@1 { 67 + compatible = "ethernet-phy-id4f51.e91b"; 68 + reg = <1>; 69 + pinctrl-0 = <&pinctrl_ethphy0>; 70 + pinctrl-names = "default"; 71 + reset-assert-us = <10000>; 72 + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 73 + }; 74 + }; 75 + }; 76 + 77 + /* 78 + * Rename SoM signals according to SMARC module usage: 79 + * GPIO_A_2 -> GPIO0 80 + * GPIO_A_3 -> GPIO1 81 + * GPIO_A_4 -> GPIO2 82 + * GPIO_A_5 -> GPIO3 83 + * USB_B_EN -> n.a. 84 + * USB_B_ID -> n.a. 85 + * USB_B_OC -> n.a. 86 + */ 87 + &gpio1 { 88 + gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "", 89 + "", "GPIO0", "GPIO1", "GPIO2", 90 + "GPIO3", "", "USB_A_ID", "", 91 + "USB_A_EN", "USB_A_OC","CAM_MCK", "", 92 + "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2", 93 + "ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK", 94 + "ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1", 95 + "ETH_B_RXD2", "ETH_B_RXD3"; 96 + }; 97 + 98 + /* 99 + * Rename SoM signals according to SMARC module usage: 100 + * SDIO_A_CD -> SDIO_CD 101 + * SDIO_A_CLK -> SDIO_CK 102 + * SDIO_A_CMD -> SDIO_CMD 103 + * SDIO_A_D0 -> SDIO_D0 104 + * SDIO_A_D1 -> SDIO_D1 105 + * SDIO_A_D2 -> SDIO_D2 106 + * SDIO_A_D3 -> SDIO_D3 107 + * SDIO_A_PWR_EN -> SDIO_PWR_EN 108 + * SDIO_A_WP -> SDIO_WP 109 + */ 110 + &gpio2 { 111 + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", 112 + "SDIO_CD", "SDIO_CK", "SDIO_CMD", "SDIO_D0", 113 + "SDIO_D1", "SDIO_D2", "SDIO_D3", "SDIO_PWR_EN", 114 + "SDIO_WP"; 115 + }; 116 + 117 + /* 118 + * Rename SoM signals according to SMARC module usage: 119 + * PCIE_CLKREQ -> PCIE_A_CKREQ 120 + * PCIE_A_PERST -> PCIE_A_RST 121 + * SDIO_B_D5 -> n.a. 122 + * SDIO_B_D6 -> n.a. 123 + * SDIO_B_D7 -> n.a. 124 + * SPI_A_WP -> n.a. 125 + * SPI_A_HOLD -> n.a. 126 + * UART_B_RTS -> SER2_RTS 127 + * UART_B_CTS -> SER2_CTS 128 + * SDIO_B_D0 -> GPIO8 129 + * SDIO_B_D1 -> GPIO9 130 + * SDIO_B_D2 -> GPIO10 131 + * SDIO_B_D3 -> GPIO11 132 + * SDIO_B_WP -> n.a. 133 + * SDIO_B_D4 -> n.a. 134 + * PCIE_SM_ALERT -> SMB_ALERT 135 + * SDIO_B_CLK -> GPIO6 136 + * SDIO_B_CMD -> GPIO7 137 + * GPIO_B_0 -> LCD0_BKLT_EN 138 + * GPIO_B_1 -> LCD1_BKLT_EN 139 + * BOOT_SEL0 -> BOOT_SEL2 140 + * SDIO_B_CD -> n.a. 141 + * SDIO_B_PWR_EN -> n.a. 142 + * HDMI_CEC -> n.a. 143 + * SDIO_B_PWR_EN -> n.a. 144 + */ 145 + &gpio3 { 146 + pinctrl-0 = <&pinctrl_gpio3>, <&pinctrl_gpio3_smarc>; 147 + gpio-line-names = "PCIE_WAKE", "PCIE_A_CKREQ", "PCIE_A_RST", "", 148 + "", "", "", "", 149 + "SER2_RTS", "SER2_CTS", "GPIO8", "GPIO9", 150 + "GPIO10", "GPIO11", "", "", 151 + "SMB_ALERT", "GPIO6", "GPIO7", "LCD0_BKLT_EN", 152 + "LCD1_BKLT_EN", "", "BOOT_SEL2", "BOOT_SEL1", 153 + "", "", "", "", 154 + "", "HDMI_HPD"; 155 + }; 156 + 157 + /* 158 + * Rename SoM signals according to SMARC module usage: 159 + * GPIO_B_5 -> n.a. 160 + * GPIO_B_6 -> n.a. 161 + * GPIO_B_7 -> n.a. 162 + * GPIO_C_0 -> LED 163 + * GPIO_B_3 -> ETH2_INT 164 + * GPIO_B_4 -> USB_HUB_RST 165 + * GPIO_B_2 -> ETH1_INT 166 + * GPIO_A_6 -> GPIO4 167 + * CAN_A_TX -> CAN0_TX 168 + * UART_A_CTS -> SER0_CTS 169 + * UART_A_RTS -> SER0_RTS 170 + * CAN_A_RX -> CAN0_RX 171 + * CAN_B_TX -> CAN1_TX 172 + * CAN_B_RX -> CAN1_RX 173 + * GPIO_A_7 -> TEST 174 + * I2S_A_DATA_IN -> I2S0_SDIN 175 + * I2S_LRCLK -> I2S0_LRCK 176 + */ 177 + &gpio4 { 178 + gpio-line-names = "", "", "", "LED", 179 + "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", 180 + "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", 181 + "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", 182 + "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH2_INT", "USB_HUB_RST", 183 + "ETH1_INT", "GPIO4", "CAN0_TX", "SER0_CTS", 184 + "SER0_RTS", "CAN0_RX", "CAN1_TX", "CAN1_RX", 185 + "TEST", "CARRIER_PWR_EN", "I2S0_SDIN", "I2S0_LRCK"; 186 + }; 187 + 188 + /* 189 + * Rename SoM signals according to SMARC module usage: 190 + * I2S_BITCLK -> I2S0_CK 191 + * I2S_A_DATA_OUT -> I2S0_SDOUT 192 + * I2S_MCLK -> AUDIO_MCK 193 + * PWM_2 -> GPIO5 194 + * PWM_1 -> LCD1_BKLT_PWM 195 + * PWM_0 -> LCD0_BKLT_PWM 196 + * SPI_A_SCK -> SPI0_CK 197 + * SPI_A_SDO -> SPI0_DO 198 + * SPI_A_SDI -> SPI0_DIN 199 + * SPI_A_CS0 -> SPI0_CS0 200 + * SPI_B_SCK -> ESPI_CK 201 + * SPI_B_SDO -> ESPI_IO_0 202 + * SPI_B_SDI -> ESPI_IO_1 203 + * SPI_B_CS0 -> ESPI_CS0 204 + * I2C_A_SCL -> I2C_PM_CK 205 + * I2C_A_SDA -> I2C_PM_DAT 206 + * I2C_B_SCL -> I2C_GP_CK 207 + * I2C_B_SDA -> I2C_GP_DAT 208 + * PCIE_SMCLK -> HDMI_CTRL_CK 209 + * PCIE_SMDAT -> HDMI_CTRL_DAT 210 + * I2C_CAM_SCL -> I2C_CAM1_CK 211 + * I2C_CAM_SDA -> I2C_CAM1_DAT 212 + * UART_A_RX -> SER0_RX 213 + * UART_A_TX -> SER0_TX 214 + * UART_C_RX -> SER3_RX 215 + * UART_C_TX -> SER3_TX 216 + * UART_CON_RX -> SER1_RX 217 + * UART_CON_TX -> SER1_TX 218 + * UART_B_RX -> SER2_RX 219 + * UART_B_TX -> SER2_TX 220 + */ 221 + &gpio5 { 222 + pinctrl-names = "default"; 223 + pinctrl-0 = <&pinctrl_gpio5_smarc>; 224 + gpio-line-names = "I2S0_CK", "I2S0_SDOUT", "AUDIO_MCK", "GPIO5", 225 + "LCD1_BKLT_PWM", "LCD0_BKLT_PWM", "SPI0_CK", "SPI0_DO", 226 + "SPI0_DIN", "SPI0_CS0", "ESPI_CK", "ESPI_IO_0", 227 + "ESPI_IO_1", "ESPI_CS0", "I2C_PM_CK", "I2C_PM_DAT", 228 + "I2C_GP_CK", "I2C_GP_DAT", "HDMI_CTRL_CK", "HDMI_CTRL_DAT", 229 + "I2C_CAM1_CK", "I2C_CAM1_DAT", "SER0_RX", "SER0_TX", 230 + "SER3_RX", "SER3_TX", "SER1_RX", "SER1_TX", 231 + "SER2_RX", "SER2_TX"; 232 + }; 233 + 234 + &usb_dwc3_1 { 235 + dr_mode = "host"; 236 + #address-cells = <1>; 237 + #size-cells = <0>; 238 + 239 + usb-hub@1 { 240 + compatible = "usb424,2514"; 241 + reg = <1>; 242 + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 243 + }; 244 + }; 245 + 246 + &usb3_1 { 247 + fsl,disable-port-power-control; 248 + fsl,permanently-attached; 249 + }; 250 + 251 + &iomuxc { 252 + pinctrl_ethphy0: ethphy0grp { 253 + fsl,pins = < 254 + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46 255 + >; 256 + }; 257 + 258 + pinctrl_ethphy1: ethphy1grp { 259 + fsl,pins = < 260 + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46 261 + >; 262 + }; 263 + 264 + pinctrl_gpio3_smarc: gpio3smarcgrp { 265 + fsl,pins = < 266 + MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x1d0 /* SMARC GPIO8 */ 267 + MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x1d0 /* SMARC GPIO9 */ 268 + MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x1d0 /* SMARC GPIO10 */ 269 + MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x1d0 /* SMARC GPIO11 */ 270 + MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x190 /* SMARC GPIO6 */ 271 + MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x1d0 /* SMARC GPIO7 */ 272 + >; 273 + }; 274 + 275 + pinctrl_gpio5_smarc: gpio5smarcgrp { 276 + fsl,pins = < 277 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1d0 /* SMARC GPIO5 */ 278 + >; 279 + }; 280 + };
+47
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
··· 18 18 stdout-path = &uart2; 19 19 }; 20 20 21 + hdmi-connector { 22 + compatible = "hdmi-connector"; 23 + label = "J15"; 24 + type = "d"; 25 + 26 + port { 27 + hdmi_connector_in: endpoint { 28 + remote-endpoint = <&hdmi_tx_out>; 29 + }; 30 + }; 31 + }; 32 + 21 33 leds { 22 34 compatible = "gpio-leds"; 23 35 pinctrl-names = "default"; ··· 95 83 qca,disable-hibernation-mode; 96 84 }; 97 85 }; 86 + }; 87 + 88 + &hdmi_pvi { 89 + status = "okay"; 90 + }; 91 + 92 + &hdmi_tx { 93 + pinctrl-names = "default"; 94 + pinctrl-0 = <&pinctrl_hdmi>; 95 + status = "okay"; 96 + 97 + ports { 98 + port@1 { 99 + hdmi_tx_out: endpoint { 100 + remote-endpoint = <&hdmi_connector_in>; 101 + }; 102 + }; 103 + }; 104 + }; 105 + 106 + &hdmi_tx_phy { 107 + status = "okay"; 98 108 }; 99 109 100 110 &i2c1 { ··· 247 213 }; 248 214 }; 249 215 216 + &lcdif3 { 217 + status = "okay"; 218 + }; 219 + 250 220 &uart2 { 251 221 /* console */ 252 222 pinctrl-names = "default"; ··· 314 276 pinctrl_gpio_led: gpioledgrp { 315 277 fsl,pins = < 316 278 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 279 + >; 280 + }; 281 + 282 + pinctrl_hdmi: hdmigrp { 283 + fsl,pins = < 284 + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 285 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 286 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 287 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 317 288 >; 318 289 }; 319 290
+348
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Boundary Devices 4 + * Copyright 2024 Silicon Signals Pvt. Ltd. 5 + * 6 + * Author : Bhavin Sharma <bhavin.sharma@siliconsignals.io> 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include <dt-bindings/leds/common.h> 12 + #include "imx8mp.dtsi" 13 + 14 + / { 15 + model = "Boundary Device Nitrogen8MP SMARC SoM"; 16 + compatible = "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp"; 17 + 18 + chosen { 19 + stdout-path = &uart2; 20 + }; 21 + 22 + leds { 23 + compatible = "gpio-leds"; 24 + pinctrl-names = "default"; 25 + pinctrl-0 = <&pinctrl_gpio_led>; 26 + 27 + led-0 { 28 + function = LED_FUNCTION_POWER; 29 + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 30 + linux,default-trigger = "heartbeat"; 31 + }; 32 + }; 33 + 34 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 35 + compatible = "regulator-fixed"; 36 + regulator-name = "VSD_3V3"; 37 + regulator-min-microvolt = <3300000>; 38 + regulator-max-microvolt = <3300000>; 39 + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 40 + enable-active-high; 41 + }; 42 + }; 43 + 44 + &A53_0 { 45 + cpu-supply = <&buck2>; 46 + }; 47 + 48 + &A53_1 { 49 + cpu-supply = <&buck2>; 50 + }; 51 + 52 + &A53_2 { 53 + cpu-supply = <&buck2>; 54 + }; 55 + 56 + &A53_3 { 57 + cpu-supply = <&buck2>; 58 + }; 59 + 60 + &i2c1 { 61 + clock-frequency = <400000>; 62 + pinctrl-names = "default"; 63 + pinctrl-0 = <&pinctrl_i2c1>; 64 + status = "okay"; 65 + 66 + pmic@25 { 67 + compatible = "nxp,pca9450c"; 68 + reg = <0x25>; 69 + pinctrl-names = "default"; 70 + pinctrl-0 = <&pinctrl_pmic>; 71 + interrupt-parent = <&gpio1>; 72 + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 73 + 74 + regulators { 75 + buck1: BUCK1 { 76 + regulator-name = "BUCK1"; 77 + regulator-min-microvolt = <600000>; 78 + regulator-max-microvolt = <2187500>; 79 + regulator-boot-on; 80 + regulator-always-on; 81 + regulator-ramp-delay = <3125>; 82 + }; 83 + 84 + buck2: BUCK2 { 85 + regulator-name = "BUCK2"; 86 + regulator-min-microvolt = <600000>; 87 + regulator-max-microvolt = <2187500>; 88 + regulator-boot-on; 89 + regulator-always-on; 90 + regulator-ramp-delay = <3125>; 91 + nxp,dvs-run-voltage = <950000>; 92 + nxp,dvs-standby-voltage = <850000>; 93 + }; 94 + 95 + buck4: BUCK4 { 96 + regulator-name = "BUCK4"; 97 + regulator-min-microvolt = <600000>; 98 + regulator-max-microvolt = <3400000>; 99 + regulator-boot-on; 100 + regulator-always-on; 101 + }; 102 + 103 + buck5: BUCK5 { 104 + regulator-name = "BUCK5"; 105 + regulator-min-microvolt = <600000>; 106 + regulator-max-microvolt = <3400000>; 107 + regulator-boot-on; 108 + regulator-always-on; 109 + }; 110 + 111 + buck6: BUCK6 { 112 + regulator-name = "BUCK6"; 113 + regulator-min-microvolt = <600000>; 114 + regulator-max-microvolt = <3400000>; 115 + regulator-boot-on; 116 + regulator-always-on; 117 + }; 118 + 119 + ldo1: LDO1 { 120 + regulator-name = "LDO1"; 121 + regulator-min-microvolt = <1600000>; 122 + regulator-max-microvolt = <3300000>; 123 + regulator-boot-on; 124 + regulator-always-on; 125 + }; 126 + 127 + ldo2: LDO2 { 128 + regulator-name = "LDO2"; 129 + regulator-min-microvolt = <800000>; 130 + regulator-max-microvolt = <1150000>; 131 + regulator-boot-on; 132 + regulator-always-on; 133 + }; 134 + 135 + ldo3: LDO3 { 136 + regulator-name = "LDO3"; 137 + regulator-min-microvolt = <800000>; 138 + regulator-max-microvolt = <3300000>; 139 + regulator-boot-on; 140 + regulator-always-on; 141 + }; 142 + 143 + ldo4: LDO4 { 144 + regulator-name = "LDO4"; 145 + regulator-min-microvolt = <800000>; 146 + regulator-max-microvolt = <3300000>; 147 + regulator-boot-on; 148 + regulator-always-on; 149 + }; 150 + 151 + ldo5: LDO5 { 152 + regulator-name = "LDO5"; 153 + regulator-min-microvolt = <1800000>; 154 + regulator-max-microvolt = <3300000>; 155 + regulator-boot-on; 156 + regulator-always-on; 157 + }; 158 + }; 159 + }; 160 + }; 161 + 162 + &i2c6 { 163 + clock-frequency = <100000>; 164 + pinctrl-names = "default"; 165 + pinctrl-0 = <&pinctrl_i2c6>; 166 + status = "okay"; 167 + 168 + mcp23018: gpio@20 { 169 + compatible = "microchip,mcp23018"; 170 + gpio-controller; 171 + #gpio-cells = <0x2>; 172 + reg = <0x20>; 173 + interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; 174 + interrupt-controller; 175 + #interrupt-cells = <0x2>; 176 + microchip,irq-mirror; 177 + pinctrl-names = "default"; 178 + pinctrl-0 = <&pinctrl_mcp23018>; 179 + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; 180 + }; 181 + }; 182 + 183 + /* Console */ 184 + &uart2 { 185 + pinctrl-names = "default"; 186 + pinctrl-0 = <&pinctrl_uart2>; 187 + status = "okay"; 188 + }; 189 + 190 + /* SD-card */ 191 + &usdhc2 { 192 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 193 + pinctrl-0 = <&pinctrl_usdhc2>; 194 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 195 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 196 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 197 + vmmc-supply = <&reg_usdhc2_vmmc>; 198 + bus-width = <4>; 199 + status = "okay"; 200 + }; 201 + 202 + /* eMMC */ 203 + &usdhc1 { 204 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 205 + pinctrl-0 = <&pinctrl_usdhc1>; 206 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 207 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 208 + bus-width = <8>; 209 + non-removable; 210 + status = "okay"; 211 + }; 212 + 213 + &wdog1 { 214 + pinctrl-names = "default"; 215 + pinctrl-0 = <&pinctrl_wdog>; 216 + fsl,ext-reset-output; 217 + status = "okay"; 218 + }; 219 + 220 + &iomuxc { 221 + pinctrl_gpio_led: gpioledgrp { 222 + fsl,pins = < 223 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 224 + >; 225 + }; 226 + 227 + pinctrl_i2c1: i2c1grp { 228 + fsl,pins = < 229 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 230 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 231 + >; 232 + }; 233 + 234 + pinctrl_i2c6: i2c6grp { 235 + fsl,pins = < 236 + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 237 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 238 + >; 239 + }; 240 + 241 + pinctrl_mcp23018: mcp23018grp { 242 + fsl,pins = < 243 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 244 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 245 + >; 246 + }; 247 + 248 + pinctrl_pmic: pmicgrp { 249 + fsl,pins = < 250 + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0 251 + >; 252 + }; 253 + 254 + pinctrl_uart2: uart2grp { 255 + fsl,pins = < 256 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 257 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 258 + >; 259 + }; 260 + 261 + pinctrl_usdhc1: usdhc1grp { 262 + fsl,pins = < 263 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 264 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 265 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150 266 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150 267 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150 268 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x150 269 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x150 270 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x150 271 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x150 272 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x150 273 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x10 274 + MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140 275 + >; 276 + }; 277 + 278 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 279 + fsl,pins = < 280 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 281 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 282 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154 283 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154 284 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154 285 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x154 286 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x154 287 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x154 288 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x154 289 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x154 290 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14 291 + >; 292 + }; 293 + 294 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 295 + fsl,pins = < 296 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 297 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 298 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152 299 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152 300 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152 301 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x152 302 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x152 303 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x152 304 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x152 305 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x152 306 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12 307 + >; 308 + }; 309 + 310 + pinctrl_usdhc2: usdhc2grp { 311 + fsl,pins = < 312 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 313 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 314 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 315 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 316 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 317 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 318 + >; 319 + }; 320 + 321 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 322 + fsl,pins = < 323 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 324 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 325 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 326 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 327 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 328 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 329 + >; 330 + }; 331 + 332 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 333 + fsl,pins = < 334 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 335 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 336 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 337 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 338 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 339 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 340 + >; 341 + }; 342 + 343 + pinctrl_wdog: wdoggrp { 344 + fsl,pins = < 345 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140 346 + >; 347 + }; 348 + };
+17
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2023 Boundary Devices 4 + * Copyright 2024 Silicon Signals Pvt. Ltd. 5 + * 6 + * Author : Bhavin Sharma <bhavin.sharma@siliconsignals.io> 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include "imx8mp-nitrogen-smarc-som.dtsi" 12 + 13 + / { 14 + model = "Boundary Device Nitrogen8MP Universal SMARC Carrier Board"; 15 + compatible = "boundary,imx8mp-nitrogen-smarc-universal-board", 16 + "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp"; 17 + };
+46 -4
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
··· 9 9 #include <dt-bindings/phy/phy-imx8-pcie.h> 10 10 #include <dt-bindings/leds/leds-pca9532.h> 11 11 #include <dt-bindings/pwm/pwm.h> 12 + #include <dt-bindings/thermal/thermal.h> 12 13 #include "imx8mp-phycore-som.dtsi" 13 14 14 15 / { ··· 31 30 num-interpolated-steps = <2>; 32 31 power-supply = <&reg_lvds1_reg_en>; 33 32 pwms = <&pwm3 0 50000 0>; 33 + }; 34 + 35 + fan0: fan { 36 + compatible = "gpio-fan"; 37 + pinctrl-names = "default"; 38 + pinctrl-0 = <&pinctrl_fan>; 39 + gpio-fan,speed-map = <0 0 40 + 13000 1>; 41 + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 42 + #cooling-cells = <2>; 34 43 }; 35 44 36 45 panel1_lvds: panel-lvds { ··· 121 110 regulator-name = "VCC_3V3_SW"; 122 111 regulator-min-microvolt = <3300000>; 123 112 regulator-max-microvolt = <3300000>; 113 + }; 114 + 115 + thermal-zones { 116 + soc-thermal { 117 + trips { 118 + active1: trip2 { 119 + temperature = <60000>; 120 + hysteresis = <2000>; 121 + type = "active"; 122 + }; 123 + }; 124 + 125 + cooling-maps { 126 + map1 { 127 + trip = <&active1>; 128 + cooling-device = <&fan0 1 THERMAL_NO_LIMIT>; 129 + }; 130 + }; 131 + }; 124 132 }; 125 133 }; 126 134 ··· 352 322 353 323 &gpio1 { 354 324 gpio-line-names = "", "", "X_PMIC_WDOG_B", "", 355 - "PMIC_SD_VSEL", "", "", "", "", "", 356 - "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; 325 + "PMIC_SD_VSEL", "", "", "", "PCIe_nPERST", "LVDS1REG_EN", 326 + "PCIe_nWAKE", "PCIe_nCLKREQ", "USB1_OTG_PWR", "", 327 + "PCIe_nW_DISABLE"; 357 328 }; 358 329 359 330 &gpio2 { 360 331 gpio-line-names = "", "", "", "", 361 332 "", "", "", "", "", "", 362 333 "", "", "X_SD2_CD_B", "", "", "", 363 - "", "", "", "SD2_RESET_B"; 334 + "", "", "", "SD2_RESET_B", "LVDS1_BL_EN"; 364 335 }; 365 336 366 337 &gpio3 { ··· 375 344 gpio-line-names = "", "", "", "", 376 345 "", "", "", "", "", "", 377 346 "", "", "", "", "", "", 378 - "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; 347 + "", "", "X_PMIC_IRQ_B", "nRTC_INT", "nENET0_INT_PWDN"; 348 + }; 349 + 350 + &gpio5 { 351 + gpio-line-names = "", "", "", "", 352 + "", "", "", "", "", "X_ECSPI1_SSO"; 379 353 }; 380 354 381 355 &iomuxc { ··· 410 374 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 411 375 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 412 376 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 377 + >; 378 + }; 379 + 380 + pinctrl_fan: fan0grp { 381 + fsl,pins = < 382 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 413 383 >; 414 384 }; 415 385
+1 -3
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
··· 209 209 }; 210 210 211 211 &gpio1 { 212 - gpio-line-names = "", "", "X_PMIC_WDOG_B", "", 213 - "", "", "", "", "", "", 214 - "", "", "", "", "", "X_nETHPHY_INT"; 212 + gpio-line-names = "", "", "X_PMIC_WDOG_B"; 215 213 }; 216 214 217 215 &gpio4 {
+3 -1
arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
··· 11 11 / { 12 12 aliases { 13 13 ethernet0 = &eqos; 14 + rtc0 = &gsc_rtc; 15 + rtc1 = &snvs_rtc; 14 16 }; 15 17 16 18 memory@40000000 { ··· 282 280 pagesize = <16>; 283 281 }; 284 282 285 - rtc@68 { 283 + gsc_rtc: rtc@68 { 286 284 compatible = "dallas,ds1672"; 287 285 reg = <0x68>; 288 286 };
+5 -2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
··· 25 25 ethernet4 = &lan3; 26 26 ethernet5 = &lan4; 27 27 ethernet6 = &lan5; 28 + rtc0 = &gsc_rtc; 29 + rtc1 = &snvs_rtc; 28 30 }; 29 31 30 32 chosen { ··· 301 299 &gpio3 { 302 300 gpio-line-names = 303 301 "", "", "", "", "", "", "m2_rst", "", 304 - "", "", "", "", "", "", "", "", 302 + "", "", "", "", "", "", "m2_gpio10", "", 305 303 "", "", "", "", "", "", "", "", 306 304 "", "", "", "", "", "", "", ""; 307 305 }; ··· 483 481 pagesize = <16>; 484 482 }; 485 483 486 - rtc@68 { 484 + gsc_rtc: rtc@68 { 487 485 compatible = "dallas,ds1672"; 488 486 reg = <0x68>; 489 487 }; ··· 818 816 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 819 817 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 820 818 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 819 + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ 821 820 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 822 821 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 823 822 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
+16
arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
··· 104 104 pinctrl-0 = <&pinctrl_i2c2>; 105 105 status = "okay"; 106 106 107 + accelerometer@19 { 108 + compatible = "st,lis2de12"; 109 + reg = <0x19>; 110 + pinctrl-names = "default"; 111 + pinctrl-0 = <&pinctrl_accel>; 112 + interrupt-parent = <&gpio5>; 113 + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 114 + st,drdy-int-pin = <1>; 115 + }; 116 + 107 117 eeprom@52 { 108 118 compatible = "atmel,24c32"; 109 119 reg = <0x52>; ··· 211 201 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */ 212 202 MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */ 213 203 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */ 204 + >; 205 + }; 206 + 207 + pinctrl_accel: accelgrp { 208 + fsl,pins = < 209 + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x159 214 210 >; 215 211 }; 216 212
+19
arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2024 Gateworks Corporation 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp.dtsi" 9 + #include "imx8mp-venice-gw702x.dtsi" 10 + #include "imx8mp-venice-gw82xx.dtsi" 11 + 12 + / { 13 + model = "Gateworks Venice GW82xx-2x i.MX8MP Development Kit"; 14 + compatible = "gateworks,imx8mp-gw82xx-2x", "fsl,imx8mp"; 15 + 16 + chosen { 17 + stdout-path = &uart2; 18 + }; 19 + };
+533
arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2024 Gateworks Corporation 4 + */ 5 + 6 + #include <dt-bindings/gpio/gpio.h> 7 + #include <dt-bindings/leds/common.h> 8 + #include <dt-bindings/phy/phy-imx8-pcie.h> 9 + 10 + / { 11 + aliases { 12 + ethernet1 = &eth1; 13 + fsa1 = &fsa0; 14 + fsa2 = &fsa1; 15 + }; 16 + 17 + led-controller { 18 + compatible = "gpio-leds"; 19 + pinctrl-names = "default"; 20 + pinctrl-0 = <&pinctrl_gpio_leds>; 21 + 22 + led-0 { 23 + function = LED_FUNCTION_STATUS; 24 + color = <LED_COLOR_ID_GREEN>; 25 + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 26 + default-state = "on"; 27 + linux,default-trigger = "heartbeat"; 28 + }; 29 + 30 + led-1 { 31 + function = LED_FUNCTION_STATUS; 32 + color = <LED_COLOR_ID_RED>; 33 + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 34 + default-state = "off"; 35 + }; 36 + }; 37 + 38 + pcie0_refclk: clock-pcie0 { 39 + compatible = "fixed-clock"; 40 + #clock-cells = <0>; 41 + clock-frequency = <100000000>; 42 + }; 43 + 44 + pps { 45 + compatible = "pps-gpio"; 46 + pinctrl-names = "default"; 47 + pinctrl-0 = <&pinctrl_pps>; 48 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 49 + }; 50 + 51 + reg_usb2_vbus: regulator-usb2 { 52 + compatible = "regulator-fixed"; 53 + pinctrl-names = "default"; 54 + pinctrl-0 = <&pinctrl_reg_usb2_en>; 55 + regulator-name = "usb2_vbus"; 56 + regulator-min-microvolt = <5000000>; 57 + regulator-max-microvolt = <5000000>; 58 + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 59 + enable-active-high; 60 + }; 61 + 62 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 63 + compatible = "regulator-fixed"; 64 + pinctrl-names = "default"; 65 + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 66 + regulator-name = "VDD_3V3_SD"; 67 + regulator-max-microvolt = <3300000>; 68 + regulator-min-microvolt = <3300000>; 69 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 70 + enable-active-high; 71 + off-on-delay-us = <12000>; 72 + startup-delay-us = <100>; 73 + }; 74 + }; 75 + 76 + &ecspi2 { 77 + pinctrl-names = "default"; 78 + pinctrl-0 = <&pinctrl_spi2>; 79 + cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */ 80 + <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */ 81 + <&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */ 82 + <&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */ 83 + status = "okay"; 84 + 85 + tpm@0 { 86 + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 87 + reg = <0x0>; 88 + spi-max-frequency = <10000000>; 89 + }; 90 + }; 91 + 92 + &flexcan1 { 93 + pinctrl-names = "default"; 94 + pinctrl-0 = <&pinctrl_can1>; 95 + status = "okay"; 96 + }; 97 + 98 + &flexcan2 { 99 + pinctrl-names = "default"; 100 + pinctrl-0 = <&pinctrl_can2>; 101 + status = "okay"; 102 + }; 103 + 104 + &gpio1 { 105 + gpio-line-names = 106 + "", "", "", "", 107 + "", "", "", "", 108 + "", "", "", "", 109 + "", "fsa2_gpio1", "", "", 110 + "", "", "", "", 111 + "", "", "", "", 112 + "", "", "", "", 113 + "", "", "", ""; 114 + }; 115 + 116 + &gpio4 { 117 + gpio-line-names = 118 + "", "", "", "", 119 + "", "", "", "", 120 + "dio1", "fsa1_gpio2", "", "dio0", 121 + "", "", "", "", 122 + "", "", "", "", 123 + "", "", "rs485_en", "rs485_term", 124 + "fsa2_gpio2", "fsa1_gpio1", "", "rs485_half", 125 + "", "", "", ""; 126 + }; 127 + 128 + &i2c2 { 129 + accelerometer@19 { 130 + compatible = "st,lis2de12"; 131 + reg = <0x19>; 132 + pinctrl-names = "default"; 133 + pinctrl-0 = <&pinctrl_accel>; 134 + interrupt-parent = <&gpio4>; 135 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 136 + st,drdy-int-pin = <1>; 137 + }; 138 + 139 + magnetometer@1e { 140 + compatible = "st,lis2mdl"; 141 + reg = <0x1e>; 142 + pinctrl-names = "default"; 143 + pinctrl-0 = <&pinctrl_mag>; 144 + interrupt-parent = <&gpio4>; 145 + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 146 + }; 147 + }; 148 + 149 + &i2c3 { 150 + i2c-mux@70 { 151 + compatible = "nxp,pca9548"; 152 + reg = <0x70>; 153 + #address-cells = <1>; 154 + #size-cells = <0>; 155 + 156 + /* J30 */ 157 + fsa1: i2c@0 { 158 + reg = <0>; 159 + pinctrl-names = "default"; 160 + pinctrl-0 = <&pinctrl_fsa2i2c>; 161 + #address-cells = <1>; 162 + #size-cells = <0>; 163 + 164 + gpio@20 { 165 + compatible = "nxp,pca9555"; 166 + reg = <0x20>; 167 + interrupt-parent = <&gpio4>; 168 + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 169 + interrupt-controller; 170 + #interrupt-cells = <2>; 171 + gpio-controller; 172 + #gpio-cells = <2>; 173 + }; 174 + 175 + eeprom@54 { 176 + compatible = "atmel,24c02"; 177 + reg = <0x54>; 178 + pagesize = <16>; 179 + }; 180 + 181 + eeprom@55 { 182 + compatible = "atmel,24c02"; 183 + reg = <0x55>; 184 + pagesize = <16>; 185 + }; 186 + }; 187 + 188 + /* J29 */ 189 + fsa0: i2c@1 { 190 + reg = <1>; 191 + pinctrl-names = "default"; 192 + pinctrl-0 = <&pinctrl_fsa1i2c>; 193 + #address-cells = <1>; 194 + #size-cells = <0>; 195 + 196 + gpio@20 { 197 + compatible = "nxp,pca9555"; 198 + reg = <0x20>; 199 + interrupt-parent = <&gpio4>; 200 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 201 + interrupt-controller; 202 + #interrupt-cells = <2>; 203 + gpio-controller; 204 + #gpio-cells = <2>; 205 + }; 206 + 207 + eeprom@54 { 208 + compatible = "atmel,24c02"; 209 + reg = <0x54>; 210 + pagesize = <16>; 211 + }; 212 + 213 + eeprom@55 { 214 + compatible = "atmel,24c02"; 215 + reg = <0x55>; 216 + pagesize = <16>; 217 + }; 218 + }; 219 + 220 + /* J33 */ 221 + i2c@2 { 222 + reg = <2>; 223 + #address-cells = <1>; 224 + #size-cells = <0>; 225 + }; 226 + }; 227 + }; 228 + 229 + &pcie_phy { 230 + clocks = <&pcie0_refclk>; 231 + clock-names = "ref"; 232 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 233 + fsl,clkreq-unsupported; 234 + status = "okay"; 235 + }; 236 + 237 + &pcie { 238 + pinctrl-names = "default"; 239 + pinctrl-0 = <&pinctrl_pcie0>; 240 + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 241 + status = "okay"; 242 + 243 + pcie@0,0 { 244 + reg = <0x0000 0 0 0 0>; 245 + device_type = "pci"; 246 + #address-cells = <3>; 247 + #size-cells = <2>; 248 + ranges; 249 + 250 + pcie@0,0 { 251 + reg = <0x0000 0 0 0 0>; 252 + device_type = "pci"; 253 + #address-cells = <3>; 254 + #size-cells = <2>; 255 + ranges; 256 + 257 + pcie@7,0 { 258 + reg = <0x3800 0 0 0 0>; 259 + device_type = "pci"; 260 + #address-cells = <3>; 261 + #size-cells = <2>; 262 + ranges; 263 + 264 + eth1: ethernet@0,0 { 265 + reg = <0x0000 0 0 0 0>; 266 + #address-cells = <3>; 267 + #size-cells = <2>; 268 + ranges; 269 + local-mac-address = [00 00 00 00 00 00]; 270 + }; 271 + }; 272 + }; 273 + }; 274 + }; 275 + 276 + /* GPS */ 277 + &uart1 { 278 + pinctrl-names = "default"; 279 + pinctrl-0 = <&pinctrl_uart1>; 280 + status = "okay"; 281 + }; 282 + 283 + /* RS232 */ 284 + &uart4 { 285 + pinctrl-names = "default"; 286 + pinctrl-0 = <&pinctrl_uart4>; 287 + status = "okay"; 288 + }; 289 + 290 + /* USB1 - FSA1 */ 291 + &usb3_0 { 292 + fsl,permanently-attached; 293 + fsl,disable-port-power-control; 294 + status = "okay"; 295 + }; 296 + 297 + &usb3_phy0 { 298 + status = "okay"; 299 + }; 300 + 301 + &usb_dwc3_0 { 302 + dr_mode = "host"; 303 + status = "okay"; 304 + }; 305 + 306 + /* USB2 - USB3.0 Hub */ 307 + &usb3_1 { 308 + fsl,permanently-attached; 309 + fsl,disable-port-power-control; 310 + status = "okay"; 311 + }; 312 + 313 + &usb3_phy1 { 314 + vbus-supply = <&reg_usb2_vbus>; 315 + status = "okay"; 316 + }; 317 + 318 + &usb_dwc3_1 { 319 + dr_mode = "host"; 320 + status = "okay"; 321 + }; 322 + 323 + /* SDIO 1.8V */ 324 + &usdhc1 { 325 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 326 + pinctrl-0 = <&pinctrl_usdhc1>; 327 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 328 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 329 + bus-width = <4>; 330 + non-removable; 331 + status = "okay"; 332 + }; 333 + 334 + /* microSD */ 335 + &usdhc2 { 336 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 337 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 338 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 339 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 340 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */ 341 + bus-width = <4>; 342 + vmmc-supply = <&reg_usdhc2_vmmc>; 343 + status = "okay"; 344 + }; 345 + 346 + &iomuxc { 347 + pinctrl-names = "default"; 348 + pinctrl-0 = <&pinctrl_hog>; 349 + 350 + pinctrl_hog: hoggrp { 351 + fsl,pins = < 352 + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 353 + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 354 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 355 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 356 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 357 + >; 358 + }; 359 + 360 + pinctrl_accel: accelgrp { 361 + fsl,pins = < 362 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */ 363 + >; 364 + }; 365 + 366 + pinctrl_can1: can1grp { 367 + fsl,pins = < 368 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 369 + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 370 + >; 371 + }; 372 + 373 + pinctrl_can2: can2grp { 374 + fsl,pins = < 375 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 376 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 377 + >; 378 + }; 379 + 380 + pinctrl_gpio_leds: gpioledgrp { 381 + fsl,pins = < 382 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 383 + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 384 + >; 385 + }; 386 + 387 + pinctrl_fsa1i2c: fsa1i2cgrp { 388 + fsl,pins = < 389 + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */ 390 + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */ 391 + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */ 392 + >; 393 + }; 394 + 395 + pinctrl_fsa2i2c: fsa2i2cgrp { 396 + fsl,pins = < 397 + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */ 398 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */ 399 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */ 400 + >; 401 + }; 402 + 403 + pinctrl_mag: maggrp { 404 + fsl,pins = < 405 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */ 406 + >; 407 + }; 408 + 409 + pinctrl_pcie0: pcie0grp { 410 + fsl,pins = < 411 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */ 412 + >; 413 + }; 414 + 415 + pinctrl_pps: ppsgrp { 416 + fsl,pins = < 417 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 418 + >; 419 + }; 420 + 421 + pinctrl_reg_usb2_en: regusb2grp { 422 + fsl,pins = < 423 + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 424 + >; 425 + }; 426 + 427 + pinctrl_spi2: spi2grp { 428 + fsl,pins = < 429 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0 430 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0 431 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0 432 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */ 433 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */ 434 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */ 435 + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */ 436 + >; 437 + }; 438 + 439 + pinctrl_uart1: uart1grp { 440 + fsl,pins = < 441 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 442 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 443 + >; 444 + }; 445 + 446 + pinctrl_uart4: uart4grp { 447 + fsl,pins = < 448 + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 449 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 450 + >; 451 + }; 452 + 453 + pinctrl_usdhc1: usdhc1grp { 454 + fsl,pins = < 455 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 456 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 457 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 458 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 459 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 460 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 461 + >; 462 + }; 463 + 464 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 465 + fsl,pins = < 466 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 467 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 468 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 469 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 470 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 471 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 472 + >; 473 + }; 474 + 475 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 476 + fsl,pins = < 477 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 478 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 479 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 480 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 481 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 482 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 483 + >; 484 + }; 485 + 486 + pinctrl_usdhc2: usdhc2grp { 487 + fsl,pins = < 488 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 489 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 490 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 491 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 492 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 493 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 494 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 495 + >; 496 + }; 497 + 498 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 499 + fsl,pins = < 500 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 501 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 502 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 503 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 504 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 505 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 506 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 507 + >; 508 + }; 509 + 510 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 511 + fsl,pins = < 512 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 513 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 514 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 515 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 516 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 517 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 518 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 519 + >; 520 + }; 521 + 522 + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 523 + fsl,pins = < 524 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0 525 + >; 526 + }; 527 + 528 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 529 + fsl,pins = < 530 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 531 + >; 532 + }; 533 + };
+512
arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2024 Toradex 4 + * 5 + * Common dtsi for Verdin IMX8MP SoM on Ivy carrier board 6 + * 7 + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus 8 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board 9 + */ 10 + 11 + #include <dt-bindings/mux/mux.h> 12 + #include <dt-bindings/leds/common.h> 13 + #include <dt-bindings/net/ti-dp83867.h> 14 + 15 + / { 16 + /* AIN1 Voltage w/o AIN1_MODE gpio control */ 17 + ain1_voltage_unmanaged: voltage-divider-ain1 { 18 + compatible = "voltage-divider"; 19 + #io-channel-cells = <1>; 20 + io-channels = <&ivy_adc1 0>; 21 + full-ohms = <19>; 22 + output-ohms = <1>; 23 + }; 24 + 25 + /* AIN1 Current w/o AIN1_MODE gpio control */ 26 + ain1_current_unmanaged: current-sense-shunt-ain1 { 27 + compatible = "current-sense-shunt"; 28 + #io-channel-cells = <0>; 29 + io-channels = <&ivy_adc1 1>; 30 + shunt-resistor-micro-ohms = <100000000>; 31 + }; 32 + 33 + /* AIN1_MODE - SODIMM 216 */ 34 + ain1_mode_mux_ctrl: mux-controller-0 { 35 + compatible = "gpio-mux"; 36 + pinctrl-names = "default"; 37 + pinctrl-0 = <&pinctrl_gpio5>; 38 + #mux-control-cells = <0>; 39 + mux-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 40 + }; 41 + 42 + ain1-voltage { 43 + compatible = "io-channel-mux"; 44 + channels = "ain1_voltage", ""; 45 + io-channels = <&ain1_voltage_unmanaged 0>; 46 + io-channel-names = "parent"; 47 + mux-controls = <&ain1_mode_mux_ctrl>; 48 + settle-time-us = <1000>; 49 + }; 50 + 51 + ain1-current { 52 + compatible = "io-channel-mux"; 53 + channels = "", "ain1_current"; 54 + io-channels = <&ain1_current_unmanaged>; 55 + io-channel-names = "parent"; 56 + mux-controls = <&ain1_mode_mux_ctrl>; 57 + settle-time-us = <1000>; 58 + }; 59 + 60 + /* AIN2 Voltage w/o AIN2_MODE gpio control */ 61 + ain2_voltage_unmanaged: voltage-divider-ain2 { 62 + compatible = "voltage-divider"; 63 + #io-channel-cells = <1>; 64 + io-channels = <&ivy_adc2 0>; 65 + full-ohms = <19>; 66 + output-ohms = <1>; 67 + }; 68 + 69 + /* AIN2 Current w/o AIN2_MODE gpio control */ 70 + ain2_current_unmanaged: current-sense-shunt-ain2 { 71 + compatible = "current-sense-shunt"; 72 + #io-channel-cells = <0>; 73 + io-channels = <&ivy_adc2 1>; 74 + shunt-resistor-micro-ohms = <100000000>; 75 + }; 76 + 77 + /* AIN2_MODE - SODIMM 218 */ 78 + ain2_mode_mux_ctrl: mux-controller-1 { 79 + compatible = "gpio-mux"; 80 + pinctrl-names = "default"; 81 + pinctrl-0 = <&pinctrl_gpio6>; 82 + #mux-control-cells = <0>; 83 + mux-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 84 + }; 85 + 86 + ain2-voltage { 87 + compatible = "io-channel-mux"; 88 + channels = "ain2_voltage", ""; 89 + io-channels = <&ain2_voltage_unmanaged 0>; 90 + io-channel-names = "parent"; 91 + mux-controls = <&ain2_mode_mux_ctrl>; 92 + settle-time-us = <1000>; 93 + }; 94 + 95 + ain2-current { 96 + compatible = "io-channel-mux"; 97 + channels = "", "ain2_current"; 98 + io-channels = <&ain2_current_unmanaged>; 99 + io-channel-names = "parent"; 100 + mux-controls = <&ain2_mode_mux_ctrl>; 101 + settle-time-us = <1000>; 102 + }; 103 + 104 + leds { 105 + compatible = "gpio-leds"; 106 + pinctrl-names = "default"; 107 + pinctrl-0 = <&pinctrl_ivy_leds>; 108 + 109 + /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */ 110 + led-0 { 111 + color = <LED_COLOR_ID_BLUE>; 112 + default-state = "off"; 113 + function = LED_FUNCTION_STATUS; 114 + function-enumerator = <1>; 115 + gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; 116 + }; 117 + 118 + /* D7 Green - SODIMM 32 - LEDs.GPIO2 */ 119 + led-1 { 120 + color = <LED_COLOR_ID_GREEN>; 121 + default-state = "off"; 122 + function = LED_FUNCTION_STATUS; 123 + function-enumerator = <1>; 124 + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; 125 + }; 126 + 127 + /* D7 Red - SODIMM 34 - LEDs.GPIO3 */ 128 + led-2 { 129 + color = <LED_COLOR_ID_RED>; 130 + default-state = "off"; 131 + function = LED_FUNCTION_STATUS; 132 + function-enumerator = <1>; 133 + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 134 + }; 135 + 136 + /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */ 137 + led-3 { 138 + color = <LED_COLOR_ID_BLUE>; 139 + default-state = "off"; 140 + function = LED_FUNCTION_STATUS; 141 + function-enumerator = <2>; 142 + gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; 143 + }; 144 + 145 + /* D8 Green - SODIMM 54 - LEDs.GPIO5 */ 146 + led-4 { 147 + color = <LED_COLOR_ID_GREEN>; 148 + default-state = "off"; 149 + function = LED_FUNCTION_STATUS; 150 + function-enumerator = <2>; 151 + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; 152 + }; 153 + 154 + /* D8 Red - SODIMM 44 - LEDs.GPIO6 */ 155 + led-5 { 156 + color = <LED_COLOR_ID_RED>; 157 + default-state = "off"; 158 + function = LED_FUNCTION_STATUS; 159 + function-enumerator = <2>; 160 + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 161 + }; 162 + 163 + /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */ 164 + led-6 { 165 + color = <LED_COLOR_ID_BLUE>; 166 + default-state = "off"; 167 + function = LED_FUNCTION_STATUS; 168 + function-enumerator = <3>; 169 + gpios = <&gpio5 01 GPIO_ACTIVE_HIGH>; 170 + }; 171 + 172 + /* D9 Red - SODIMM 48 - LEDs.GPIO8 */ 173 + led-7 { 174 + color = <LED_COLOR_ID_RED>; 175 + default-state = "off"; 176 + function = LED_FUNCTION_STATUS; 177 + function-enumerator = <3>; 178 + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 179 + }; 180 + }; 181 + 182 + reg_3v2_ain1: regulator-3v2-ain1 { 183 + compatible = "regulator-fixed"; 184 + regulator-max-microvolt = <3200000>; 185 + regulator-min-microvolt = <3200000>; 186 + regulator-name = "+3V2_AIN1"; 187 + }; 188 + 189 + reg_3v2_ain2: regulator-3v2-ain2 { 190 + compatible = "regulator-fixed"; 191 + regulator-max-microvolt = <3200000>; 192 + regulator-min-microvolt = <3200000>; 193 + regulator-name = "+3V2_AIN2"; 194 + }; 195 + 196 + /* Ivy Power Supply Input Voltage */ 197 + ivy-input-voltage { 198 + compatible = "voltage-divider"; 199 + /* Verdin ADC_1 */ 200 + io-channels = <&verdin_som_adc 7>; 201 + full-ohms = <204700>; /* 200k + 4.7k */ 202 + output-ohms = <4700>; 203 + }; 204 + 205 + ivy-5v-voltage { 206 + compatible = "voltage-divider"; 207 + /* Verdin ADC_2 */ 208 + io-channels = <&verdin_som_adc 6>; 209 + full-ohms = <39000>; /* 27k + 12k */ 210 + output-ohms = <12000>; 211 + }; 212 + 213 + ivy-3v3-voltage { 214 + compatible = "voltage-divider"; 215 + /* Verdin ADC_3 */ 216 + io-channels = <&verdin_som_adc 5>; 217 + full-ohms = <54000>; /* 27k + 27k */ 218 + output-ohms = <27000>; 219 + }; 220 + 221 + ivy-1v8-voltage { 222 + compatible = "voltage-divider"; 223 + /* Verdin ADC_4 */ 224 + io-channels = <&verdin_som_adc 4>; 225 + full-ohms = <39000>; /* 12k + 27k */ 226 + output-ohms = <27000>; 227 + }; 228 + }; 229 + 230 + /* Verdin SPI_1 */ 231 + &ecspi1 { 232 + pinctrl-0 = <&pinctrl_ecspi1>, 233 + <&pinctrl_gpio1>, 234 + <&pinctrl_gpio4>; 235 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 236 + <&gpio1 0 GPIO_ACTIVE_LOW>, 237 + <&gpio1 6 GPIO_ACTIVE_LOW>; 238 + status = "okay"; 239 + 240 + tpm@1 { 241 + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 242 + reg = <1>; 243 + spi-max-frequency = <18500000>; 244 + }; 245 + 246 + fram@2 { 247 + compatible = "fujitsu,mb85rs256", "atmel,at25"; 248 + reg = <2>; 249 + address-width = <16>; 250 + size = <32768>; 251 + spi-max-frequency = <33000000>; 252 + pagesize = <1>; 253 + }; 254 + }; 255 + 256 + /* EEPROM on Ivy */ 257 + &eeprom_carrier_board { 258 + status = "okay"; 259 + }; 260 + 261 + /* Verdin ETH_1 */ 262 + &eqos { 263 + status = "okay"; 264 + }; 265 + 266 + /* Verdin ETH_2 */ 267 + &fec { 268 + phy-handle = <&ethphy2>; 269 + phy-mode = "rgmii-id"; 270 + status = "okay"; 271 + }; 272 + 273 + &verdin_eth2_mdio { 274 + ethphy2: ethernet-phy@2 { 275 + reg = <2>; 276 + interrupt-parent = <&gpio4>; 277 + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 278 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 279 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 280 + }; 281 + }; 282 + 283 + /* Verdin CAN_1 */ 284 + &flexcan1 { 285 + status = "okay"; 286 + }; 287 + 288 + /* Verdin CAN_2 */ 289 + &flexcan2 { 290 + status = "okay"; 291 + }; 292 + 293 + &gpio1 { 294 + gpio-line-names = 295 + "", /* 0 */ 296 + "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */ 297 + "", 298 + "", 299 + "", 300 + "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */ 301 + "", 302 + "", 303 + "", 304 + "", 305 + "", 306 + "", /* 10 */ 307 + "", 308 + "", 309 + "", 310 + "", 311 + "", 312 + "", 313 + "", 314 + "", 315 + "", 316 + "", /* 20 */ 317 + "", 318 + "", 319 + "", 320 + "", 321 + "", 322 + "", 323 + "", 324 + "", 325 + ""; 326 + }; 327 + 328 + &gpio3 { 329 + gpio-line-names = 330 + "", /* 0 */ 331 + "", 332 + "", 333 + "", 334 + "", 335 + "", 336 + "DIG_1", /* SODIMM 56 */ 337 + "DIG_2", /* SODIMM 58 */ 338 + "REL1", /* SODIMM 60 */ 339 + "REL2", /* SODIMM 62 */ 340 + "", /* 10 */ 341 + "", 342 + "", 343 + "", 344 + "REL4", /* SODIMM 66 */ 345 + "", 346 + "REL3", /* SODIMM 64 */ 347 + "", 348 + "", 349 + "", 350 + "", /* 20 */ 351 + "", 352 + "", 353 + "", 354 + "", 355 + "", 356 + "", 357 + "", 358 + "", 359 + ""; 360 + }; 361 + 362 + /* Temperature sensor on Ivy */ 363 + &hwmon_temp { 364 + compatible = "ti,tmp1075"; 365 + status = "okay"; 366 + }; 367 + 368 + /* Verdin I2C_4 CSI */ 369 + &i2c3 { 370 + status = "okay"; 371 + 372 + ivy_adc1: adc@40 { 373 + compatible = "ti,ads1119"; 374 + reg = <0x40>; 375 + pinctrl-names = "default"; 376 + pinctrl-0 = <&pinctrl_gpio7>; 377 + interrupt-parent = <&gpio4>; 378 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 379 + avdd-supply = <&reg_3v2_ain1>; 380 + dvdd-supply = <&reg_3v2_ain1>; 381 + vref-supply = <&reg_3v2_ain1>; 382 + #address-cells = <1>; 383 + #io-channel-cells = <1>; 384 + #size-cells = <0>; 385 + 386 + /* AIN1 0-33V Voltage Input */ 387 + channel@0 { 388 + reg = <0>; 389 + diff-channels = <0 1>; 390 + }; 391 + 392 + /* AIN1 0-20mA Current Input */ 393 + channel@1 { 394 + reg = <1>; 395 + diff-channels = <2 3>; 396 + }; 397 + }; 398 + 399 + ivy_adc2: adc@41 { 400 + compatible = "ti,ads1119"; 401 + reg = <0x41>; 402 + pinctrl-names = "default"; 403 + pinctrl-0 = <&pinctrl_gpio8>; 404 + interrupt-parent = <&gpio4>; 405 + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 406 + avdd-supply = <&reg_3v2_ain2>; 407 + dvdd-supply = <&reg_3v2_ain2>; 408 + vref-supply = <&reg_3v2_ain2>; 409 + #address-cells = <1>; 410 + #io-channel-cells = <1>; 411 + #size-cells = <0>; 412 + 413 + /* AIN2 0-33V Voltage Input */ 414 + channel@0 { 415 + reg = <0>; 416 + diff-channels = <0 1>; 417 + }; 418 + 419 + /* AIN2 0-20mA Current Input */ 420 + channel@1 { 421 + reg = <1>; 422 + diff-channels = <2 3>; 423 + }; 424 + }; 425 + }; 426 + 427 + /* Verdin I2C_1 */ 428 + &i2c4 { 429 + status = "okay"; 430 + }; 431 + 432 + /* Verdin PCIE_1 */ 433 + &pcie { 434 + status = "okay"; 435 + }; 436 + 437 + &pcie_phy { 438 + status = "okay"; 439 + }; 440 + 441 + /* Verdin UART_1 */ 442 + &uart1 { 443 + status = "okay"; 444 + }; 445 + 446 + /* Verdin UART_2 */ 447 + &uart2 { 448 + linux,rs485-enabled-at-boot-time; 449 + rs485-rx-during-tx; 450 + status = "okay"; 451 + }; 452 + 453 + /* Verdin UART_3 */ 454 + &uart3 { 455 + status = "okay"; 456 + }; 457 + 458 + /* Verdin USB_1 */ 459 + &usb3_0 { 460 + status = "okay"; 461 + }; 462 + 463 + &usb3_phy0 { 464 + status = "okay"; 465 + }; 466 + 467 + /* Verdin USB_2 */ 468 + &usb3_1 { 469 + status = "okay"; 470 + }; 471 + 472 + &usb3_phy1 { 473 + status = "okay"; 474 + }; 475 + 476 + /* Verdin SD_1 */ 477 + &usdhc2 { 478 + status = "okay"; 479 + }; 480 + 481 + &iomuxc { 482 + 483 + pinctrl-names = "default"; 484 + pinctrl-0 = <&pinctrl_gpio2>, <&pinctrl_gpio3>, 485 + <&pinctrl_ivy_dig_inputs>, <&pinctrl_ivy_relays>; 486 + 487 + pinctrl_ivy_dig_inputs: ivydiginputsgrp { 488 + fsl,pins = 489 + <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x96>, /* SODIMM 56 */ 490 + <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x96>; /* SODIMM 58 */ 491 + }; 492 + 493 + pinctrl_ivy_leds: ivyledsgrp { 494 + fsl,pins = 495 + <MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x16>, /* SODIMM 30 */ 496 + <MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x16>, /* SODIMM 32 */ 497 + <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x16>, /* SODIMM 34 */ 498 + <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x16>, /* SODIMM 36 */ 499 + <MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x16>, /* SODIMM 44 */ 500 + <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x16>, /* SODIMM 46 */ 501 + <MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x16>, /* SODIMM 48 */ 502 + <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x16>; /* SODIMM 54 */ 503 + }; 504 + 505 + pinctrl_ivy_relays: ivyrelaysgrp { 506 + fsl,pins = 507 + <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x16>, /* SODIMM 60 */ 508 + <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x16>, /* SODIMM 62 */ 509 + <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x16>, /* SODIMM 64 */ 510 + <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x16>; /* SODIMM 66 */ 511 + }; 512 + };
+18
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2024 Toradex 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp-verdin.dtsi" 9 + #include "imx8mp-verdin-nonwifi.dtsi" 10 + #include "imx8mp-verdin-ivy.dtsi" 11 + 12 + / { 13 + model = "Toradex Verdin iMX8M Plus on Ivy"; 14 + compatible = "toradex,verdin-imx8mp-nonwifi-ivy", 15 + "toradex,verdin-imx8mp-nonwifi", 16 + "toradex,verdin-imx8mp", 17 + "fsl,imx8mp"; 18 + };
+18
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright 2024 Toradex 4 + */ 5 + 6 + /dts-v1/; 7 + 8 + #include "imx8mp-verdin.dtsi" 9 + #include "imx8mp-verdin-wifi.dtsi" 10 + #include "imx8mp-verdin-ivy.dtsi" 11 + 12 + / { 13 + model = "Toradex Verdin iMX8M Plus WB on Ivy"; 14 + compatible = "toradex,verdin-imx8mp-wifi-ivy", 15 + "toradex,verdin-imx8mp-wifi", 16 + "toradex,verdin-imx8mp", 17 + "fsl,imx8mp"; 18 + };
+9 -3
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
··· 175 175 regulator-max-microvolt = <3300000>; 176 176 regulator-min-microvolt = <3300000>; 177 177 regulator-name = "+V3.3_SD"; 178 - startup-delay-us = <2000>; 178 + startup-delay-us = <20000>; 179 179 }; 180 180 181 181 reserved-memory { ··· 320 320 pinctrl-0 = <&pinctrl_fec>; 321 321 pinctrl-1 = <&pinctrl_fec_sleep>; 322 322 323 - mdio { 323 + verdin_eth2_mdio: mdio { 324 324 #address-cells = <1>; 325 325 #size-cells = <0>; 326 326 ··· 478 478 pinctrl-1 = <&pinctrl_i2c1_gpio>; 479 479 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 480 480 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 481 + single-master; 481 482 status = "okay"; 482 483 483 484 pca9450: pmic@25 { ··· 592 591 vs-supply = <&reg_vdd_1v8>; 593 592 }; 594 593 595 - adc@49 { 594 + verdin_som_adc: adc@49 { 596 595 compatible = "ti,ads1015"; 597 596 reg = <0x49>; 598 597 #address-cells = <1>; 599 598 #size-cells = <0>; 599 + #io-channel-cells = <1>; 600 600 601 601 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 602 602 channel@0 { ··· 671 669 pinctrl-1 = <&pinctrl_i2c2_gpio>; 672 670 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 673 671 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 672 + single-master; 674 673 675 674 atmel_mxt_ts_mezzanine: touch-mezzanine@4a { 676 675 compatible = "atmel,maxtouch"; ··· 693 690 pinctrl-1 = <&pinctrl_i2c3_gpio>; 694 691 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 695 692 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 693 + single-master; 696 694 }; 697 695 698 696 /* Verdin I2C_1 */ ··· 704 700 pinctrl-1 = <&pinctrl_i2c4_gpio>; 705 701 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 706 702 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 703 + single-master; 707 704 708 705 gpio_expander_21: gpio-expander@21 { 709 706 compatible = "nxp,pcal6416"; ··· 793 788 pinctrl-1 = <&pinctrl_i2c5_gpio>; 794 789 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 795 790 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 791 + single-master; 796 792 }; 797 793 798 794 /* Verdin PCIE_1 */
+23 -2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
··· 47 47 #address-cells = <1>; 48 48 #size-cells = <0>; 49 49 50 + idle-states { 51 + entry-method = "psci"; 52 + 53 + cpu_pd_wait: cpu-pd-wait { 54 + compatible = "arm,idle-state"; 55 + arm,psci-suspend-param = <0x0010033>; 56 + local-timer-stop; 57 + entry-latency-us = <1000>; 58 + exit-latency-us = <700>; 59 + min-residency-us = <2700>; 60 + wakeup-latency-us = <1500>; 61 + }; 62 + }; 63 + 50 64 A53_0: cpu@0 { 51 65 device_type = "cpu"; 52 66 compatible = "arm,cortex-a53"; ··· 79 65 nvmem-cell-names = "speed_grade"; 80 66 operating-points-v2 = <&a53_opp_table>; 81 67 #cooling-cells = <2>; 68 + cpu-idle-states = <&cpu_pd_wait>; 82 69 }; 83 70 84 71 A53_1: cpu@1 { ··· 98 83 next-level-cache = <&A53_L2>; 99 84 operating-points-v2 = <&a53_opp_table>; 100 85 #cooling-cells = <2>; 86 + cpu-idle-states = <&cpu_pd_wait>; 101 87 }; 102 88 103 89 A53_2: cpu@2 { ··· 117 101 next-level-cache = <&A53_L2>; 118 102 operating-points-v2 = <&a53_opp_table>; 119 103 #cooling-cells = <2>; 104 + cpu-idle-states = <&cpu_pd_wait>; 120 105 }; 121 106 122 107 A53_3: cpu@3 { ··· 136 119 next-level-cache = <&A53_L2>; 137 120 operating-points-v2 = <&a53_opp_table>; 138 121 #cooling-cells = <2>; 122 + cpu-idle-states = <&cpu_pd_wait>; 139 123 }; 140 124 141 125 A53_L2: l2-cache0 { ··· 2194 2176 2195 2177 pcie_ep: pcie-ep@33800000 { 2196 2178 compatible = "fsl,imx8mp-pcie-ep"; 2197 - reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 2198 - reg-names = "dbi", "addr_space"; 2179 + reg = <0x33800000 0x100000>, 2180 + <0x18000000 0x8000000>, 2181 + <0x33900000 0x100000>, 2182 + <0x33b00000 0x100000>; 2183 + reg-names = "dbi", "addr_space", "dbi2", "atu"; 2199 2184 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2200 2185 <&clk IMX8MP_CLK_HSIO_AXI>, 2201 2186 <&clk IMX8MP_CLK_PCIE_ROOT>;
+5 -3
arch/arm64/boot/dts/freescale/imx8mq.dtsi
··· 1819 1819 1820 1820 pcie1_ep: pcie-ep@33c00000 { 1821 1821 compatible = "fsl,imx8mq-pcie-ep"; 1822 - reg = <0x33c00000 0x000400000>, 1823 - <0x20000000 0x08000000>; 1824 - reg-names = "dbi", "addr_space"; 1822 + reg = <0x33c00000 0x100000>, 1823 + <0x20000000 0x8000000>, 1824 + <0x33d00000 0x100000>, 1825 + <0x33f00000 0x100000>; 1826 + reg-names = "dbi", "addr_space", "dbi2", "atu"; 1825 1827 num-lanes = <1>; 1826 1828 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1827 1829 interrupt-names = "dma";
+89
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
··· 92 92 reg = <0 0x90400000 0 0x100000>; 93 93 no-map; 94 94 }; 95 + 96 + dsp_reserved: memory@92400000 { 97 + reg = <0 0x92400000 0 0x1000000>; 98 + no-map; 99 + }; 100 + 101 + dsp_vdev0vring0: memory@942f0000 { 102 + reg = <0 0x942f0000 0 0x8000>; 103 + no-map; 104 + }; 105 + 106 + dsp_vdev0vring1: memory@942f8000 { 107 + reg = <0 0x942f8000 0 0x8000>; 108 + no-map; 109 + }; 110 + 111 + dsp_vdev0buffer: memory@94300000 { 112 + compatible = "shared-dma-pool"; 113 + reg = <0 0x94300000 0 0x100000>; 114 + no-map; 115 + }; 95 116 }; 96 117 97 118 lvds_backlight0: backlight-lvds0 { ··· 200 179 gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 201 180 enable-active-high; 202 181 vin-supply = <&reg_can2_en>; 182 + }; 183 + 184 + reg_pciea: regulator-pcie { 185 + compatible = "regulator-fixed"; 186 + pinctrl-0 = <&pinctrl_pciea_reg>; 187 + pinctrl-names = "default"; 188 + regulator-max-microvolt = <3300000>; 189 + regulator-min-microvolt = <3300000>; 190 + regulator-name = "mpcie_3v3"; 191 + gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; 192 + enable-active-high; 203 193 }; 204 194 205 195 reg_vref_1v8: regulator-adc-vref { ··· 325 293 }; 326 294 327 295 &cm41_intmux { 296 + status = "okay"; 297 + }; 298 + 299 + &hsio_phy { 300 + fsl,hsio-cfg = "pciea-pcieb-sata"; 301 + fsl,refclk-pad-mode = "input"; 328 302 status = "okay"; 329 303 }; 330 304 ··· 579 541 status = "okay"; 580 542 }; 581 543 544 + &pciea { 545 + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 546 + phy-names = "pcie-phy"; 547 + pinctrl-0 = <&pinctrl_pciea>; 548 + pinctrl-names = "default"; 549 + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; 550 + vpcie-supply = <&reg_pciea>; 551 + status = "okay"; 552 + }; 553 + 554 + &pcieb { 555 + phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; 556 + phy-names = "pcie-phy"; 557 + pinctrl-0 = <&pinctrl_pcieb>; 558 + pinctrl-names = "default"; 559 + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; 560 + status = "disabled"; 561 + }; 562 + 582 563 &qm_pwm_lvds0 { 583 564 pinctrl-names = "default"; 584 565 pinctrl-0 = <&pinctrl_pwm_lvds0>; ··· 694 637 assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 695 638 assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 696 639 fsl,sai-asynchronous; 640 + status = "okay"; 641 + }; 642 + 643 + &sata { 644 + status = "okay"; 645 + }; 646 + 647 + &vpu_dsp { 648 + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 649 + <&dsp_vdev0vring1>, <&dsp_reserved>; 697 650 status = "okay"; 698 651 }; 699 652 ··· 893 826 fsl,pins = < 894 827 IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c 895 828 IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c 829 + >; 830 + }; 831 + 832 + pinctrl_pciea: pcieagrp { 833 + fsl,pins = < 834 + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 835 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 836 + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 837 + >; 838 + }; 839 + 840 + pinctrl_pciea_reg: pcieareggrp { 841 + fsl,pins = < 842 + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 843 + >; 844 + }; 845 + 846 + pinctrl_pcieb: pciebgrp { 847 + fsl,pins = < 848 + IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 849 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 850 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 896 851 >; 897 852 }; 898 853
+2 -2
arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
··· 304 304 }; 305 305 306 306 /* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ 307 - &edma0{ 307 + &edma0 { 308 308 reg = <0x591f0000 0x150000>; 309 309 dma-channels = <20>; 310 310 dma-channel-mask = <0>; ··· 351 351 }; 352 352 353 353 /* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ 354 - &edma1{ 354 + &edma1 { 355 355 reg = <0x599f0000 0xc0000>; 356 356 dma-channels = <11>; 357 357 dma-channel-mask = <0xc0>;
+4
arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
··· 4 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 5 */ 6 6 7 + &usbphy1 { 8 + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy"; 9 + }; 10 + 7 11 &fec1 { 8 12 compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; 9 13 iommus = <&smmu 0x12 0x7f80>;
+3
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
··· 4 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 5 */ 6 6 7 + /delete-node/ &adma_pwm; 8 + /delete-node/ &adma_pwm_lpcg; 9 + 7 10 &dma_subsys { 8 11 uart4_lpcg: clock-controller@5a4a0000 { 9 12 compatible = "fsl,imx8qxp-lpcg";
+209
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright 2024 NXP 4 + * Richard Zhu <hongxing.zhu@nxp.com> 5 + */ 6 + 7 + &hsio_subsys { 8 + compatible = "simple-bus"; 9 + ranges = <0x5f000000 0x0 0x5f000000 0x01000000>, 10 + <0x40000000 0x0 0x60000000 0x10000000>, 11 + <0x80000000 0x0 0x70000000 0x10000000>; 12 + #address-cells = <1>; 13 + #size-cells = <1>; 14 + 15 + pciea: pcie@5f000000 { 16 + compatible = "fsl,imx8q-pcie"; 17 + reg = <0x5f000000 0x10000>, 18 + <0x4ff00000 0x80000>; 19 + reg-names = "dbi", "config"; 20 + ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>, 21 + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; 22 + #interrupt-cells = <1>; 23 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 24 + interrupt-names = "msi"; 25 + #address-cells = <3>; 26 + #size-cells = <2>; 27 + clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, 28 + <&pciea_lpcg IMX_LPCG_CLK_4>, 29 + <&pciea_lpcg IMX_LPCG_CLK_5>; 30 + clock-names = "dbi", "mstr", "slv"; 31 + bus-range = <0x00 0xff>; 32 + device_type = "pci"; 33 + interrupt-map = <0 0 0 1 &gic 0 73 4>, 34 + <0 0 0 2 &gic 0 74 4>, 35 + <0 0 0 3 &gic 0 75 4>, 36 + <0 0 0 4 &gic 0 76 4>; 37 + interrupt-map-mask = <0 0 0 0x7>; 38 + num-lanes = <1>; 39 + num-viewport = <4>; 40 + power-domains = <&pd IMX_SC_R_PCIE_A>; 41 + fsl,max-link-speed = <3>; 42 + status = "disabled"; 43 + }; 44 + 45 + pcieb: pcie@5f010000 { 46 + compatible = "fsl,imx8q-pcie"; 47 + reg = <0x5f010000 0x10000>, 48 + <0x8ff00000 0x80000>; 49 + reg-names = "dbi", "config"; 50 + ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, 51 + <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; 52 + #interrupt-cells = <1>; 53 + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 54 + interrupt-names = "msi"; 55 + #address-cells = <3>; 56 + #size-cells = <2>; 57 + clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, 58 + <&pcieb_lpcg IMX_LPCG_CLK_4>, 59 + <&pcieb_lpcg IMX_LPCG_CLK_5>; 60 + clock-names = "dbi", "mstr", "slv"; 61 + bus-range = <0x00 0xff>; 62 + device_type = "pci"; 63 + interrupt-map = <0 0 0 1 &gic 0 105 4>, 64 + <0 0 0 2 &gic 0 106 4>, 65 + <0 0 0 3 &gic 0 107 4>, 66 + <0 0 0 4 &gic 0 108 4>; 67 + interrupt-map-mask = <0 0 0 0x7>; 68 + num-lanes = <1>; 69 + num-viewport = <4>; 70 + power-domains = <&pd IMX_SC_R_PCIE_B>; 71 + fsl,max-link-speed = <3>; 72 + status = "disabled"; 73 + }; 74 + 75 + sata: sata@5f020000 { 76 + compatible = "fsl,imx8qm-ahci"; 77 + reg = <0x5f020000 0x10000>; 78 + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 79 + clocks = <&sata_lpcg IMX_LPCG_CLK_4>, 80 + <&sata_crr4_lpcg IMX_LPCG_CLK_4>; 81 + clock-names = "sata", "sata_ref"; 82 + phy-names = "sata-phy", "cali-phy0", "cali-phy1"; 83 + power-domains = <&pd IMX_SC_R_SATA_0>; 84 + /* 85 + * Since "REXT" pin is only present for first lane PHY 86 + * and its calibration result will be stored, and shared 87 + * by the PHY used by SATA. 88 + * 89 + * Add the calibration PHYs for SATA here, although only 90 + * the third lane PHY is used by SATA. 91 + */ 92 + phys = <&hsio_phy 2 PHY_TYPE_SATA 0>, 93 + <&hsio_phy 0 PHY_TYPE_PCIE 0>, 94 + <&hsio_phy 1 PHY_TYPE_PCIE 1>; 95 + status = "disabled"; 96 + }; 97 + 98 + pciea_lpcg: clock-controller@5f050000 { 99 + compatible = "fsl,imx8qxp-lpcg"; 100 + reg = <0x5f050000 0x10000>; 101 + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; 102 + #clock-cells = <1>; 103 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; 104 + clock-output-names = "hsio_pciea_mstr_axi_clk", 105 + "hsio_pciea_slv_axi_clk", 106 + "hsio_pciea_dbi_axi_clk"; 107 + power-domains = <&pd IMX_SC_R_PCIE_A>; 108 + }; 109 + 110 + sata_lpcg: clock-controller@5f070000 { 111 + compatible = "fsl,imx8qxp-lpcg"; 112 + reg = <0x5f070000 0x10000>; 113 + clocks = <&hsio_axi_clk>; 114 + #clock-cells = <1>; 115 + clock-indices = <IMX_LPCG_CLK_4>; 116 + clock-output-names = "hsio_sata_clk"; 117 + power-domains = <&pd IMX_SC_R_SATA_0>; 118 + }; 119 + 120 + phyx2_lpcg: clock-controller@5f080000 { 121 + compatible = "fsl,imx8qxp-lpcg"; 122 + reg = <0x5f080000 0x10000>; 123 + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, 124 + <&hsio_refa_clk>, <&hsio_per_clk>; 125 + #clock-cells = <1>; 126 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 127 + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 128 + clock-output-names = "hsio_phyx2_pclk_0", 129 + "hsio_phyx2_pclk_1", 130 + "hsio_phyx2_apbclk_0", 131 + "hsio_phyx2_apbclk_1"; 132 + power-domains = <&pd IMX_SC_R_SERDES_0>; 133 + }; 134 + 135 + phyx1_lpcg: clock-controller@5f090000 { 136 + compatible = "fsl,imx8qxp-lpcg"; 137 + reg = <0x5f090000 0x10000>; 138 + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, 139 + <&hsio_per_clk>, <&hsio_per_clk>; 140 + #clock-cells = <1>; 141 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 142 + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>; 143 + clock-output-names = "hsio_phyx1_pclk", 144 + "hsio_phyx1_epcs_tx_clk", 145 + "hsio_phyx1_epcs_rx_clk", 146 + "hsio_phyx1_apb_clk"; 147 + power-domains = <&pd IMX_SC_R_SERDES_1>; 148 + }; 149 + 150 + phyx2_crr0_lpcg: clock-controller@5f0a0000 { 151 + compatible = "fsl,imx8qxp-lpcg"; 152 + reg = <0x5f0a0000 0x10000>; 153 + clocks = <&hsio_per_clk>; 154 + #clock-cells = <1>; 155 + clock-indices = <IMX_LPCG_CLK_4>; 156 + clock-output-names = "hsio_phyx2_per_clk"; 157 + power-domains = <&pd IMX_SC_R_SERDES_0>; 158 + }; 159 + 160 + pciea_crr2_lpcg: clock-controller@5f0c0000 { 161 + compatible = "fsl,imx8qxp-lpcg"; 162 + reg = <0x5f0c0000 0x10000>; 163 + clocks = <&hsio_per_clk>; 164 + #clock-cells = <1>; 165 + clock-indices = <IMX_LPCG_CLK_4>; 166 + clock-output-names = "hsio_pciea_per_clk"; 167 + power-domains = <&pd IMX_SC_R_PCIE_A>; 168 + }; 169 + 170 + sata_crr4_lpcg: clock-controller@5f0e0000 { 171 + compatible = "fsl,imx8qxp-lpcg"; 172 + reg = <0x5f0e0000 0x10000>; 173 + clocks = <&hsio_per_clk>; 174 + #clock-cells = <1>; 175 + clock-indices = <IMX_LPCG_CLK_4>; 176 + clock-output-names = "hsio_sata_per_clk"; 177 + power-domains = <&pd IMX_SC_R_SATA_0>; 178 + }; 179 + 180 + hsio_phy: phy@5f180000 { 181 + compatible = "fsl,imx8qm-hsio"; 182 + reg = <0x5f180000 0x30000>, 183 + <0x5f110000 0x20000>, 184 + <0x5f130000 0x30000>, 185 + <0x5f160000 0x10000>; 186 + reg-names = "reg", "phy", "ctrl", "misc"; 187 + clocks = <&phyx2_lpcg IMX_LPCG_CLK_0>, 188 + <&phyx2_lpcg IMX_LPCG_CLK_1>, 189 + <&phyx2_lpcg IMX_LPCG_CLK_4>, 190 + <&phyx2_lpcg IMX_LPCG_CLK_5>, 191 + <&phyx1_lpcg IMX_LPCG_CLK_0>, 192 + <&phyx1_lpcg IMX_LPCG_CLK_1>, 193 + <&phyx1_lpcg IMX_LPCG_CLK_2>, 194 + <&phyx1_lpcg IMX_LPCG_CLK_4>, 195 + <&phyx2_crr0_lpcg IMX_LPCG_CLK_4>, 196 + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, 197 + <&pciea_crr2_lpcg IMX_LPCG_CLK_4>, 198 + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, 199 + <&sata_crr4_lpcg IMX_LPCG_CLK_4>, 200 + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; 201 + clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1", 202 + "pclk2", "epcs_tx", "epcs_rx", "apb_pclk2", 203 + "phy0_crr", "phy1_crr", "ctl0_crr", 204 + "ctl1_crr", "ctl2_crr", "misc_crr"; 205 + #phy-cells = <3>; 206 + power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>; 207 + status = "disabled"; 208 + }; 209 + };
+34
arch/arm64/boot/dts/freescale/imx8qm.dtsi
··· 24 24 serial1 = &lpuart1; 25 25 serial2 = &lpuart2; 26 26 serial3 = &lpuart3; 27 + spi0 = &lpspi0; 28 + spi1 = &lpspi1; 29 + spi2 = &lpspi2; 30 + spi3 = &lpspi3; 27 31 vpu-core0 = &vpu_core0; 28 32 vpu-core1 = &vpu_core1; 29 33 vpu-core2 = &vpu_core2; ··· 585 581 clock-output-names = "mipi_pll_div2_clk"; 586 582 }; 587 583 584 + vpu_subsys_dsp: bus@55000000 { 585 + compatible = "simple-bus"; 586 + #address-cells = <1>; 587 + #size-cells = <1>; 588 + ranges = <0x55000000 0x0 0x55000000 0x1000000>; 589 + 590 + vpu_dsp: dsp@556e8000 { 591 + compatible = "fsl,imx8qm-hifi4"; 592 + reg = <0x556e8000 0x88000>; 593 + clocks = <&clk_dummy>, 594 + <&clk_dummy>, 595 + <&clk_dummy>; 596 + clock-names = "ipg", "ocram", "core"; 597 + power-domains = <&pd IMX_SC_R_MU_13B>, 598 + <&pd IMX_SC_R_DSP>, 599 + <&pd IMX_SC_R_DSP_RAM>, 600 + <&pd IMX_SC_R_MU_2A>; 601 + mboxes = <&lsio_mu13 0 0>, 602 + <&lsio_mu13 1 0>, 603 + <&lsio_mu13 3 0>; 604 + mbox-names = "tx", "rx", "rxdb"; 605 + firmware-name = "imx/dsp/hifi4.bin"; 606 + status = "disabled"; 607 + }; 608 + }; 609 + 588 610 /* sorted in register address */ 589 611 #include "imx8-ss-cm41.dtsi" 590 612 #include "imx8-ss-audio.dtsi" ··· 624 594 #include "imx8-ss-dma.dtsi" 625 595 #include "imx8-ss-conn.dtsi" 626 596 #include "imx8-ss-lsio.dtsi" 597 + #include "imx8-ss-hsio.dtsi" 627 598 }; 628 599 629 600 #include "imx8qm-ss-img.dtsi" ··· 634 603 #include "imx8qm-ss-audio.dtsi" 635 604 #include "imx8qm-ss-lvds.dtsi" 636 605 #include "imx8qm-ss-mipi.dtsi" 606 + #include "imx8qm-ss-hsio.dtsi" 607 + 608 + /delete-node/ &dsp;
+297 -1
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
··· 12 12 model = "Freescale i.MX8QXP MEK"; 13 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 14 14 15 + bt_sco_codec: audio-codec-bt { 16 + compatible = "linux,bt-sco"; 17 + #sound-dai-cells = <1>; 18 + }; 19 + 15 20 chosen { 16 21 stdout-path = &lpuart0; 22 + }; 23 + 24 + imx8x_cm4: imx8x-cm4 { 25 + compatible = "fsl,imx8qxp-cm4"; 26 + mbox-names = "tx", "rx", "rxdb"; 27 + mboxes = <&lsio_mu5 0 1 28 + &lsio_mu5 1 1 29 + &lsio_mu5 3 1>; 30 + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 31 + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 32 + power-domains = <&pd IMX_SC_R_M4_0_PID0>, 33 + <&pd IMX_SC_R_M4_0_MU_1A>; 34 + fsl,entry-address = <0x34fe0000>; 35 + fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 17 36 }; 18 37 19 38 memory@80000000 { 20 39 device_type = "memory"; 21 40 reg = <0x00000000 0x80000000 0 0x40000000>; 41 + }; 42 + 43 + reserved-memory { 44 + dsp_vdev0vring0: memory@942f0000 { 45 + reg = <0 0x942f0000 0 0x8000>; 46 + no-map; 47 + }; 48 + 49 + dsp_vdev0vring1: memory@942f8000 { 50 + reg = <0 0x942f8000 0 0x8000>; 51 + no-map; 52 + }; 53 + 54 + dsp_vdev0buffer: memory@94300000 { 55 + compatible = "shared-dma-pool"; 56 + reg = <0 0x94300000 0 0x100000>; 57 + no-map; 58 + }; 22 59 }; 23 60 24 61 reg_usdhc2_vmmc: usdhc2-vmmc { ··· 82 45 }; 83 46 }; 84 47 48 + reg_pcieb: regulator-pcie { 49 + compatible = "regulator-fixed"; 50 + regulator-max-microvolt = <3300000>; 51 + regulator-min-microvolt = <3300000>; 52 + regulator-name = "mpcie_3v3"; 53 + gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; 54 + enable-active-high; 55 + }; 56 + 57 + reg_audio: regulator-audio { 58 + compatible = "regulator-fixed"; 59 + regulator-max-microvolt = <3300000>; 60 + regulator-min-microvolt = <3300000>; 61 + regulator-name = "cs42888_supply"; 62 + }; 63 + 64 + reg_can_en: regulator-can-en { 65 + compatible = "regulator-fixed"; 66 + regulator-max-microvolt = <3300000>; 67 + regulator-min-microvolt = <3300000>; 68 + regulator-name = "can-en"; 69 + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 70 + enable-active-high; 71 + }; 72 + 73 + reg_can_stby: regulator-can-stby { 74 + compatible = "regulator-fixed"; 75 + regulator-max-microvolt = <3300000>; 76 + regulator-min-microvolt = <3300000>; 77 + regulator-name = "can-stby"; 78 + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 79 + enable-active-high; 80 + vin-supply = <&reg_can_en>; 81 + }; 82 + 83 + reg_usb_otg1_vbus: regulator-usbotg1-vbus { 84 + compatible = "regulator-fixed"; 85 + regulator-max-microvolt = <5000000>; 86 + regulator-min-microvolt = <5000000>; 87 + regulator-name = "usb_otg1_vbus"; 88 + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; 89 + enable-active-high; 90 + }; 91 + 92 + reserved-memory { 93 + #address-cells = <2>; 94 + #size-cells = <2>; 95 + ranges; 96 + 97 + vdev0vring0: memory@90000000 { 98 + reg = <0 0x90000000 0 0x8000>; 99 + no-map; 100 + }; 101 + 102 + vdev0vring1: memory@90008000 { 103 + reg = <0 0x90008000 0 0x8000>; 104 + no-map; 105 + }; 106 + 107 + vdev1vring0: memory@90010000 { 108 + reg = <0 0x90010000 0 0x8000>; 109 + no-map; 110 + }; 111 + 112 + vdev1vring1: memory@90018000 { 113 + reg = <0 0x90018000 0 0x8000>; 114 + no-map; 115 + }; 116 + 117 + rsc_table: memory@900ff000 { 118 + reg = <0 0x900ff000 0 0x1000>; 119 + no-map; 120 + }; 121 + 122 + vdevbuffer: memory@90400000 { 123 + compatible = "shared-dma-pool"; 124 + reg = <0 0x90400000 0 0x100000>; 125 + no-map; 126 + }; 127 + 128 + gpu_reserved: memory@880000000 { 129 + no-map; 130 + reg = <0x8 0x80000000 0 0x10000000>; 131 + }; 132 + }; 133 + 134 + sound-bt-sco { 135 + compatible = "simple-audio-card"; 136 + simple-audio-card,bitclock-inversion; 137 + simple-audio-card,bitclock-master = <&btcpu>; 138 + simple-audio-card,format = "dsp_a"; 139 + simple-audio-card,frame-master = <&btcpu>; 140 + simple-audio-card,name = "bt-sco-audio"; 141 + 142 + simple-audio-card,codec { 143 + sound-dai = <&bt_sco_codec 1>; 144 + }; 145 + 146 + btcpu: simple-audio-card,cpu { 147 + dai-tdm-slot-num = <2>; 148 + dai-tdm-slot-width = <16>; 149 + sound-dai = <&sai0>; 150 + }; 151 + }; 152 + 153 + sound-cs42888 { 154 + compatible = "fsl,imx-audio-cs42888"; 155 + audio-asrc = <&asrc0>; 156 + audio-codec = <&cs42888>; 157 + audio-cpu = <&esai0>; 158 + audio-routing = 159 + "Line Out Jack", "AOUT1L", 160 + "Line Out Jack", "AOUT1R", 161 + "Line Out Jack", "AOUT2L", 162 + "Line Out Jack", "AOUT2R", 163 + "Line Out Jack", "AOUT3L", 164 + "Line Out Jack", "AOUT3R", 165 + "Line Out Jack", "AOUT4L", 166 + "Line Out Jack", "AOUT4R", 167 + "AIN1L", "Line In Jack", 168 + "AIN1R", "Line In Jack", 169 + "AIN2L", "Line In Jack", 170 + "AIN2R", "Line In Jack"; 171 + model = "imx-cs42888"; 172 + }; 173 + 85 174 sound-wm8960 { 86 175 compatible = "fsl,imx-audio-wm8960"; 87 176 model = "wm8960-audio"; ··· 225 62 }; 226 63 }; 227 64 65 + &amix { 66 + status = "okay"; 67 + }; 68 + 69 + &asrc0 { 70 + fsl,asrc-rate = <48000>; 71 + status = "okay"; 72 + }; 73 + 228 74 &dsp { 229 - memory-region = <&dsp_reserved>; 75 + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 76 + <&dsp_vdev0vring1>, <&dsp_reserved>; 230 77 status = "okay"; 231 78 }; 232 79 233 80 &dsp_reserved { 81 + status = "okay"; 82 + }; 83 + 84 + &esai0 { 85 + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 86 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 87 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 88 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 89 + <&esai0_lpcg IMX_LPCG_CLK_0>; 90 + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; 91 + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; 92 + pinctrl-0 = <&pinctrl_esai0>; 93 + pinctrl-names = "default"; 234 94 status = "okay"; 235 95 }; 236 96 ··· 426 240 gpio-controller; 427 241 #gpio-cells = <2>; 428 242 }; 243 + 244 + cs42888: audio-codec@48 { 245 + compatible = "cirrus,cs42888"; 246 + reg = <0x48>; 247 + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 248 + clock-names = "mclk"; 249 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 250 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 251 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 252 + <&mclkout0_lpcg IMX_LPCG_CLK_0>; 253 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 254 + reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>; 255 + VA-supply = <&reg_audio>; 256 + VD-supply = <&reg_audio>; 257 + VLC-supply = <&reg_audio>; 258 + VLS-supply = <&reg_audio>; 259 + }; 429 260 }; 430 261 431 262 &cm40_intmux { 263 + status = "okay"; 264 + }; 265 + 266 + &hsio_phy { 267 + fsl,hsio-cfg = "pciea-x2-pcieb"; 268 + fsl,refclk-pad-mode = "input"; 269 + status = "okay"; 270 + }; 271 + 272 + &flexcan1 { 273 + pinctrl-0 = <&pinctrl_flexcan1>; 274 + pinctrl-names = "default"; 275 + xceiver-supply = <&reg_can_stby>; 276 + status = "okay"; 277 + }; 278 + 279 + &flexcan2 { 280 + pinctrl-0 = <&pinctrl_flexcan2>; 281 + pinctrl-names = "default"; 282 + xceiver-supply = <&reg_can_stby>; 283 + status = "okay"; 284 + }; 285 + 286 + &jpegdec { 287 + status = "okay"; 288 + }; 289 + 290 + &jpegenc { 432 291 status = "okay"; 433 292 }; 434 293 ··· 495 264 status = "okay"; 496 265 }; 497 266 267 + &lsio_mu5 { 268 + status = "okay"; 269 + }; 270 + 498 271 &mu_m0 { 499 272 status = "okay"; 500 273 }; 501 274 502 275 &mu1_m0 { 276 + status = "okay"; 277 + }; 278 + 279 + &pcieb { 280 + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 281 + phy-names = "pcie-phy"; 282 + pinctrl-0 = <&pinctrl_pcieb>; 283 + pinctrl-names = "default"; 284 + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; 285 + vpcie-supply = <&reg_pcieb>; 503 286 status = "okay"; 504 287 }; 505 288 ··· 629 384 status = "okay"; 630 385 }; 631 386 387 + &usbphy1 { 388 + status = "okay"; 389 + }; 390 + 391 + &usbotg1 { 392 + adp-disable; 393 + hnp-disable; 394 + srp-disable; 395 + disable-over-current; 396 + power-active-high; 397 + vbus-supply = <&reg_usb_otg1_vbus>; 398 + status = "okay"; 399 + }; 400 + 632 401 &usbotg3 { 633 402 status = "okay"; 634 403 }; ··· 693 434 >; 694 435 }; 695 436 437 + pinctrl_esai0: esai0grp { 438 + fsl,pins = < 439 + IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 440 + IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 441 + IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 442 + IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 443 + IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 444 + IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 445 + IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 446 + IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 447 + IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 448 + IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 449 + >; 450 + }; 451 + 696 452 pinctrl_fec1: fec1grp { 697 453 fsl,pins = < 698 454 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 ··· 724 450 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 725 451 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 726 452 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 453 + >; 454 + }; 455 + 456 + pinctrl_flexcan1: flexcan0grp { 457 + fsl,pins = < 458 + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 459 + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 460 + >; 461 + }; 462 + 463 + pinctrl_flexcan2: flexcan1grp { 464 + fsl,pins = < 465 + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 466 + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 727 467 >; 728 468 }; 729 469 ··· 778 490 fsl,pins = < 779 491 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 780 492 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 493 + >; 494 + }; 495 + 496 + pinctrl_pcieb: pcieagrp { 497 + fsl,pins = < 498 + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 499 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021 500 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 781 501 >; 782 502 }; 783 503
+4
arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
··· 4 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 5 */ 6 6 7 + &usbphy1 { 8 + compatible = "fsl,imx8qxp-usbphy", "fsl,imx7ulp-usbphy"; 9 + }; 10 + 7 11 &usdhc1 { 8 12 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 9 13 };
+41
arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright 2024 NXP 4 + * Richard Zhu <hongxing.zhu@nxp.com> 5 + */ 6 + 7 + &hsio_subsys { 8 + phyx1_lpcg: clock-controller@5f090000 { 9 + compatible = "fsl,imx8qxp-lpcg"; 10 + reg = <0x5f090000 0x10000>; 11 + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, 12 + <&hsio_per_clk>, <&hsio_per_clk>; 13 + #clock-cells = <1>; 14 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 15 + <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>; 16 + clock-output-names = "hsio_phyx1_pclk", 17 + "hsio_phyx1_epcs_tx_clk", 18 + "hsio_phyx1_epcs_rx_clk", 19 + "hsio_phyx1_apb_clk"; 20 + power-domains = <&pd IMX_SC_R_SERDES_1>; 21 + }; 22 + 23 + hsio_phy: phy@5f1a0000 { 24 + compatible = "fsl,imx8qxp-hsio"; 25 + reg = <0x5f1a0000 0x10000>, 26 + <0x5f120000 0x10000>, 27 + <0x5f140000 0x10000>, 28 + <0x5f160000 0x10000>; 29 + reg-names = "reg", "phy", "ctrl", "misc"; 30 + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, 31 + <&phyx1_lpcg IMX_LPCG_CLK_1>, 32 + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, 33 + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, 34 + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; 35 + clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", 36 + "misc_crr"; 37 + #phy-cells = <3>; 38 + power-domains = <&pd IMX_SC_R_SERDES_1>; 39 + status = "disabled"; 40 + }; 41 + };
+6
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
··· 46 46 serial1 = &lpuart1; 47 47 serial2 = &lpuart2; 48 48 serial3 = &lpuart3; 49 + spi0 = &lpspi0; 50 + spi1 = &lpspi1; 51 + spi2 = &lpspi2; 52 + spi3 = &lpspi3; 49 53 vpu-core0 = &vpu_core0; 50 54 vpu-core1 = &vpu_core1; 51 55 }; ··· 327 323 #include "imx8-ss-conn.dtsi" 328 324 #include "imx8-ss-ddr.dtsi" 329 325 #include "imx8-ss-lsio.dtsi" 326 + #include "imx8-ss-hsio.dtsi" 330 327 }; 331 328 332 329 #include "imx8qxp-ss-img.dtsi" ··· 335 330 #include "imx8qxp-ss-adma.dtsi" 336 331 #include "imx8qxp-ss-conn.dtsi" 337 332 #include "imx8qxp-ss-lsio.dtsi" 333 + #include "imx8qxp-ss-hsio.dtsi"
+70
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
··· 11 11 model = "NXP i.MX8ULP EVK"; 12 12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13 13 14 + bt_sco_codec: bt-sco-codec { 15 + #sound-dai-cells = <1>; 16 + compatible = "linux,bt-sco"; 17 + }; 18 + 14 19 chosen { 15 20 stdout-path = &lpuart5; 16 21 }; ··· 88 83 clock-output-names = "ext_ts_clk"; 89 84 #clock-cells = <0>; 90 85 }; 86 + 87 + sound-bt-sco { 88 + compatible = "simple-audio-card"; 89 + simple-audio-card,name = "bt-sco-audio"; 90 + simple-audio-card,format = "dsp_a"; 91 + simple-audio-card,bitclock-inversion; 92 + simple-audio-card,frame-master = <&btcpu>; 93 + simple-audio-card,bitclock-master = <&btcpu>; 94 + 95 + btcpu: simple-audio-card,cpu { 96 + sound-dai = <&sai5>; 97 + dai-tdm-slot-num = <2>; 98 + dai-tdm-slot-width = <16>; 99 + }; 100 + 101 + simple-audio-card,codec { 102 + sound-dai = <&bt_sco_codec 1>; 103 + }; 104 + }; 105 + 106 + sound-spdif { 107 + compatible = "fsl,imx-audio-spdif"; 108 + model = "imx-spdif"; 109 + audio-cpu = <&spdif>; 110 + audio-codec = <&spdif_out>; 111 + }; 112 + 113 + spdif_out: spdif-out { 114 + compatible = "linux,spdif-dit"; 115 + #sound-dai-cells = <0>; 116 + }; 91 117 }; 92 118 93 119 &cm33 { ··· 187 151 pinctrl-0 = <&pinctrl_typec2>; 188 152 status = "disabled"; 189 153 }; 154 + }; 155 + 156 + &sai5 { 157 + pinctrl-names = "default", "sleep"; 158 + pinctrl-0 = <&pinctrl_sai5>; 159 + pinctrl-1 = <&pinctrl_sai5>; 160 + assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>; 161 + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; 162 + fsl,dataline = <1 0x08 0x01>; 163 + status = "okay"; 164 + }; 165 + 166 + &spdif { 167 + pinctrl-names = "default", "sleep"; 168 + pinctrl-0 = <&pinctrl_spdif>; 169 + pinctrl-1 = <&pinctrl_spdif>; 170 + assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>; 171 + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; 172 + status = "okay"; 190 173 }; 191 174 192 175 &usbotg1 { ··· 334 279 fsl,pins = < 335 280 MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 336 281 MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 282 + >; 283 + }; 284 + 285 + pinctrl_sai5: sai5grp { 286 + fsl,pins = < 287 + MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43 288 + MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43 289 + MX8ULP_PAD_PTF28__I2S5_TXD0 0x43 290 + MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 291 + >; 292 + }; 293 + 294 + pinctrl_spdif: spdifgrp { 295 + fsl,pins = < 296 + MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43 337 297 >; 338 298 }; 339 299
+214
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
··· 28 28 serial1 = &lpuart5; 29 29 serial2 = &lpuart6; 30 30 serial3 = &lpuart7; 31 + spi0 = &lpspi4; 32 + spi1 = &lpspi5; 31 33 }; 32 34 33 35 cpus { ··· 213 211 #address-cells = <1>; 214 212 #size-cells = <1>; 215 213 ranges; 214 + 215 + edma1: dma-controller@29010000 { 216 + compatible = "fsl,imx8ulp-edma"; 217 + reg = <0x29010000 0x210000>; 218 + #dma-cells = <3>; 219 + dma-channels = <32>; 220 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 221 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 222 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 223 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 224 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 225 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 226 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 227 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 228 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 229 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 230 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 231 + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 232 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 233 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 234 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 235 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 236 + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 237 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 238 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 239 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 240 + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 241 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 242 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 243 + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 244 + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 245 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 246 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 247 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 248 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 249 + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 250 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 251 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 252 + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, 253 + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, 254 + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, 255 + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, 256 + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, 257 + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, 258 + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, 259 + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, 260 + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, 261 + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, 262 + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, 263 + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, 264 + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, 265 + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, 266 + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, 267 + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, 268 + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; 269 + clock-names = "dma", "ch00","ch01", "ch02", "ch03", 270 + "ch04", "ch05", "ch06", "ch07", 271 + "ch08", "ch09", "ch10", "ch11", 272 + "ch12", "ch13", "ch14", "ch15", 273 + "ch16", "ch17", "ch18", "ch19", 274 + "ch20", "ch21", "ch22", "ch23", 275 + "ch24", "ch25", "ch26", "ch27", 276 + "ch28", "ch29", "ch30", "ch31"; 277 + }; 216 278 217 279 mu: mailbox@29220000 { 218 280 compatible = "fsl,imx8ulp-mu"; ··· 508 442 status = "disabled"; 509 443 }; 510 444 445 + sai4: sai@29880000 { 446 + compatible = "fsl,imx8ulp-sai"; 447 + reg = <0x29880000 0x10000>; 448 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 449 + clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, 450 + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 451 + <&cgc1 IMX8ULP_CLK_DUMMY>; 452 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 453 + dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; 454 + dma-names = "rx", "tx"; 455 + #sound-dai-cells = <0>; 456 + fsl,dataline = <0 0x03 0x03>; 457 + status = "disabled"; 458 + }; 459 + 460 + sai5: sai@29890000 { 461 + compatible = "fsl,imx8ulp-sai"; 462 + reg = <0x29890000 0x10000>; 463 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 464 + clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, 465 + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 466 + <&cgc1 IMX8ULP_CLK_DUMMY>; 467 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 468 + dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; 469 + dma-names = "rx", "tx"; 470 + #sound-dai-cells = <0>; 471 + fsl,dataline = <0 0x0f 0x0f>; 472 + status = "disabled"; 473 + }; 474 + 511 475 iomuxc1: pinctrl@298c0000 { 512 476 compatible = "fsl,imx8ulp-iomuxc1"; 513 477 reg = <0x298c0000 0x10000>; ··· 710 614 #size-cells = <1>; 711 615 ranges; 712 616 617 + edma2: dma-controller@2d800000 { 618 + compatible = "fsl,imx8ulp-edma"; 619 + reg = <0x2d800000 0x210000>; 620 + #dma-cells = <3>; 621 + dma-channels = <32>; 622 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 623 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 624 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 625 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 626 + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 627 + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 628 + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 629 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 630 + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 631 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 632 + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 633 + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 634 + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 635 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 636 + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 637 + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 638 + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 639 + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 640 + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 641 + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 642 + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 643 + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 644 + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 645 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 646 + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 647 + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 648 + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 649 + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 650 + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 651 + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 652 + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 653 + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 654 + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, 655 + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, 656 + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, 657 + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, 658 + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, 659 + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, 660 + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, 661 + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, 662 + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, 663 + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, 664 + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, 665 + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, 666 + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, 667 + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, 668 + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, 669 + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, 670 + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; 671 + clock-names = "dma", "ch00","ch01", "ch02", "ch03", 672 + "ch04", "ch05", "ch06", "ch07", 673 + "ch08", "ch09", "ch10", "ch11", 674 + "ch12", "ch13", "ch14", "ch15", 675 + "ch16", "ch17", "ch18", "ch19", 676 + "ch20", "ch21", "ch22", "ch23", 677 + "ch24", "ch25", "ch26", "ch27", 678 + "ch28", "ch29", "ch30", "ch31"; 679 + }; 680 + 713 681 cgc2: clock-controller@2da60000 { 714 682 compatible = "fsl,imx8ulp-cgc2"; 715 683 reg = <0x2da60000 0x10000>; ··· 785 625 reg = <0x2da70000 0x10000>; 786 626 #clock-cells = <1>; 787 627 #reset-cells = <1>; 628 + }; 629 + 630 + sai6: sai@2da90000 { 631 + compatible = "fsl,imx8ulp-sai"; 632 + reg = <0x2da90000 0x10000>; 633 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 634 + clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, 635 + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 636 + <&cgc1 IMX8ULP_CLK_DUMMY>; 637 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 638 + dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; 639 + dma-names = "rx", "tx"; 640 + #sound-dai-cells = <0>; 641 + fsl,dataline = <0 0x0f 0x0f>; 642 + status = "disabled"; 643 + }; 644 + 645 + sai7: sai@2daa0000 { 646 + compatible = "fsl,imx8ulp-sai"; 647 + reg = <0x2daa0000 0x10000>; 648 + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 649 + clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, 650 + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, 651 + <&cgc1 IMX8ULP_CLK_DUMMY>; 652 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 653 + dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; 654 + dma-names = "rx", "tx"; 655 + #sound-dai-cells = <0>; 656 + fsl,dataline = <0 0x0f 0x0f>; 657 + status = "disabled"; 658 + }; 659 + 660 + spdif: spdif@2dab0000 { 661 + compatible = "fsl,imx8ulp-spdif"; 662 + reg = <0x2dab0000 0x10000>; 663 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 664 + clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ 665 + <&sosc>, /* 0, extal */ 666 + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ 667 + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ 668 + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ 669 + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ 670 + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ 671 + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ 672 + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ 673 + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ 674 + clock-names = "core", "rxtx0", 675 + "rxtx1", "rxtx2", 676 + "rxtx3", "rxtx4", 677 + "rxtx5", "rxtx6", 678 + "rxtx7", "spba"; 679 + dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; 680 + dma-names = "rx", "tx"; 681 + status = "disabled"; 788 682 }; 789 683 }; 790 684
+2 -2
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
··· 166 166 }; 167 167 168 168 /* Touch controller */ 169 - touchscreen@2c { 169 + ad7879_ts: touchscreen@2c { 170 170 compatible = "adi,ad7879-1"; 171 171 pinctrl-names = "default"; 172 172 pinctrl-0 = <&pinctrl_ad7879_int>; ··· 698 698 699 699 /* 700 700 * This pin is used in the SCFW as a UART. Using it from 701 - * Linux would require rewritting the SCFW board file. 701 + * Linux would require rewriting the SCFW board file. 702 702 */ 703 703 pinctrl_hog_scfw: hogscfwgrp { 704 704 fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */
+111 -4
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
··· 78 78 regulator-max-microvolt = <1800000>; 79 79 }; 80 80 81 + reg_audio_pwr: regulator-audio-pwr { 82 + compatible = "regulator-fixed"; 83 + regulator-name = "audio-pwr"; 84 + regulator-min-microvolt = <3300000>; 85 + regulator-max-microvolt = <3300000>; 86 + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 87 + enable-active-high; 88 + }; 89 + 90 + reg_can2_standby: regulator-can2-standby { 91 + compatible = "regulator-fixed"; 92 + regulator-name = "can2-stby"; 93 + regulator-min-microvolt = <3300000>; 94 + regulator-max-microvolt = <3300000>; 95 + gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; 96 + }; 97 + 81 98 reg_usdhc2_vmmc: regulator-usdhc2 { 82 99 compatible = "regulator-fixed"; 83 100 pinctrl-names = "default"; ··· 154 137 sound-dai = <&micfil>; 155 138 }; 156 139 }; 140 + }; 141 + 142 + sound-wm8962 { 143 + compatible = "fsl,imx-audio-wm8962"; 144 + model = "wm8962-audio"; 145 + audio-cpu = <&sai3>; 146 + audio-codec = <&wm8962>; 147 + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 148 + audio-routing = 149 + "Headphone Jack", "HPOUTL", 150 + "Headphone Jack", "HPOUTR", 151 + "Ext Spk", "SPKOUTL", 152 + "Ext Spk", "SPKOUTR", 153 + "AMIC", "MICBIAS", 154 + "IN3R", "AMIC", 155 + "IN1R", "AMIC"; 157 156 }; 158 157 159 158 sound-xcvr { ··· 249 216 }; 250 217 }; 251 218 219 + &flexcan2 { 220 + pinctrl-names = "default"; 221 + pinctrl-0 = <&pinctrl_flexcan2>; 222 + xceiver-supply = <&reg_can2_standby>; 223 + status = "okay"; 224 + }; 225 + 252 226 &lpi2c1 { 253 227 clock-frequency = <400000>; 254 228 pinctrl-names = "default"; 255 229 pinctrl-0 = <&pinctrl_lpi2c1>; 256 230 status = "okay"; 231 + 232 + wm8962: codec@1a { 233 + compatible = "wlf,wm8962"; 234 + reg = <0x1a>; 235 + clocks = <&clk IMX93_CLK_SAI3_GATE>; 236 + DCVDD-supply = <&reg_audio_pwr>; 237 + DBVDD-supply = <&reg_audio_pwr>; 238 + AVDD-supply = <&reg_audio_pwr>; 239 + CPVDD-supply = <&reg_audio_pwr>; 240 + MICVDD-supply = <&reg_audio_pwr>; 241 + PLLVDD-supply = <&reg_audio_pwr>; 242 + SPKVDD1-supply = <&reg_audio_pwr>; 243 + SPKVDD2-supply = <&reg_audio_pwr>; 244 + gpio-cfg = < 245 + 0x0000 /* 0:Default */ 246 + 0x0000 /* 1:Default */ 247 + 0x0000 /* 2:FN_DMICCLK */ 248 + 0x0000 /* 3:Default */ 249 + 0x0000 /* 4:FN_DMICCDAT */ 250 + 0x0000 /* 5:Default */ 251 + >; 252 + }; 257 253 258 254 inertial-meter@6a { 259 255 compatible = "st,lsm6dso"; ··· 292 230 293 231 &lpi2c2 { 294 232 clock-frequency = <400000>; 295 - pinctrl-names = "default", "sleep"; 233 + pinctrl-names = "default"; 296 234 pinctrl-0 = <&pinctrl_lpi2c2>; 297 - pinctrl-1 = <&pinctrl_lpi2c2>; 298 235 status = "okay"; 299 236 300 237 pcal6524: gpio@22 { ··· 334 273 regulator-ramp-delay = <3125>; 335 274 }; 336 275 337 - buck4: BUCK4{ 276 + buck4: BUCK4 { 338 277 regulator-name = "BUCK4"; 339 278 regulator-min-microvolt = <1620000>; 340 279 regulator-max-microvolt = <3400000>; ··· 342 281 regulator-always-on; 343 282 }; 344 283 345 - buck5: BUCK5{ 284 + buck5: BUCK5 { 346 285 regulator-name = "BUCK5"; 347 286 regulator-min-microvolt = <1620000>; 348 287 regulator-max-microvolt = <3400000>; ··· 400 339 pinctrl-names = "default"; 401 340 pinctrl-0 = <&pinctrl_lpi2c3>; 402 341 status = "okay"; 342 + 343 + adp5585_isp: io-expander@34 { 344 + compatible = "adi,adp5585-01", "adi,adp5585"; 345 + reg = <0x34>; 346 + gpio-controller; 347 + #gpio-cells = <2>; 348 + #pwm-cells = <3>; 349 + }; 403 350 404 351 ptn5110: tcpc@50 { 405 352 compatible = "nxp,ptn5110", "tcpci"; ··· 518 449 pinctrl-0 = <&pinctrl_sai1>; 519 450 pinctrl-1 = <&pinctrl_sai1_sleep>; 520 451 assigned-clocks = <&clk IMX93_CLK_SAI1>; 452 + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 453 + assigned-clock-rates = <12288000>; 454 + fsl,sai-mclk-direction-output; 455 + status = "okay"; 456 + }; 457 + 458 + &sai3 { 459 + pinctrl-names = "default", "sleep"; 460 + pinctrl-0 = <&pinctrl_sai3>; 461 + pinctrl-1 = <&pinctrl_sai3_sleep>; 462 + assigned-clocks = <&clk IMX93_CLK_SAI3>; 521 463 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 522 464 assigned-clock-rates = <12288000>; 523 465 fsl,sai-mclk-direction-output; ··· 694 614 >; 695 615 }; 696 616 617 + pinctrl_flexcan2: flexcan2grp { 618 + fsl,pins = < 619 + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 620 + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 621 + >; 622 + }; 623 + 697 624 pinctrl_uart1: uart1grp { 698 625 fsl,pins = < 699 626 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e ··· 832 745 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 833 746 fsl,pins = < 834 747 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 748 + >; 749 + }; 750 + 751 + pinctrl_sai3: sai3grp { 752 + fsl,pins = < 753 + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 754 + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 755 + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 756 + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 757 + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 758 + >; 759 + }; 760 + 761 + pinctrl_sai3_sleep: sai3sleepgrp { 762 + fsl,pins = < 763 + MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e 764 + MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e 765 + MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e 766 + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e 767 + MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e 835 768 >; 836 769 }; 837 770
+72
arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright 2024 NXP 4 + */ 5 + 6 + #include <dt-bindings/interrupt-controller/irq.h> 7 + #include <dt-bindings/i3c/i3c.h> 8 + #include <dt-bindings/usb/pd.h> 9 + 10 + #include "imx93-pinfunc.h" 11 + 12 + /dts-v1/; 13 + /plugin/; 14 + 15 + &lpi2c1 { 16 + status = "disabled"; 17 + }; 18 + 19 + &i3c1 { 20 + pinctrl-names = "default"; 21 + pinctrl-0 = <&pinctrl_i3c1>; 22 + #address-cells = <3>; 23 + #size-cells = <0>; 24 + i2c-scl-hz = <400000>; 25 + status = "okay"; 26 + 27 + tcpc@50 { 28 + compatible = "nxp,ptn5110", "tcpci"; 29 + reg = <0x50 0x00 (I2C_FM | I2C_NO_FILTER_LOW_FREQUENCY)>; 30 + interrupt-parent = <&gpio3>; 31 + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 32 + 33 + connector { 34 + compatible = "usb-c-connector"; 35 + label = "USB-C"; 36 + power-role = "dual"; 37 + data-role = "dual"; 38 + try-power-role = "sink"; 39 + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 40 + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 41 + PDO_VAR(5000, 20000, 3000)>; 42 + op-sink-microwatt = <15000000>; 43 + self-powered; 44 + 45 + ports { 46 + #address-cells = <1>; 47 + #size-cells = <0>; 48 + 49 + port@0 { 50 + reg = <0>; 51 + 52 + typec1_dr_sw: endpoint { 53 + remote-endpoint = <&usb1_drd_sw>; 54 + }; 55 + }; 56 + }; 57 + }; 58 + }; 59 + }; 60 + 61 + &usb1_drd_sw { 62 + remote-endpoint = <&typec1_dr_sw>; 63 + }; 64 + 65 + &iomuxc { 66 + pinctrl_i3c1: i3c1grp { 67 + fsl,pins = < 68 + MX93_PAD_I2C1_SCL__I3C1_SCL 0x40000186 69 + MX93_PAD_I2C1_SDA__I3C1_SDA 0x40000186 70 + >; 71 + }; 72 + };
+156 -2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
··· 12 12 model = "NXP i.MX93 9x9 Quick Start Board"; 13 13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; 14 14 15 + bt_sco_codec: bt-sco-codec { 16 + #sound-dai-cells = <1>; 17 + compatible = "linux,bt-sco"; 18 + }; 19 + 15 20 chosen { 16 21 stdout-path = &lpuart1; 17 22 }; ··· 73 68 regulator-max-microvolt = <1800000>; 74 69 }; 75 70 71 + reg_audio_pwr: regulator-audio-pwr { 72 + compatible = "regulator-fixed"; 73 + regulator-name = "audio-pwr"; 74 + regulator-min-microvolt = <3300000>; 75 + regulator-max-microvolt = <3300000>; 76 + gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; 77 + enable-active-high; 78 + }; 79 + 76 80 reg_rpi_3v3: regulator-rpi { 77 81 compatible = "regulator-fixed"; 78 82 regulator-name = "VDD_RPI_3V3"; ··· 101 87 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 102 88 enable-active-high; 103 89 off-on-delay-us = <12000>; 90 + }; 91 + 92 + sound-bt-sco { 93 + compatible = "simple-audio-card"; 94 + simple-audio-card,name = "bt-sco-audio"; 95 + simple-audio-card,format = "dsp_a"; 96 + simple-audio-card,bitclock-inversion; 97 + simple-audio-card,frame-master = <&btcpu>; 98 + simple-audio-card,bitclock-master = <&btcpu>; 99 + 100 + btcpu: simple-audio-card,cpu { 101 + sound-dai = <&sai1>; 102 + dai-tdm-slot-num = <2>; 103 + dai-tdm-slot-width = <16>; 104 + }; 105 + 106 + simple-audio-card,codec { 107 + sound-dai = <&bt_sco_codec 1>; 108 + }; 109 + }; 110 + 111 + sound-micfil { 112 + compatible = "fsl,imx-audio-card"; 113 + model = "micfil-audio"; 114 + 115 + pri-dai-link { 116 + link-name = "micfil hifi"; 117 + format = "i2s"; 118 + 119 + cpu { 120 + sound-dai = <&micfil>; 121 + }; 122 + }; 123 + }; 124 + 125 + sound-wm8962 { 126 + compatible = "fsl,imx-audio-wm8962"; 127 + model = "wm8962-audio"; 128 + audio-cpu = <&sai3>; 129 + audio-codec = <&wm8962>; 130 + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 131 + audio-routing = 132 + "Headphone Jack", "HPOUTL", 133 + "Headphone Jack", "HPOUTR", 134 + "Ext Spk", "SPKOUTL", 135 + "Ext Spk", "SPKOUTR", 136 + "AMIC", "MICBIAS", 137 + "IN3R", "AMIC", 138 + "IN1R", "AMIC"; 104 139 }; 105 140 }; 106 141 ··· 198 135 pinctrl-names = "default"; 199 136 pinctrl-0 = <&pinctrl_lpi2c1>; 200 137 status = "okay"; 138 + 139 + wm8962: audio-codec@1a { 140 + compatible = "wlf,wm8962"; 141 + reg = <0x1a>; 142 + clocks = <&clk IMX93_CLK_SAI3_GATE>; 143 + DCVDD-supply = <&reg_audio_pwr>; 144 + DBVDD-supply = <&reg_audio_pwr>; 145 + AVDD-supply = <&reg_audio_pwr>; 146 + CPVDD-supply = <&reg_audio_pwr>; 147 + MICVDD-supply = <&reg_audio_pwr>; 148 + PLLVDD-supply = <&reg_audio_pwr>; 149 + SPKVDD1-supply = <&reg_audio_pwr>; 150 + SPKVDD2-supply = <&reg_audio_pwr>; 151 + gpio-cfg = < 152 + 0x0000 /* 0:Default */ 153 + 0x0000 /* 1:Default */ 154 + 0x0000 /* 2:FN_DMICCLK */ 155 + 0x0000 /* 3:Default */ 156 + 0x0000 /* 4:FN_DMICCDAT */ 157 + 0x0000 /* 5:Default */ 158 + >; 159 + }; 201 160 202 161 ptn5110: tcpc@50 { 203 162 compatible = "nxp,ptn5110", "tcpci"; ··· 279 194 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 280 195 pinctrl-names = "default"; 281 196 pinctrl-0 = <&pinctrl_pcal6524>; 197 + 198 + exp-sel-hog { 199 + gpio-hog; 200 + gpios = <22 GPIO_ACTIVE_HIGH>; 201 + output-low; 202 + }; 203 + 204 + mic-can-sel-hog { 205 + gpio-hog; 206 + gpios = <17 GPIO_ACTIVE_HIGH>; 207 + output-low; 208 + }; 282 209 }; 283 210 284 211 pmic@25 { ··· 318 221 regulator-ramp-delay = <3125>; 319 222 }; 320 223 321 - buck4: BUCK4{ 224 + buck4: BUCK4 { 322 225 regulator-name = "BUCK4"; 323 226 regulator-min-microvolt = <600000>; 324 227 regulator-max-microvolt = <3400000>; ··· 326 229 regulator-always-on; 327 230 }; 328 231 329 - buck5: BUCK5{ 232 + buck5: BUCK5 { 330 233 regulator-name = "BUCK5"; 331 234 regulator-min-microvolt = <600000>; 332 235 regulator-max-microvolt = <3400000>; ··· 375 278 status = "okay"; 376 279 }; 377 280 281 + &micfil { 282 + pinctrl-names = "default"; 283 + pinctrl-0 = <&pinctrl_pdm>; 284 + assigned-clocks = <&clk IMX93_CLK_PDM>; 285 + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 286 + assigned-clock-rates = <49152000>; 287 + status = "okay"; 288 + }; 289 + 378 290 &mu1 { 379 291 status = "okay"; 380 292 }; 381 293 382 294 &mu2 { 295 + status = "okay"; 296 + }; 297 + 298 + &sai1 { 299 + pinctrl-names = "default"; 300 + pinctrl-0 = <&pinctrl_sai1>; 301 + assigned-clocks = <&clk IMX93_CLK_SAI1>; 302 + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 303 + assigned-clock-rates = <12288000>; 304 + fsl,sai-mclk-direction-output; 305 + status = "okay"; 306 + }; 307 + 308 + &sai3 { 309 + pinctrl-names = "default"; 310 + pinctrl-0 = <&pinctrl_sai3>; 311 + assigned-clocks = <&clk IMX93_CLK_SAI3>; 312 + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 313 + assigned-clock-rates = <12288000>; 314 + fsl,sai-mclk-direction-output; 315 + fsl,sai-synchronous-rx; 383 316 status = "okay"; 384 317 }; 385 318 ··· 497 370 >; 498 371 }; 499 372 373 + pinctrl_pdm: pdmgrp { 374 + fsl,pins = < 375 + MX93_PAD_PDM_CLK__PDM_CLK 0x31e 376 + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 377 + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 378 + >; 379 + }; 380 + 500 381 pinctrl_uart1: uart1grp { 501 382 fsl,pins = < 502 383 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e ··· 575 440 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 576 441 fsl,pins = < 577 442 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 443 + >; 444 + }; 445 + 446 + pinctrl_sai1: sai1grp { 447 + fsl,pins = < 448 + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 449 + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 450 + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 451 + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 452 + >; 453 + }; 454 + 455 + pinctrl_sai3: sai3grp { 456 + fsl,pins = < 457 + MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e 458 + MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e 459 + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 460 + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 461 + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 578 462 >; 579 463 }; 580 464
+8
arch/arm64/boot/dts/freescale/imx93.dtsi
··· 42 42 serial5 = &lpuart6; 43 43 serial6 = &lpuart7; 44 44 serial7 = &lpuart8; 45 + spi0 = &lpspi1; 46 + spi1 = &lpspi2; 47 + spi2 = &lpspi3; 48 + spi3 = &lpspi4; 49 + spi4 = &lpspi5; 50 + spi5 = &lpspi6; 51 + spi6 = &lpspi7; 52 + spi7 = &lpspi8; 45 53 }; 46 54 47 55 cpus {
+86
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
··· 8 8 #include <dt-bindings/pwm/pwm.h> 9 9 #include "imx95.dtsi" 10 10 11 + #define FALLING_EDGE 1 12 + #define RISING_EDGE 2 13 + 14 + #define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ 15 + #define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ 16 + #define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ 17 + #define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ 18 + #define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ 19 + 11 20 / { 12 21 model = "NXP i.MX95 19X19 board"; 13 22 compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 14 23 15 24 aliases { 25 + gpio0 = &gpio1; 26 + gpio1 = &gpio2; 27 + gpio2 = &gpio3; 28 + gpio3 = &gpio4; 29 + gpio4 = &gpio5; 30 + i2c0 = &lpi2c1; 31 + i2c1 = &lpi2c2; 32 + i2c2 = &lpi2c3; 33 + i2c3 = &lpi2c4; 34 + i2c4 = &lpi2c5; 35 + i2c5 = &lpi2c6; 36 + i2c6 = &lpi2c7; 37 + i2c7 = &lpi2c8; 16 38 mmc0 = &usdhc1; 17 39 mmc1 = &usdhc2; 18 40 serial0 = &lpuart1; ··· 254 232 }; 255 233 }; 256 234 235 + &lpi2c5 { 236 + clock-frequency = <100000>; 237 + pinctrl-names = "default"; 238 + pinctrl-0 = <&pinctrl_lpi2c5>; 239 + status = "okay"; 240 + 241 + i2c5_pcal6408: gpio@21 { 242 + compatible = "nxp,pcal6408"; 243 + reg = <0x21>; 244 + gpio-controller; 245 + #gpio-cells = <2>; 246 + vcc-supply = <&reg_3p3v>; 247 + }; 248 + }; 249 + 250 + &lpi2c6 { 251 + clock-frequency = <100000>; 252 + pinctrl-names = "default"; 253 + pinctrl-0 = <&pinctrl_lpi2c6>; 254 + status = "okay"; 255 + 256 + i2c6_pcal6416: gpio@21 { 257 + compatible = "nxp,pcal6416"; 258 + reg = <0x21>; 259 + gpio-controller; 260 + #gpio-cells = <2>; 261 + interrupt-controller; 262 + #interrupt-cells = <2>; 263 + interrupt-parent = <&gpio4>; 264 + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 265 + pinctrl-names = "default"; 266 + pinctrl-0 = <&pinctrl_pcal6416>; 267 + vcc-supply = <&reg_3p3v>; 268 + }; 269 + }; 270 + 257 271 &lpi2c7 { 258 272 clock-frequency = <1000000>; 259 273 pinctrl-names = "default"; ··· 415 357 status = "okay"; 416 358 }; 417 359 360 + &scmi_misc { 361 + nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE 362 + BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE 363 + BRD_SM_CTRL_BT_WAKE FALLING_EDGE 364 + BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE 365 + BRD_SM_CTRL_BUTTON FALLING_EDGE>; 366 + }; 367 + 418 368 &wdog3 { 419 369 fsl,ext-reset-output; 420 370 status = "okay"; ··· 476 410 >; 477 411 }; 478 412 413 + pinctrl_lpi2c5: lpi2c5grp { 414 + fsl,pins = < 415 + IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 416 + IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 417 + >; 418 + }; 419 + 420 + pinctrl_lpi2c6: lpi2c6grp { 421 + fsl,pins = < 422 + IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e 423 + IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e 424 + >; 425 + }; 426 + 479 427 pinctrl_lpi2c7: lpi2c7grp { 480 428 fsl,pins = < 481 429 IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e ··· 506 426 pinctrl_pcie1: pcie1grp { 507 427 fsl,pins = < 508 428 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 429 + >; 430 + }; 431 + 432 + pinctrl_pcal6416: pcal6416grp { 433 + fsl,pins = < 434 + IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e 509 435 >; 510 436 }; 511 437
+66 -2
arch/arm64/boot/dts/freescale/imx95.dtsi
··· 22 22 #address-cells = <1>; 23 23 #size-cells = <0>; 24 24 25 + idle-states { 26 + entry-method = "psci"; 27 + 28 + cpu_pd_wait: cpu-pd-wait { 29 + compatible = "arm,idle-state"; 30 + arm,psci-suspend-param = <0x0010033>; 31 + local-timer-stop; 32 + entry-latency-us = <10000>; 33 + exit-latency-us = <7000>; 34 + min-residency-us = <27000>; 35 + wakeup-latency-us = <15000>; 36 + }; 37 + }; 38 + 25 39 A55_0: cpu@0 { 26 40 device_type = "cpu"; 27 41 compatible = "arm,cortex-a55"; 28 42 reg = <0x0>; 29 43 enable-method = "psci"; 30 44 #cooling-cells = <2>; 45 + cpu-idle-states = <&cpu_pd_wait>; 31 46 power-domains = <&scmi_perf IMX95_PERF_A55>; 32 47 power-domain-names = "perf"; 33 48 i-cache-size = <32768>; ··· 60 45 reg = <0x100>; 61 46 enable-method = "psci"; 62 47 #cooling-cells = <2>; 48 + cpu-idle-states = <&cpu_pd_wait>; 63 49 power-domains = <&scmi_perf IMX95_PERF_A55>; 64 50 power-domain-names = "perf"; 65 51 i-cache-size = <32768>; ··· 78 62 reg = <0x200>; 79 63 enable-method = "psci"; 80 64 #cooling-cells = <2>; 65 + cpu-idle-states = <&cpu_pd_wait>; 81 66 power-domains = <&scmi_perf IMX95_PERF_A55>; 82 67 power-domain-names = "perf"; 83 68 i-cache-size = <32768>; ··· 96 79 reg = <0x300>; 97 80 enable-method = "psci"; 98 81 #cooling-cells = <2>; 82 + cpu-idle-states = <&cpu_pd_wait>; 99 83 power-domains = <&scmi_perf IMX95_PERF_A55>; 100 84 power-domain-names = "perf"; 101 85 i-cache-size = <32768>; ··· 116 98 power-domain-names = "perf"; 117 99 enable-method = "psci"; 118 100 #cooling-cells = <2>; 101 + cpu-idle-states = <&cpu_pd_wait>; 119 102 i-cache-size = <32768>; 120 103 i-cache-line-size = <64>; 121 104 i-cache-sets = <128>; ··· 134 115 power-domain-names = "perf"; 135 116 enable-method = "psci"; 136 117 #cooling-cells = <2>; 118 + cpu-idle-states = <&cpu_pd_wait>; 137 119 i-cache-size = <32768>; 138 120 i-cache-line-size = <64>; 139 121 i-cache-sets = <128>; ··· 313 293 shmem = <&scmi_buf0>, <&scmi_buf1>; 314 294 #address-cells = <1>; 315 295 #size-cells = <0>; 296 + arm,max-rx-timeout-ms = <5000>; 316 297 317 298 scmi_devpd: protocol@11 { 318 299 reg = <0x11>; 319 300 #power-domain-cells = <1>; 301 + }; 302 + 303 + scmi_sys_power: protocol@12 { 304 + reg = <0x12>; 320 305 }; 321 306 322 307 scmi_perf: protocol@13 { ··· 343 318 reg = <0x19>; 344 319 }; 345 320 321 + scmi_bbm: protocol@81 { 322 + reg = <0x81>; 323 + }; 324 + 325 + scmi_misc: protocol@84 { 326 + reg = <0x84>; 327 + }; 346 328 }; 347 329 }; 348 330 ··· 366 334 367 335 trips { 368 336 cpu_alert0: trip0 { 369 - temperature = <85000>; 337 + temperature = <105000>; 370 338 hysteresis = <2000>; 371 339 type = "passive"; 372 340 }; 373 341 374 342 cpu_crit0: trip1 { 375 - temperature = <95000>; 343 + temperature = <125000>; 376 344 hysteresis = <2000>; 377 345 type = "critical"; 378 346 }; ··· 381 349 cooling-maps { 382 350 map0 { 383 351 trip = <&cpu_alert0>; 352 + cooling-device = 353 + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 354 + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 355 + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 356 + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 357 + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 358 + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 359 + }; 360 + }; 361 + }; 362 + 363 + ana-thermal { 364 + polling-delay-passive = <250>; 365 + polling-delay = <2000>; 366 + thermal-sensors = <&scmi_sensor 0>; 367 + trips { 368 + ana_alert: trip0 { 369 + temperature = <105000>; 370 + hysteresis = <2000>; 371 + type = "passive"; 372 + }; 373 + 374 + ana_crit0: trip1 { 375 + temperature = <125000>; 376 + hysteresis = <2000>; 377 + type = "critical"; 378 + }; 379 + }; 380 + 381 + cooling-maps { 382 + map0 { 383 + trip = <&ana_alert>; 384 384 cooling-device = 385 385 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386 386 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-6
arch/arm64/boot/dts/freescale/mba8mx.dtsi
··· 100 100 101 101 port { 102 102 panel_in_lvds: endpoint { 103 - data-lanes = <1 2 3 4>; 104 103 remote-endpoint = <&lvds_bridge_out>; 105 104 }; 106 105 }; ··· 315 316 }; 316 317 }; 317 318 }; 318 - }; 319 - 320 - &mipi_dsi { 321 - samsung,burst-clock-frequency = <891000000>; 322 - samsung,esc-clock-frequency = <20000000>; 323 319 }; 324 320 325 321 &mipi_dsi_out {
+153
arch/arm64/boot/dts/freescale/s32g2.dtsi
··· 162 162 slew-rate = <166>; 163 163 }; 164 164 }; 165 + 166 + pinctrl_usdhc0: usdhc0grp-pins { 167 + usdhc0-grp0 { 168 + pinmux = <0x2e1>, 169 + <0x381>; 170 + output-enable; 171 + bias-pull-down; 172 + slew-rate = <150>; 173 + }; 174 + 175 + usdhc0-grp1 { 176 + pinmux = <0x2f1>, 177 + <0x301>, 178 + <0x311>, 179 + <0x321>, 180 + <0x331>, 181 + <0x341>, 182 + <0x351>, 183 + <0x361>, 184 + <0x371>; 185 + output-enable; 186 + input-enable; 187 + bias-pull-up; 188 + slew-rate = <150>; 189 + }; 190 + 191 + usdhc0-grp2 { 192 + pinmux = <0x391>; 193 + output-enable; 194 + slew-rate = <150>; 195 + }; 196 + 197 + usdhc0-grp3 { 198 + pinmux = <0x3a0>; 199 + input-enable; 200 + slew-rate = <150>; 201 + }; 202 + 203 + usdhc0-grp4 { 204 + pinmux = <0x2032>, 205 + <0x2042>, 206 + <0x2052>, 207 + <0x2062>, 208 + <0x2072>, 209 + <0x2082>, 210 + <0x2092>, 211 + <0x20a2>, 212 + <0x20b2>, 213 + <0x20c2>; 214 + }; 215 + }; 216 + 217 + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 218 + usdhc0-100mhz-grp0 { 219 + pinmux = <0x2e1>, 220 + <0x381>; 221 + output-enable; 222 + bias-pull-down; 223 + slew-rate = <150>; 224 + }; 225 + 226 + usdhc0-100mhz-grp1 { 227 + pinmux = <0x2f1>, 228 + <0x301>, 229 + <0x311>, 230 + <0x321>, 231 + <0x331>, 232 + <0x341>, 233 + <0x351>, 234 + <0x361>, 235 + <0x371>; 236 + output-enable; 237 + input-enable; 238 + bias-pull-up; 239 + slew-rate = <150>; 240 + }; 241 + 242 + usdhc0-100mhz-grp2 { 243 + pinmux = <0x391>; 244 + output-enable; 245 + slew-rate = <150>; 246 + }; 247 + 248 + usdhc0-100mhz-grp3 { 249 + pinmux = <0x3a0>; 250 + input-enable; 251 + slew-rate = <150>; 252 + }; 253 + 254 + usdhc0-100mhz-grp4 { 255 + pinmux = <0x2032>, 256 + <0x2042>, 257 + <0x2052>, 258 + <0x2062>, 259 + <0x2072>, 260 + <0x2082>, 261 + <0x2092>, 262 + <0x20a2>, 263 + <0x20b2>, 264 + <0x20c2>; 265 + }; 266 + }; 267 + 268 + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 269 + usdhc0-200mhz-grp0 { 270 + pinmux = <0x2e1>, 271 + <0x381>; 272 + output-enable; 273 + bias-pull-down; 274 + slew-rate = <208>; 275 + }; 276 + 277 + usdhc0-200mhz-grp1 { 278 + pinmux = <0x2f1>, 279 + <0x301>, 280 + <0x311>, 281 + <0x321>, 282 + <0x331>, 283 + <0x341>, 284 + <0x351>, 285 + <0x361>, 286 + <0x371>; 287 + output-enable; 288 + input-enable; 289 + bias-pull-up; 290 + slew-rate = <208>; 291 + }; 292 + 293 + usdhc0-200mhz-grp2 { 294 + pinmux = <0x391>; 295 + output-enable; 296 + slew-rate = <208>; 297 + }; 298 + 299 + usdhc0-200mhz-grp3 { 300 + pinmux = <0x3a0>; 301 + input-enable; 302 + slew-rate = <208>; 303 + }; 304 + 305 + usdhc0-200mhz-grp4 { 306 + pinmux = <0x2032>, 307 + <0x2042>, 308 + <0x2052>, 309 + <0x2062>, 310 + <0x2072>, 311 + <0x2082>, 312 + <0x2092>, 313 + <0x20a2>, 314 + <0x20b2>, 315 + <0x20c2>; 316 + }; 317 + }; 165 318 }; 166 319 167 320 uart0: serial@401c8000 {
+5
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
··· 34 34 }; 35 35 36 36 &usdhc0 { 37 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 38 + pinctrl-0 = <&pinctrl_usdhc0>; 39 + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; 40 + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; 37 41 disable-wp; 42 + no-1-8-v; 38 43 status = "okay"; 39 44 };
+13
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
··· 40 40 }; 41 41 42 42 &usdhc0 { 43 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 44 + pinctrl-0 = <&pinctrl_usdhc0>; 45 + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; 46 + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; 43 47 disable-wp; 48 + /* Remove no-1-8-v to enable higher speed modes for SD card. 49 + * However, this is not enough to enable HS400 or HS200 modes for eMMC. 50 + * In this case, the position of the resistor R797 must be changed 51 + * from A to B before removing the property. 52 + * If the property is removed without changing the resistor position, 53 + * HS*00 may be enabled, but the interface might be unstable because of 54 + * the wrong VCCQ voltage applied to the eMMC. 55 + */ 56 + no-1-8-v; 44 57 status = "okay"; 45 58 };
+153
arch/arm64/boot/dts/freescale/s32g3.dtsi
··· 219 219 slew-rate = <166>; 220 220 }; 221 221 }; 222 + 223 + pinctrl_usdhc0: usdhc0grp-pins { 224 + usdhc0-grp0 { 225 + pinmux = <0x2e1>, 226 + <0x381>; 227 + output-enable; 228 + bias-pull-down; 229 + slew-rate = <150>; 230 + }; 231 + 232 + usdhc0-grp1 { 233 + pinmux = <0x2f1>, 234 + <0x301>, 235 + <0x311>, 236 + <0x321>, 237 + <0x331>, 238 + <0x341>, 239 + <0x351>, 240 + <0x361>, 241 + <0x371>; 242 + output-enable; 243 + input-enable; 244 + bias-pull-up; 245 + slew-rate = <150>; 246 + }; 247 + 248 + usdhc0-grp2 { 249 + pinmux = <0x391>; 250 + output-enable; 251 + slew-rate = <150>; 252 + }; 253 + 254 + usdhc0-grp3 { 255 + pinmux = <0x3a0>; 256 + input-enable; 257 + slew-rate = <150>; 258 + }; 259 + 260 + usdhc0-grp4 { 261 + pinmux = <0x2032>, 262 + <0x2042>, 263 + <0x2052>, 264 + <0x2062>, 265 + <0x2072>, 266 + <0x2082>, 267 + <0x2092>, 268 + <0x20a2>, 269 + <0x20b2>, 270 + <0x20c2>; 271 + }; 272 + }; 273 + 274 + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { 275 + usdhc0-100mhz-grp0 { 276 + pinmux = <0x2e1>, 277 + <0x381>; 278 + output-enable; 279 + bias-pull-down; 280 + slew-rate = <150>; 281 + }; 282 + 283 + usdhc0-100mhz-grp1 { 284 + pinmux = <0x2f1>, 285 + <0x301>, 286 + <0x311>, 287 + <0x321>, 288 + <0x331>, 289 + <0x341>, 290 + <0x351>, 291 + <0x361>, 292 + <0x371>; 293 + output-enable; 294 + input-enable; 295 + bias-pull-up; 296 + slew-rate = <150>; 297 + }; 298 + 299 + usdhc0-100mhz-grp2 { 300 + pinmux = <0x391>; 301 + output-enable; 302 + slew-rate = <150>; 303 + }; 304 + 305 + usdhc0-100mhz-grp3 { 306 + pinmux = <0x3a0>; 307 + input-enable; 308 + slew-rate = <150>; 309 + }; 310 + 311 + usdhc0-100mhz-grp4 { 312 + pinmux = <0x2032>, 313 + <0x2042>, 314 + <0x2052>, 315 + <0x2062>, 316 + <0x2072>, 317 + <0x2082>, 318 + <0x2092>, 319 + <0x20a2>, 320 + <0x20b2>, 321 + <0x20c2>; 322 + }; 323 + }; 324 + 325 + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { 326 + usdhc0-200mhz-grp0 { 327 + pinmux = <0x2e1>, 328 + <0x381>; 329 + output-enable; 330 + bias-pull-down; 331 + slew-rate = <208>; 332 + }; 333 + 334 + usdhc0-200mhz-grp1 { 335 + pinmux = <0x2f1>, 336 + <0x301>, 337 + <0x311>, 338 + <0x321>, 339 + <0x331>, 340 + <0x341>, 341 + <0x351>, 342 + <0x361>, 343 + <0x371>; 344 + output-enable; 345 + input-enable; 346 + bias-pull-up; 347 + slew-rate = <208>; 348 + }; 349 + 350 + usdhc0-200mhz-grp2 { 351 + pinmux = <0x391>; 352 + output-enable; 353 + slew-rate = <208>; 354 + }; 355 + 356 + usdhc0-200mhz-grp3 { 357 + pinmux = <0x3a0>; 358 + input-enable; 359 + slew-rate = <208>; 360 + }; 361 + 362 + usdhc0-200mhz-grp4 { 363 + pinmux = <0x2032>, 364 + <0x2042>, 365 + <0x2052>, 366 + <0x2062>, 367 + <0x2072>, 368 + <0x2082>, 369 + <0x2092>, 370 + <0x20a2>, 371 + <0x20b2>, 372 + <0x20c2>; 373 + }; 374 + }; 222 375 }; 223 376 224 377 uart0: serial@401c8000 {
+4
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
··· 40 40 }; 41 41 42 42 &usdhc0 { 43 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 44 + pinctrl-0 = <&pinctrl_usdhc0>; 45 + pinctrl-1 = <&pinctrl_usdhc0_100mhz>; 46 + pinctrl-2 = <&pinctrl_usdhc0_200mhz>; 43 47 bus-width = <8>; 44 48 disable-wp; 45 49 status = "okay";