Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: move LPT clock gating init into intel_pch
Move the LPT PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding
Haswell/Broadwell callers to the display-specific code.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-4-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
+21
-19
+19
drivers/gpu/drm/i915/display/intel_pch.c
+19
drivers/gpu/drm/i915/display/intel_pch.c
···
264
264
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
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}
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+
static void intel_pch_lpt_init_clock_gating(struct intel_display *display)
268
+
{
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+
/*
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+
* TODO: this bit should only be enabled when really needed, then
271
+
* disabled when not needed anymore in order to save power.
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+
*/
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+
if (HAS_PCH_LPT_LP(display))
274
+
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
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+
PCH_LP_PARTITION_LEVEL_DISABLE);
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+
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+
/* WADPOClockGatingDisable:hsw */
278
+
intel_de_rmw(display, TRANS_CHICKEN1(PIPE_A), 0,
279
+
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
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+
}
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+
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void intel_pch_init_clock_gating(struct intel_display *display)
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{
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switch (INTEL_PCH_TYPE(display)) {
···
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break;
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case PCH_CPT:
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intel_pch_cpt_init_clock_gating(display);
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+
break;
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+
case PCH_LPT_H:
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+
case PCH_LPT_LP:
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+
intel_pch_lpt_init_clock_gating(display);
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break;
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default:
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break;
+2
-19
drivers/gpu/drm/i915/intel_clock_gating.c
+2
-19
drivers/gpu/drm/i915/intel_clock_gating.c
···
266
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gen6_check_mch_setup(i915);
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}
268
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269
-
static void lpt_init_clock_gating(struct drm_i915_private *i915)
270
-
{
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-
struct intel_display *display = i915->display;
272
-
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-
/*
274
-
* TODO: this bit should only be enabled when really needed, then
275
-
* disabled when not needed anymore in order to save power.
276
-
*/
277
-
if (HAS_PCH_LPT_LP(display))
278
-
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
279
-
0, PCH_LP_PARTITION_LEVEL_DISABLE);
280
-
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-
/* WADPOClockGatingDisable:hsw */
282
-
intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
283
-
0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
284
-
}
285
-
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269
static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
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int general_prio_credits,
288
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int high_prio_credits)
···
405
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intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
406
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0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
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408
-
lpt_init_clock_gating(i915);
425
+
intel_pch_init_clock_gating(i915->display);
409
426
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/* WaDisableDopClockGating:bdw
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*
···
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/* WaSwitchSolVfFArbitrationPriority:hsw */
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intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
441
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-
lpt_init_clock_gating(i915);
459
+
intel_pch_init_clock_gating(i915->display);
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}
444
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static void ivb_init_clock_gating(struct drm_i915_private *i915)