Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: move CPT clock gating init into intel_pch
Move the CPT PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding IVB callers
to the display-specific code.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-3-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
+42
-37
+40
drivers/gpu/drm/i915/display/intel_pch.c
+40
drivers/gpu/drm/i915/display/intel_pch.c
···
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6
#include <drm/drm_print.h>
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#include "intel_de.h"
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+
#include "intel_display.h"
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#include "intel_display_regs.h"
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#include "intel_display_core.h"
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#include "intel_display_utils.h"
···
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PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
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}
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static void intel_pch_cpt_init_clock_gating(struct intel_display *display)
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{
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enum pipe pipe;
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u32 val;
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+
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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intel_de_write(display, SOUTH_DSPCLK_GATE_D,
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PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
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PCH_DPLUNIT_CLOCK_GATE_DISABLE |
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PCH_CPUNIT_CLOCK_GATE_DISABLE);
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intel_de_rmw(display, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
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+
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/* The below fixes the weird display corruption, a few pixels shifted
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* downward, on (only) LVDS of some HP laptops with IVY.
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*/
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for_each_pipe(display, pipe) {
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val = intel_de_read(display, TRANS_CHICKEN2(pipe));
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val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
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val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
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if (display->vbt.fdi_rx_polarity_inverted)
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val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
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val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
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val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
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intel_de_write(display, TRANS_CHICKEN2(pipe), val);
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}
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+
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/* WADP0ClockGatingDisable */
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for_each_pipe(display, pipe)
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intel_de_write(display, TRANS_CHICKEN1(pipe),
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TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
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}
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+
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void intel_pch_init_clock_gating(struct intel_display *display)
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{
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switch (INTEL_PCH_TYPE(display)) {
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case PCH_IBX:
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intel_pch_ibx_init_clock_gating(display);
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break;
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case PCH_CPT:
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intel_pch_cpt_init_clock_gating(display);
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break;
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default:
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break;
+2
-37
drivers/gpu/drm/i915/intel_clock_gating.c
+2
-37
drivers/gpu/drm/i915/intel_clock_gating.c
···
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intel_pch_init_clock_gating(i915->display);
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}
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-
static void cpt_init_clock_gating(struct drm_i915_private *i915)
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{
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struct intel_display *display = i915->display;
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enum pipe pipe;
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u32 val;
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-
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/*
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* On Ibex Peak and Cougar Point, we need to disable clock
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-
* gating for the panel power sequencer or it will fail to
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* start up when no ports are active.
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*/
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intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
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PCH_DPLUNIT_CLOCK_GATE_DISABLE |
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PCH_CPUNIT_CLOCK_GATE_DISABLE);
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intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
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/* The below fixes the weird display corruption, a few pixels shifted
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* downward, on (only) LVDS of some HP laptops with IVY.
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-
*/
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for_each_pipe(display, pipe) {
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val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
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val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
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val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
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if (display->vbt.fdi_rx_polarity_inverted)
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val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
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val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
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val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
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intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
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}
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/* WADP0ClockGatingDisable */
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for_each_pipe(display, pipe) {
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intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
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TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
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-
}
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}
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-
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static void gen6_check_mch_setup(struct drm_i915_private *i915)
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{
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u32 tmp;
···
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g4x_disable_trickle_feed(i915);
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-
cpt_init_clock_gating(i915);
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intel_pch_init_clock_gating(i915->display);
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gen6_check_mch_setup(i915);
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}
···
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GEN6_MBC_SNPCR_MED);
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if (!HAS_PCH_NOP(display))
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cpt_init_clock_gating(i915);
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intel_pch_init_clock_gating(display);
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541
gen6_check_mch_setup(i915);
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}