Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Update vm start, end, hole to support 57bit address
Change gmc macro AMDGPU_GMC_HOLE_START/END/MASK to 57bit if vm root
level is PDB3 for 5-level page tables.
The macro access adev without passing adev as parameter is to minimize
the code change to support 57bit, then we have to add adev variable in
several places to use the macro.
Because adev definition is not available in all amdgpu c files which
include amdgpu_gmc.h, change inline function amdgpu_gmc_sign_extend to
macro.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Philip Yang
and committed by
Alex Deucher
cf856ca9
f6b1c1f5
+33
-25
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+9
-11
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+9
-11
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
···
32
32
#include "amdgpu_xgmi.h"
33
33
#include "amdgpu_ras.h"
34
34
35
-
/* VA hole for 48bit addresses on Vega10 */
36
-
#define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
37
-
#define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
35
+
/* VA hole for 48bit and 57bit addresses */
36
+
#define AMDGPU_GMC_HOLE_START (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\
37
+
0x0100000000000000ULL : 0x0000800000000000ULL)
38
+
#define AMDGPU_GMC_HOLE_END (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\
39
+
0xff00000000000000ULL : 0xffff800000000000ULL)
38
40
39
41
/*
40
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* Hardware is programmed as if the hole doesn't exists with start and end
···
45
43
* This mask is used to remove the upper 16bits of the VA and so come up with
46
44
* the linear addr value.
47
45
*/
48
-
#define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
46
+
#define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\
47
+
0x00ffffffffffffffULL : 0x0000ffffffffffffULL)
49
48
50
49
/*
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50
* Ring size as power of two for the log of recent faults.
···
397
394
*
398
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* @addr: address to extend
399
396
*/
400
-
static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
401
-
{
402
-
if (addr >= AMDGPU_GMC_HOLE_START)
403
-
addr |= AMDGPU_GMC_HOLE_END;
404
-
405
-
return addr;
406
-
}
397
+
#define amdgpu_gmc_sign_extend(addr) ((addr) >= AMDGPU_GMC_HOLE_START ?\
398
+
((addr) | AMDGPU_GMC_HOLE_END) : (addr))
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bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev);
409
401
int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev);
+5
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+5
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
···
166
166
return 0;
167
167
}
168
168
169
-
int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue,
169
+
int amdgpu_userq_input_va_validate(struct amdgpu_device *adev,
170
+
struct amdgpu_usermode_queue *queue,
170
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u64 addr, u64 expected_size)
171
172
{
172
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struct amdgpu_bo_va_mapping *va_map;
···
731
730
db_info.doorbell_offset = args->in.doorbell_offset;
732
731
733
732
/* Validate the userq virtual address.*/
734
-
if (amdgpu_userq_input_va_validate(queue, args->in.queue_va, args->in.queue_size) ||
735
-
amdgpu_userq_input_va_validate(queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) ||
736
-
amdgpu_userq_input_va_validate(queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) {
733
+
if (amdgpu_userq_input_va_validate(adev, queue, args->in.queue_va, args->in.queue_size) ||
734
+
amdgpu_userq_input_va_validate(adev, queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) ||
735
+
amdgpu_userq_input_va_validate(adev, queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) {
737
736
r = -EINVAL;
738
737
kfree(queue);
739
738
goto unlock;
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
···
153
153
void amdgpu_userq_pre_reset(struct amdgpu_device *adev);
154
154
int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost);
155
155
156
-
int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue,
156
+
int amdgpu_userq_input_va_validate(struct amdgpu_device *adev,
157
+
struct amdgpu_usermode_queue *queue,
157
158
u64 addr, u64 expected_size);
158
159
int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev,
159
160
struct amdgpu_bo_va_mapping *mapping,
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
···
352
352
/**
353
353
* amdgpu_userq_fence_read_wptr - Read the userq wptr value
354
354
*
355
+
* @adev: amdgpu_device pointer
355
356
* @queue: user mode queue structure pointer
356
357
* @wptr: write pointer value
357
358
*
···
362
361
*
363
362
* Returns wptr value on success, error on failure.
364
363
*/
365
-
static int amdgpu_userq_fence_read_wptr(struct amdgpu_usermode_queue *queue,
364
+
static int amdgpu_userq_fence_read_wptr(struct amdgpu_device *adev,
365
+
struct amdgpu_usermode_queue *queue,
366
366
u64 *wptr)
367
367
{
368
368
struct amdgpu_bo_va_mapping *mapping;
···
457
455
int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
458
456
struct drm_file *filp)
459
457
{
458
+
struct amdgpu_device *adev = drm_to_adev(dev);
460
459
struct amdgpu_fpriv *fpriv = filp->driver_priv;
461
460
struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr;
462
461
struct drm_amdgpu_userq_signal *args = data;
···
548
545
goto put_gobj_write;
549
546
}
550
547
551
-
r = amdgpu_userq_fence_read_wptr(queue, &wptr);
548
+
r = amdgpu_userq_fence_read_wptr(adev, queue, &wptr);
552
549
if (r)
553
550
goto put_gobj_write;
554
551
+1
-1
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
···
827
827
* Set the internal MC address mask This is the max address of the GPU's
828
828
* internal address space.
829
829
*/
830
-
adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
830
+
adev->gmc.mc_mask = AMDGPU_GMC_HOLE_MASK;
831
831
832
832
r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
833
833
if (r) {
+7
-6
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
+7
-6
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
···
59
59
}
60
60
61
61
static int
62
-
mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
62
+
mes_userq_create_wptr_mapping(struct amdgpu_device *adev,
63
+
struct amdgpu_userq_mgr *uq_mgr,
63
64
struct amdgpu_usermode_queue *queue,
64
65
uint64_t wptr)
65
66
{
···
301
300
goto free_mqd;
302
301
}
303
302
304
-
r = amdgpu_userq_input_va_validate(queue, compute_mqd->eop_va,
303
+
r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va,
305
304
2048);
306
305
if (r)
307
306
goto free_mqd;
···
342
341
userq_props->tmz_queue =
343
342
mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE;
344
343
345
-
r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->shadow_va,
344
+
r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va,
346
345
shadow_info.shadow_size);
347
346
if (r)
348
347
goto free_mqd;
349
-
r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->csa_va,
348
+
r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va,
350
349
shadow_info.csa_size);
351
350
if (r)
352
351
goto free_mqd;
···
367
366
r = -ENOMEM;
368
367
goto free_mqd;
369
368
}
370
-
r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11->csa_va,
369
+
r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va,
371
370
32);
372
371
if (r)
373
372
goto free_mqd;
···
392
391
}
393
392
394
393
/* FW expects WPTR BOs to be mapped into GART */
395
-
r = mes_userq_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr);
394
+
r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr);
396
395
if (r) {
397
396
DRM_ERROR("Failed to create WPTR mapping\n");
398
397
goto free_ctx;
+1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
···
2053
2053
{
2054
2054
struct ttm_operation_ctx ctx = { false, false };
2055
2055
struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
2056
+
struct amdgpu_device *adev = parser->adev;
2056
2057
struct amdgpu_vm *vm = &fpriv->vm;
2057
2058
struct amdgpu_bo_va_mapping *mapping;
2058
2059
struct amdgpu_bo *bo;
+1
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+1
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c