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drm/msm/a6xx: Use barriers while updating HFI Q headers

To avoid harmful compiler optimizations and IO reordering in the HW, use
barriers and READ/WRITE_ONCE helpers as necessary while accessing the HFI
queue index variables.

Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714653/
Message-ID: <20260327-a8xx-gpu-batch2-v2-1-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark dc78b35d 47cbfe26

+10 -4
+10 -4
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
··· 34 34 struct a6xx_hfi_queue_header *header = queue->header; 35 35 u32 i, hdr, index = header->read_index; 36 36 37 - if (header->read_index == header->write_index) { 37 + if (header->read_index == READ_ONCE(header->write_index)) { 38 38 header->rx_request = 1; 39 39 return 0; 40 40 } ··· 62 62 if (!gmu->legacy) 63 63 index = ALIGN(index, 4) % header->size; 64 64 65 - header->read_index = index; 65 + /* Ensure all memory operations are complete before updating the read index */ 66 + dma_mb(); 67 + 68 + WRITE_ONCE(header->read_index, index); 66 69 return HFI_HEADER_SIZE(hdr); 67 70 } 68 71 ··· 77 74 78 75 spin_lock(&queue->lock); 79 76 80 - space = CIRC_SPACE(header->write_index, header->read_index, 77 + space = CIRC_SPACE(header->write_index, READ_ONCE(header->read_index), 81 78 header->size); 82 79 if (space < dwords) { 83 80 header->dropped++; ··· 98 95 queue->data[index] = 0xfafafafa; 99 96 } 100 97 101 - header->write_index = index; 98 + /* Ensure all memory operations are complete before updating the write index */ 99 + dma_mb(); 100 + 101 + WRITE_ONCE(header->write_index, index); 102 102 spin_unlock(&queue->lock); 103 103 104 104 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);