Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-qmp-pcie: add support for sc8280xp
Add support for the single and dual-lane PHYs found on SC8280XP.
Note that the SC8280XP binding does not try to describe every register
subregion and instead the driver holds the corresponding offsets.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-16-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Johan Hovold
and committed by
Vinod Koul
d0a846ba
9e420f1e
+291
-10
+289
-10
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+289
-10
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
834
834
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
835
835
};
836
836
837
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
838
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
839
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
840
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
841
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
842
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
843
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
844
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
845
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
846
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
847
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
848
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
849
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
850
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
851
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
852
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
853
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
854
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
855
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
856
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
857
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
858
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
859
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
860
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
861
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
862
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
863
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
864
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
865
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
866
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
867
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
868
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
869
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
870
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
871
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
872
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
873
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
874
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
875
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
876
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
877
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
878
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
879
+
};
880
+
881
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
882
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
883
+
};
884
+
885
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
886
+
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
887
+
};
888
+
889
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
890
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
891
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
892
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
893
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
894
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
895
+
};
896
+
897
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
898
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
899
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
900
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
901
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
902
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
903
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
904
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
905
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
906
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
907
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
908
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
909
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
910
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
911
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
912
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
913
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
914
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
915
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
916
+
};
917
+
918
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
919
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
920
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
921
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
922
+
};
923
+
924
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
925
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
926
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
927
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
928
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
929
+
};
930
+
931
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
932
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
933
+
QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
934
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
935
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
936
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
937
+
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
938
+
};
939
+
940
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
941
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
942
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
943
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
944
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
945
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
946
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
947
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
948
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
949
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
950
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
951
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
952
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
953
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
954
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
955
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
956
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
957
+
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
958
+
};
959
+
960
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
961
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
962
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
963
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
964
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
965
+
};
966
+
967
+
static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
968
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
969
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
970
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
971
+
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
972
+
};
973
+
837
974
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
838
975
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
839
976
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
···
1450
1313
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1451
1314
};
1452
1315
1316
+
struct qmp_pcie_offsets {
1317
+
u16 serdes;
1318
+
u16 pcs;
1319
+
u16 pcs_misc;
1320
+
u16 tx;
1321
+
u16 rx;
1322
+
u16 tx2;
1323
+
u16 rx2;
1324
+
};
1325
+
1453
1326
struct qmp_phy_cfg_tbls {
1454
1327
const struct qmp_phy_init_tbl *serdes;
1455
1328
int serdes_num;
···
1476
1329
/* struct qmp_phy_cfg - per-PHY initialization config */
1477
1330
struct qmp_phy_cfg {
1478
1331
int lanes;
1332
+
1333
+
const struct qmp_pcie_offsets *offsets;
1479
1334
1480
1335
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1481
1336
const struct qmp_phy_cfg_tbls tbls;
···
1571
1422
"aux", "cfg_ahb", "ref",
1572
1423
};
1573
1424
1425
+
static const char * const sc8280xp_pciephy_clk_l[] = {
1426
+
"aux", "cfg_ahb", "ref", "rchng",
1427
+
};
1574
1428
1575
1429
static const char * const sdm845_pciephy_clk_l[] = {
1576
1430
"aux", "cfg_ahb", "ref", "refgen",
···
1591
1439
1592
1440
static const char * const sdm845_pciephy_reset_l[] = {
1593
1441
"phy",
1442
+
};
1443
+
1444
+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
1445
+
.serdes = 0,
1446
+
.pcs = 0x0200,
1447
+
.pcs_misc = 0x0600,
1448
+
.tx = 0x0e00,
1449
+
.rx = 0x1000,
1450
+
.tx2 = 0x1600,
1451
+
.rx2 = 0x1800,
1594
1452
};
1595
1453
1596
1454
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
···
1852
1690
},
1853
1691
.clk_list = sdm845_pciephy_clk_l,
1854
1692
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1693
+
.reset_list = sdm845_pciephy_reset_l,
1694
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1695
+
.vreg_list = qmp_phy_vreg_l,
1696
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1697
+
.regs = sm8250_pcie_regs_layout,
1698
+
1699
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1700
+
.phy_status = PHYSTATUS,
1701
+
};
1702
+
1703
+
static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
1704
+
.lanes = 1,
1705
+
1706
+
.offsets = &qmp_pcie_offsets_v5,
1707
+
1708
+
.tbls = {
1709
+
.serdes = sc8280xp_qmp_pcie_serdes_tbl,
1710
+
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
1711
+
.tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
1712
+
.tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
1713
+
.rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
1714
+
.rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
1715
+
.pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
1716
+
.pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
1717
+
.pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
1718
+
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
1719
+
},
1720
+
1721
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
1722
+
.serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
1723
+
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
1724
+
},
1725
+
1726
+
.clk_list = sc8280xp_pciephy_clk_l,
1727
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
1728
+
.reset_list = sdm845_pciephy_reset_l,
1729
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1730
+
.vreg_list = qmp_phy_vreg_l,
1731
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1732
+
.regs = sm8250_pcie_regs_layout,
1733
+
1734
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1735
+
.phy_status = PHYSTATUS,
1736
+
};
1737
+
1738
+
static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
1739
+
.lanes = 2,
1740
+
1741
+
.offsets = &qmp_pcie_offsets_v5,
1742
+
1743
+
.tbls = {
1744
+
.serdes = sc8280xp_qmp_pcie_serdes_tbl,
1745
+
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
1746
+
.tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
1747
+
.tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
1748
+
.rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
1749
+
.rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
1750
+
.pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
1751
+
.pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
1752
+
.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
1753
+
.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
1754
+
},
1755
+
1756
+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
1757
+
.serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
1758
+
.serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
1759
+
},
1760
+
1761
+
.clk_list = sc8280xp_pciephy_clk_l,
1762
+
.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
1855
1763
.reset_list = sdm845_pciephy_reset_l,
1856
1764
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1857
1765
.vreg_list = qmp_phy_vreg_l,
···
2452
2220
return 0;
2453
2221
}
2454
2222
2223
+
static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
2224
+
{
2225
+
struct platform_device *pdev = to_platform_device(qmp->dev);
2226
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
2227
+
const struct qmp_pcie_offsets *offs = cfg->offsets;
2228
+
struct device *dev = qmp->dev;
2229
+
void __iomem *base;
2230
+
int ret;
2231
+
2232
+
if (!offs)
2233
+
return -EINVAL;
2234
+
2235
+
base = devm_platform_ioremap_resource(pdev, 0);
2236
+
if (IS_ERR(base))
2237
+
return PTR_ERR(base);
2238
+
2239
+
qmp->serdes = base + offs->serdes;
2240
+
qmp->pcs = base + offs->pcs;
2241
+
qmp->pcs_misc = base + offs->pcs_misc;
2242
+
qmp->tx = base + offs->tx;
2243
+
qmp->rx = base + offs->rx;
2244
+
2245
+
if (cfg->lanes >= 2) {
2246
+
qmp->tx2 = base + offs->tx2;
2247
+
qmp->rx2 = base + offs->rx2;
2248
+
}
2249
+
2250
+
qmp->num_pipe_clks = 2;
2251
+
qmp->pipe_clks[0].id = "pipe";
2252
+
qmp->pipe_clks[1].id = "pipediv2";
2253
+
2254
+
ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
2255
+
if (ret)
2256
+
return ret;
2257
+
2258
+
return 0;
2259
+
}
2260
+
2455
2261
static int qmp_pcie_probe(struct platform_device *pdev)
2456
2262
{
2457
2263
struct device *dev = &pdev->dev;
2458
-
struct device_node *child;
2459
2264
struct phy_provider *phy_provider;
2265
+
struct device_node *np;
2460
2266
struct qmp_pcie *qmp;
2461
2267
int ret;
2462
2268
···
2523
2253
if (ret)
2524
2254
return ret;
2525
2255
2526
-
child = of_get_next_available_child(dev->of_node, NULL);
2527
-
if (!child)
2528
-
return -EINVAL;
2529
-
2530
-
ret = qmp_pcie_parse_dt_legacy(qmp, child);
2256
+
/* Check for legacy binding with child node. */
2257
+
np = of_get_next_available_child(dev->of_node, NULL);
2258
+
if (np) {
2259
+
ret = qmp_pcie_parse_dt_legacy(qmp, np);
2260
+
} else {
2261
+
np = of_node_get(dev->of_node);
2262
+
ret = qmp_pcie_parse_dt(qmp);
2263
+
}
2531
2264
if (ret)
2532
2265
goto err_node_put;
2533
2266
2534
-
ret = phy_pipe_clk_register(qmp, child);
2267
+
ret = phy_pipe_clk_register(qmp, np);
2535
2268
if (ret)
2536
2269
goto err_node_put;
2537
2270
2538
2271
qmp->mode = PHY_MODE_PCIE_RC;
2539
2272
2540
-
qmp->phy = devm_phy_create(dev, child, &qmp_pcie_phy_ops);
2273
+
qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
2541
2274
if (IS_ERR(qmp->phy)) {
2542
2275
ret = PTR_ERR(qmp->phy);
2543
2276
dev_err(dev, "failed to create PHY: %d\n", ret);
···
2549
2276
2550
2277
phy_set_drvdata(qmp->phy, qmp);
2551
2278
2552
-
of_node_put(child);
2279
+
of_node_put(np);
2553
2280
2554
2281
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2555
2282
2556
2283
return PTR_ERR_OR_ZERO(phy_provider);
2557
2284
2558
2285
err_node_put:
2559
-
of_node_put(child);
2286
+
of_node_put(np);
2560
2287
return ret;
2561
2288
}
2562
2289
···
2576
2303
}, {
2577
2304
.compatible = "qcom,sc8180x-qmp-pcie-phy",
2578
2305
.data = &sc8180x_pciephy_cfg,
2306
+
}, {
2307
+
.compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
2308
+
.data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
2309
+
}, {
2310
+
.compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
2311
+
.data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
2579
2312
}, {
2580
2313
.compatible = "qcom,sdm845-qhp-pcie-phy",
2581
2314
.data = &sdm845_qhp_pciephy_cfg,
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
···
8
8
#define QCOM_PHY_QMP_PCS_PCIE_V5_H_
9
9
10
10
/* Only for QMP V5 PHY - PCS_PCIE registers */
11
+
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
12
+
#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
11
13
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
12
14
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
13
15
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94