Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"We've been sitting on our fixes branch for a while, so this batch is
unfortunately on the large side.
A lot of these are tweaks and fixes to device trees, fixing various
bugs around clocks, reg ranges, etc. There's also a few defconfig
updates (which are on the late side, no more of those).
All in all the diffstat is bigger than ideal at this time, but nothing
in here seems particularly risky"
* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits)
reset: sunxi: fix spinlock initialization
ARM: dts: disable CCI on exynos5420 based arndale-octa
drivers: bus: check cci device tree node status
ARM: rockchip: disable jtag/sdmmc autoswitching on rk3288
ARM: nomadik: fix up leftover device tree pins
ARM: at91: board-dt-sama5: add phy_fixup to override NAND_Tree
ARM: at91/dt: sam9263: Add missing clocks to lcdc node
ARM: at91: sama5d3: dt: correct the sound route
ARM: at91/dt: sama5d4: fix the timer reg length
ARM: exynos_defconfig: Enable LM90 driver
ARM: exynos_defconfig: Enable options for display panel support
arm: dts: Use pmu_system_controller phandle for dp phy
ARM: shmobile: sh73a0 legacy: Set .control_parent for all irqpin instances
ARM: dts: berlin: correct BG2Q's SM GPIO location.
ARM: dts: berlin: add broken-cd and set bus width for eMMC in Marvell DMP DT
ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 host
ARM: dts: Revert disabling of smc91x for n900
ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling
ARM: dts: dra7-evm: fix qspi device tree partition size
ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT
...
+272
-80
+2
arch/arm/boot/dts/at91sam9263.dtsi
+2
arch/arm/boot/dts/at91sam9263.dtsi
+2
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+2
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+32
-31
arch/arm/boot/dts/berlin2q.dtsi
+32
-31
arch/arm/boot/dts/berlin2q.dtsi
···
83
83
compatible = "mrvl,pxav3-mmc";
84
84
reg = <0xab1000 0x200>;
85
85
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
86
-
clocks = <&chip CLKID_SDIO1XIN>;
86
+
clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
87
+
clock-names = "io", "core";
87
88
status = "disabled";
88
89
};
89
90
···
349
348
interrupt-parent = <&gic>;
350
349
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
351
350
};
352
-
353
-
gpio4: gpio@5000 {
354
-
compatible = "snps,dw-apb-gpio";
355
-
reg = <0x5000 0x400>;
356
-
#address-cells = <1>;
357
-
#size-cells = <0>;
358
-
359
-
porte: gpio-port@4 {
360
-
compatible = "snps,dw-apb-gpio-port";
361
-
gpio-controller;
362
-
#gpio-cells = <2>;
363
-
snps,nr-gpios = <32>;
364
-
reg = <0>;
365
-
};
366
-
};
367
-
368
-
gpio5: gpio@c000 {
369
-
compatible = "snps,dw-apb-gpio";
370
-
reg = <0xc000 0x400>;
371
-
#address-cells = <1>;
372
-
#size-cells = <0>;
373
-
374
-
portf: gpio-port@5 {
375
-
compatible = "snps,dw-apb-gpio-port";
376
-
gpio-controller;
377
-
#gpio-cells = <2>;
378
-
snps,nr-gpios = <32>;
379
-
reg = <0>;
380
-
};
381
-
};
382
351
};
383
352
384
353
chip: chip-control@ea0000 {
···
437
466
ranges = <0 0xfc0000 0x10000>;
438
467
interrupt-parent = <&sic>;
439
468
469
+
sm_gpio1: gpio@5000 {
470
+
compatible = "snps,dw-apb-gpio";
471
+
reg = <0x5000 0x400>;
472
+
#address-cells = <1>;
473
+
#size-cells = <0>;
474
+
475
+
portf: gpio-port@5 {
476
+
compatible = "snps,dw-apb-gpio-port";
477
+
gpio-controller;
478
+
#gpio-cells = <2>;
479
+
snps,nr-gpios = <32>;
480
+
reg = <0>;
481
+
};
482
+
};
483
+
440
484
i2c2: i2c@7000 {
441
485
compatible = "snps,designware-i2c";
442
486
#address-cells = <1>;
···
500
514
pinctrl-0 = <&uart1_pmux>;
501
515
pinctrl-names = "default";
502
516
status = "disabled";
517
+
};
518
+
519
+
sm_gpio0: gpio@c000 {
520
+
compatible = "snps,dw-apb-gpio";
521
+
reg = <0xc000 0x400>;
522
+
#address-cells = <1>;
523
+
#size-cells = <0>;
524
+
525
+
porte: gpio-port@4 {
526
+
compatible = "snps,dw-apb-gpio-port";
527
+
gpio-controller;
528
+
#gpio-cells = <2>;
529
+
snps,nr-gpios = <32>;
530
+
reg = <0>;
531
+
};
503
532
};
504
533
505
534
sysctrl: pin-controller@d000 {
+5
-5
arch/arm/boot/dts/dra7-evm.dts
+5
-5
arch/arm/boot/dts/dra7-evm.dts
···
499
499
};
500
500
partition@5 {
501
501
label = "QSPI.u-boot-spl-os";
502
-
reg = <0x00140000 0x00010000>;
502
+
reg = <0x00140000 0x00080000>;
503
503
};
504
504
partition@6 {
505
505
label = "QSPI.u-boot-env";
506
-
reg = <0x00150000 0x00010000>;
506
+
reg = <0x001c0000 0x00010000>;
507
507
};
508
508
partition@7 {
509
509
label = "QSPI.u-boot-env.backup1";
510
-
reg = <0x00160000 0x0010000>;
510
+
reg = <0x001d0000 0x0010000>;
511
511
};
512
512
partition@8 {
513
513
label = "QSPI.kernel";
514
-
reg = <0x00170000 0x0800000>;
514
+
reg = <0x001e0000 0x0800000>;
515
515
};
516
516
partition@9 {
517
517
label = "QSPI.file-system";
518
-
reg = <0x00970000 0x01690000>;
518
+
reg = <0x009e0000 0x01620000>;
519
519
};
520
520
};
521
521
};
+1
-1
arch/arm/boot/dts/exynos5250.dtsi
+1
-1
arch/arm/boot/dts/exynos5250.dtsi
+4
arch/arm/boot/dts/exynos5420-arndale-octa.dts
+4
arch/arm/boot/dts/exynos5420-arndale-octa.dts
+3
-3
arch/arm/boot/dts/exynos5420.dtsi
+3
-3
arch/arm/boot/dts/exynos5420.dtsi
···
120
120
};
121
121
};
122
122
123
-
cci@10d20000 {
123
+
cci: cci@10d20000 {
124
124
compatible = "arm,cci-400";
125
125
#address-cells = <1>;
126
126
#size-cells = <1>;
···
503
503
};
504
504
505
505
dp_phy: video-phy@10040728 {
506
-
compatible = "samsung,exynos5250-dp-video-phy";
507
-
reg = <0x10040728 4>;
506
+
compatible = "samsung,exynos5420-dp-video-phy";
507
+
samsung,pmu-syscon = <&pmu_system_controller>;
508
508
#phy-cells = <0>;
509
509
};
510
510
+1
-1
arch/arm/boot/dts/imx25.dtsi
+1
-1
arch/arm/boot/dts/imx25.dtsi
+5
-17
arch/arm/boot/dts/imx51-babbage.dts
+5
-17
arch/arm/boot/dts/imx51-babbage.dts
···
127
127
#address-cells = <1>;
128
128
#size-cells = <0>;
129
129
130
-
reg_usbh1_vbus: regulator@0 {
131
-
compatible = "regulator-fixed";
132
-
pinctrl-names = "default";
133
-
pinctrl-0 = <&pinctrl_usbh1reg>;
134
-
reg = <0>;
135
-
regulator-name = "usbh1_vbus";
136
-
regulator-min-microvolt = <5000000>;
137
-
regulator-max-microvolt = <5000000>;
138
-
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
139
-
enable-active-high;
140
-
};
141
-
142
-
reg_usbotg_vbus: regulator@1 {
130
+
reg_hub_reset: regulator@0 {
143
131
compatible = "regulator-fixed";
144
132
pinctrl-names = "default";
145
133
pinctrl-0 = <&pinctrl_usbotgreg>;
146
-
reg = <1>;
147
-
regulator-name = "usbotg_vbus";
134
+
reg = <0>;
135
+
regulator-name = "hub_reset";
148
136
regulator-min-microvolt = <5000000>;
149
137
regulator-max-microvolt = <5000000>;
150
138
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
···
164
176
reg = <0>;
165
177
clocks = <&clks IMX5_CLK_DUMMY>;
166
178
clock-names = "main_clk";
179
+
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
167
180
};
168
181
};
169
182
};
···
408
419
&usbh1 {
409
420
pinctrl-names = "default";
410
421
pinctrl-0 = <&pinctrl_usbh1>;
411
-
vbus-supply = <®_usbh1_vbus>;
422
+
vbus-supply = <®_hub_reset>;
412
423
fsl,usbphy = <&usbh1phy>;
413
424
phy_type = "ulpi";
414
425
status = "okay";
···
418
429
dr_mode = "otg";
419
430
disable-over-current;
420
431
phy_type = "utmi_wide";
421
-
vbus-supply = <®_usbotg_vbus>;
422
432
status = "okay";
423
433
};
424
434
+2
-2
arch/arm/boot/dts/imx6qdl.dtsi
+2
-2
arch/arm/boot/dts/imx6qdl.dtsi
···
335
335
vpu: vpu@02040000 {
336
336
compatible = "cnm,coda960";
337
337
reg = <0x02040000 0x3c000>;
338
-
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
339
-
<0 12 IRQ_TYPE_LEVEL_HIGH>;
338
+
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
339
+
<0 3 IRQ_TYPE_LEVEL_HIGH>;
340
340
interrupt-names = "bit", "jpeg";
341
341
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342
342
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
+1
arch/arm/boot/dts/ls1021a.dtsi
+1
arch/arm/boot/dts/ls1021a.dtsi
+1
-3
arch/arm/boot/dts/omap3-n900.dts
+1
-3
arch/arm/boot/dts/omap3-n900.dts
···
700
700
};
701
701
};
702
702
703
+
/* Ethernet is on some early development boards and qemu */
703
704
ethernet@gpmc {
704
705
compatible = "smsc,lan91c94";
705
-
706
-
status = "disabled";
707
-
708
706
interrupt-parent = <&gpio2>;
709
707
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
710
708
reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
+30
arch/arm/boot/dts/rk3288-evb.dtsi
+30
arch/arm/boot/dts/rk3288-evb.dtsi
···
155
155
};
156
156
157
157
&pinctrl {
158
+
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
159
+
drive-strength = <8>;
160
+
};
161
+
162
+
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
163
+
bias-pull-up;
164
+
drive-strength = <8>;
165
+
};
166
+
158
167
backlight {
159
168
bl_en: bl-en {
160
169
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
···
179
170
pmic {
180
171
pmic_int: pmic-int {
181
172
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
173
+
};
174
+
};
175
+
176
+
sdmmc {
177
+
/*
178
+
* Default drive strength isn't enough to achieve even
179
+
* high-speed mode on EVB board so bump up to 8ma.
180
+
*/
181
+
sdmmc_bus4: sdmmc-bus4 {
182
+
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
183
+
<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
184
+
<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
185
+
<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
186
+
};
187
+
188
+
sdmmc_clk: sdmmc-clk {
189
+
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
190
+
};
191
+
192
+
sdmmc_cmd: sdmmc-cmd {
193
+
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
182
194
};
183
195
};
184
196
+1
-1
arch/arm/boot/dts/sama5d3xmb.dtsi
+1
-1
arch/arm/boot/dts/sama5d3xmb.dtsi
+1
-1
arch/arm/boot/dts/sama5d4.dtsi
+1
-1
arch/arm/boot/dts/sama5d4.dtsi
+4
-4
arch/arm/boot/dts/ste-nomadik-nhk15.dts
+4
-4
arch/arm/boot/dts/ste-nomadik-nhk15.dts
···
25
25
stmpe2401_1 {
26
26
stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
27
27
nhk_cfg1 {
28
-
ste,pins = "GPIO76_B20"; // IRQ line
28
+
pins = "GPIO76_B20"; // IRQ line
29
29
ste,input = <0>;
30
30
};
31
31
nhk_cfg2 {
32
-
ste,pins = "GPIO77_B8"; // reset line
32
+
pins = "GPIO77_B8"; // reset line
33
33
ste,output = <1>;
34
34
};
35
35
};
···
37
37
stmpe2401_2 {
38
38
stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
39
39
nhk_cfg1 {
40
-
ste,pins = "GPIO78_A8"; // IRQ line
40
+
pins = "GPIO78_A8"; // IRQ line
41
41
ste,input = <0>;
42
42
};
43
43
nhk_cfg2 {
44
-
ste,pins = "GPIO79_C9"; // reset line
44
+
pins = "GPIO79_C9"; // reset line
45
45
ste,output = <1>;
46
46
};
47
47
};
+17
-1
arch/arm/configs/exynos_defconfig
+17
-1
arch/arm/configs/exynos_defconfig
···
84
84
CONFIG_POWER_SUPPLY=y
85
85
CONFIG_BATTERY_SBS=y
86
86
CONFIG_CHARGER_TPS65090=y
87
-
# CONFIG_HWMON is not set
87
+
CONFIG_HWMON=y
88
+
CONFIG_SENSORS_LM90=y
88
89
CONFIG_THERMAL=y
89
90
CONFIG_EXYNOS_THERMAL=y
90
91
CONFIG_EXYNOS_THERMAL_CORE=y
···
110
109
CONFIG_REGULATOR_S2MPS11=y
111
110
CONFIG_REGULATOR_S5M8767=y
112
111
CONFIG_REGULATOR_TPS65090=y
112
+
CONFIG_DRM=y
113
+
CONFIG_DRM_BRIDGE=y
114
+
CONFIG_DRM_PTN3460=y
115
+
CONFIG_DRM_PS8622=y
116
+
CONFIG_DRM_EXYNOS=y
117
+
CONFIG_DRM_EXYNOS_FIMD=y
118
+
CONFIG_DRM_EXYNOS_DP=y
119
+
CONFIG_DRM_PANEL=y
120
+
CONFIG_DRM_PANEL_SIMPLE=y
113
121
CONFIG_FB=y
114
122
CONFIG_FB_MODE_HELPERS=y
115
123
CONFIG_FB_SIMPLE=y
116
124
CONFIG_EXYNOS_VIDEO=y
117
125
CONFIG_EXYNOS_MIPI_DSI=y
126
+
CONFIG_BACKLIGHT_LCD_SUPPORT=y
127
+
CONFIG_LCD_CLASS_DEVICE=y
128
+
CONFIG_LCD_PLATFORM=y
129
+
CONFIG_BACKLIGHT_CLASS_DEVICE=y
130
+
CONFIG_BACKLIGHT_GENERIC=y
131
+
CONFIG_BACKLIGHT_PWM=y
118
132
CONFIG_FRAMEBUFFER_CONSOLE=y
119
133
CONFIG_FONTS=y
120
134
CONFIG_FONT_7x14=y
+1
-1
arch/arm/configs/omap2plus_defconfig
+1
-1
arch/arm/configs/omap2plus_defconfig
+18
arch/arm/mach-at91/board-dt-sama5.c
+18
arch/arm/mach-at91/board-dt-sama5.c
···
17
17
#include <linux/of_platform.h>
18
18
#include <linux/phy.h>
19
19
#include <linux/clk-provider.h>
20
+
#include <linux/phy.h>
20
21
21
22
#include <asm/setup.h>
22
23
#include <asm/irq.h>
···
27
26
28
27
#include "generic.h"
29
28
29
+
static int ksz8081_phy_fixup(struct phy_device *phy)
30
+
{
31
+
int value;
32
+
33
+
value = phy_read(phy, 0x16);
34
+
value &= ~0x20;
35
+
phy_write(phy, 0x16, value);
36
+
37
+
return 0;
38
+
}
39
+
30
40
static void __init sama5_dt_device_init(void)
31
41
{
42
+
if (of_machine_is_compatible("atmel,sama5d4ek") &&
43
+
IS_ENABLED(CONFIG_PHYLIB)) {
44
+
phy_register_fixup_for_id("fc028000.etherne:00",
45
+
ksz8081_phy_fixup);
46
+
}
47
+
32
48
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
33
49
}
34
50
+1
-1
arch/arm/mach-imx/clk-imx6q.c
+1
-1
arch/arm/mach-imx/clk-imx6q.c
···
144
144
post_div_table[1].div = 1;
145
145
post_div_table[2].div = 1;
146
146
video_div_table[1].div = 1;
147
-
video_div_table[2].div = 1;
147
+
video_div_table[3].div = 1;
148
148
}
149
149
150
150
clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
+3
arch/arm/mach-imx/clk-imx6sx.c
+3
arch/arm/mach-imx/clk-imx6sx.c
···
558
558
clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
559
559
clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
560
560
561
+
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
562
+
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
563
+
561
564
/* Set initial power mode */
562
565
imx6q_set_lpm(WAIT_CLOCKED);
563
566
}
+18
arch/arm/mach-omap2/board-generic.c
+18
arch/arm/mach-omap2/board-generic.c
···
77
77
#endif
78
78
79
79
#ifdef CONFIG_ARCH_OMAP3
80
+
/* Some boards need board name for legacy userspace in /proc/cpuinfo */
81
+
static const char *const n900_boards_compat[] __initconst = {
82
+
"nokia,omap3-n900",
83
+
NULL,
84
+
};
85
+
86
+
DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
87
+
.reserve = omap_reserve,
88
+
.map_io = omap3_map_io,
89
+
.init_early = omap3430_init_early,
90
+
.init_machine = omap_generic_init,
91
+
.init_late = omap3_init_late,
92
+
.init_time = omap3_sync32k_timer_init,
93
+
.dt_compat = n900_boards_compat,
94
+
.restart = omap3xxx_restart,
95
+
MACHINE_END
96
+
97
+
/* Generic omap3 boards, most boards can use these */
80
98
static const char *const omap3_boards_compat[] __initconst = {
81
99
"ti,omap3430",
82
100
"ti,omap3",
+1
arch/arm/mach-omap2/common.h
+1
arch/arm/mach-omap2/common.h
+4
arch/arm/mach-omap2/control.h
+4
arch/arm/mach-omap2/control.h
···
286
286
#define OMAP5XXX_CONTROL_STATUS 0x134
287
287
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
288
288
289
+
/* DRA7XX CONTROL CORE BOOTSTRAP */
290
+
#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
291
+
#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
292
+
289
293
/*
290
294
* REVISIT: This list of registers is not comprehensive - there are more
291
295
* that should be added.
+21
arch/arm/mach-omap2/omap-headsmp.S
+21
arch/arm/mach-omap2/omap-headsmp.S
···
22
22
23
23
/* Physical address needed since MMU not enabled yet on secondary core */
24
24
#define AUX_CORE_BOOT0_PA 0x48281800
25
+
#define API_HYP_ENTRY 0x102
25
26
26
27
/*
27
28
* OMAP5 specific entry point for secondary CPU to jump from ROM
···
41
40
bne wait
42
41
b secondary_startup
43
42
ENDPROC(omap5_secondary_startup)
43
+
/*
44
+
* Same as omap5_secondary_startup except we call into the ROM to
45
+
* enable HYP mode first. This is called instead of
46
+
* omap5_secondary_startup if the primary CPU was put into HYP mode by
47
+
* the boot loader.
48
+
*/
49
+
ENTRY(omap5_secondary_hyp_startup)
50
+
wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
51
+
ldr r0, [r2]
52
+
mov r0, r0, lsr #5
53
+
mrc p15, 0, r4, c0, c0, 5
54
+
and r4, r4, #0x0f
55
+
cmp r0, r4
56
+
bne wait_2
57
+
ldr r12, =API_HYP_ENTRY
58
+
adr r0, hyp_boot
59
+
smc #0
60
+
hyp_boot:
61
+
b secondary_startup
62
+
ENDPROC(omap5_secondary_hyp_startup)
44
63
/*
45
64
* OMAP4 specific entry point for secondary CPU to jump from ROM
46
65
* code. This routine also provides a holding flag into which
+11
-2
arch/arm/mach-omap2/omap-smp.c
+11
-2
arch/arm/mach-omap2/omap-smp.c
···
22
22
#include <linux/irqchip/arm-gic.h>
23
23
24
24
#include <asm/smp_scu.h>
25
+
#include <asm/virt.h>
25
26
26
27
#include "omap-secure.h"
27
28
#include "omap-wakeupgen.h"
···
228
227
if (omap_secure_apis_support())
229
228
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
230
229
else
231
-
writel_relaxed(virt_to_phys(omap5_secondary_startup),
232
-
base + OMAP_AUX_CORE_BOOT_1);
230
+
/*
231
+
* If the boot CPU is in HYP mode then start secondary
232
+
* CPU in HYP mode as well.
233
+
*/
234
+
if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
235
+
writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
236
+
base + OMAP_AUX_CORE_BOOT_1);
237
+
else
238
+
writel_relaxed(virt_to_phys(omap5_secondary_startup),
239
+
base + OMAP_AUX_CORE_BOOT_1);
233
240
234
241
}
235
242
+38
-6
arch/arm/mach-omap2/timer.c
+38
-6
arch/arm/mach-omap2/timer.c
···
54
54
55
55
#include "soc.h"
56
56
#include "common.h"
57
+
#include "control.h"
57
58
#include "powerdomain.h"
58
59
#include "omap-secure.h"
59
60
···
497
496
void __iomem *base;
498
497
static struct clk *sys_clk;
499
498
unsigned long rate;
500
-
unsigned int reg, num, den;
499
+
unsigned int reg;
500
+
unsigned long long num, den;
501
501
502
502
base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
503
503
if (!base) {
···
513
511
}
514
512
515
513
rate = clk_get_rate(sys_clk);
514
+
515
+
if (soc_is_dra7xx()) {
516
+
/*
517
+
* Errata i856 says the 32.768KHz crystal does not start at
518
+
* power on, so the CPU falls back to an emulated 32KHz clock
519
+
* based on sysclk / 610 instead. This causes the master counter
520
+
* frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
521
+
* (OR sysclk * 75 / 244)
522
+
*
523
+
* This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
524
+
* Of course any board built without a populated 32.768KHz
525
+
* crystal would also need this fix even if the CPU is fixed
526
+
* later.
527
+
*
528
+
* Either case can be detected by using the two speedselect bits
529
+
* If they are not 0, then the 32.768KHz clock driving the
530
+
* coarse counter that corrects the fine counter every time it
531
+
* ticks is actually rate/610 rather than 32.768KHz and we
532
+
* should compensate to avoid the 570ppm (at 20MHz, much worse
533
+
* at other rates) too fast system time.
534
+
*/
535
+
reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
536
+
if (reg & DRA7_SPEEDSELECT_MASK) {
537
+
num = 75;
538
+
den = 244;
539
+
goto sysclk1_based;
540
+
}
541
+
}
542
+
516
543
/* Numerator/denumerator values refer TRM Realtime Counter section */
517
544
switch (rate) {
518
-
case 1200000:
545
+
case 12000000:
519
546
num = 64;
520
547
den = 125;
521
548
break;
522
-
case 1300000:
549
+
case 13000000:
523
550
num = 768;
524
551
den = 1625;
525
552
break;
···
560
529
num = 192;
561
530
den = 625;
562
531
break;
563
-
case 2600000:
532
+
case 26000000:
564
533
num = 384;
565
534
den = 1625;
566
535
break;
567
-
case 2700000:
536
+
case 27000000:
568
537
num = 256;
569
538
den = 1125;
570
539
break;
···
576
545
break;
577
546
}
578
547
548
+
sysclk1_based:
579
549
/* Program numerator and denumerator registers */
580
550
reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
581
551
NUMERATOR_DENUMERATOR_MASK;
···
588
556
reg |= den;
589
557
writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
590
558
591
-
arch_timer_freq = (rate / den) * num;
559
+
arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
592
560
set_cntfreq();
593
561
594
562
iounmap(base);
+27
arch/arm/mach-rockchip/rockchip.c
+27
arch/arm/mach-rockchip/rockchip.c
···
19
19
#include <linux/init.h>
20
20
#include <linux/of_platform.h>
21
21
#include <linux/irqchip.h>
22
+
#include <linux/clk-provider.h>
23
+
#include <linux/clocksource.h>
24
+
#include <linux/mfd/syscon.h>
25
+
#include <linux/regmap.h>
22
26
#include <asm/mach/arch.h>
23
27
#include <asm/mach/map.h>
24
28
#include <asm/hardware/cache-l2x0.h>
25
29
#include "core.h"
30
+
31
+
#define RK3288_GRF_SOC_CON0 0x244
32
+
33
+
static void __init rockchip_timer_init(void)
34
+
{
35
+
if (of_machine_is_compatible("rockchip,rk3288")) {
36
+
struct regmap *grf;
37
+
38
+
/*
39
+
* Disable auto jtag/sdmmc switching that causes issues
40
+
* with the mmc controllers making them unreliable
41
+
*/
42
+
grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
43
+
if (!IS_ERR(grf))
44
+
regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
45
+
else
46
+
pr_err("rockchip: could not get grf syscon\n");
47
+
}
48
+
49
+
of_clk_init(NULL);
50
+
clocksource_of_init();
51
+
}
26
52
27
53
static void __init rockchip_dt_init(void)
28
54
{
···
68
42
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
69
43
.l2c_aux_val = 0,
70
44
.l2c_aux_mask = ~0,
45
+
.init_time = rockchip_timer_init,
71
46
.dt_compat = rockchip_board_dt_compat,
72
47
.init_machine = rockchip_dt_init,
73
48
MACHINE_END
+7
arch/arm/mach-shmobile/setup-r8a7740.c
+7
arch/arm/mach-shmobile/setup-r8a7740.c
···
800
800
void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
801
801
void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
802
802
803
+
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
804
+
void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
805
+
void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
806
+
807
+
gic_init(0, 29, gic_dist_base, gic_cpu_base);
808
+
#else
803
809
irqchip_init();
810
+
#endif
804
811
805
812
/* route signals to GIC */
806
813
iowrite32(0x0, pfc_inta_ctrl);
+3
arch/arm/mach-shmobile/setup-sh73a0.c
+3
arch/arm/mach-shmobile/setup-sh73a0.c
···
595
595
596
596
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
597
597
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
598
+
.control_parent = true,
598
599
};
599
600
600
601
static struct resource irqpin0_resources[] = {
···
657
656
658
657
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
659
658
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
659
+
.control_parent = true,
660
660
};
661
661
662
662
static struct resource irqpin2_resources[] = {
···
688
686
689
687
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
690
688
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
689
+
.control_parent = true,
691
690
};
692
691
693
692
static struct resource irqpin3_resources[] = {
+3
drivers/bus/arm-cci.c
+3
drivers/bus/arm-cci.c
+4
drivers/reset/reset-sunxi.c
+4
drivers/reset/reset-sunxi.c
···
102
102
goto err_alloc;
103
103
}
104
104
105
+
spin_lock_init(&data->lock);
106
+
105
107
data->rcdev.owner = THIS_MODULE;
106
108
data->rcdev.nr_resets = size * 32;
107
109
data->rcdev.ops = &sunxi_reset_ops;
···
158
156
data->membase = devm_ioremap_resource(&pdev->dev, res);
159
157
if (IS_ERR(data->membase))
160
158
return PTR_ERR(data->membase);
159
+
160
+
spin_lock_init(&data->lock);
161
161
162
162
data->rcdev.owner = THIS_MODULE;
163
163
data->rcdev.nr_resets = resource_size(res) * 32;