Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.
For the CMD panel usecase some of IRQ indexes depend on the selected
resources. Move setting them to the irq_enable() callback.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577529/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-3-caf5dcd125c0@linaro.org
+17
-46
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
···
69
69
* @is_master: Whether this phys_enc is the current master
70
70
* encoder. Can be switched at enable time. Based
71
71
* on split_role and current mode (CMD/VID).
72
-
* @atomic_mode_set: DRM Call. Set a DRM mode.
73
-
* This likely caches the mode, for use at enable.
74
72
* @enable: DRM Call. Enable a DRM mode.
75
73
* @disable: DRM Call. Disable mode.
76
74
* @atomic_check: DRM Call. Atomic check new DRM state.
···
94
96
struct dpu_encoder_phys_ops {
95
97
void (*prepare_commit)(struct dpu_encoder_phys *encoder);
96
98
bool (*is_master)(struct dpu_encoder_phys *encoder);
97
-
void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
98
-
struct drm_crtc_state *crtc_state,
99
-
struct drm_connector_state *conn_state);
100
99
void (*enable)(struct dpu_encoder_phys *encoder);
101
100
void (*disable)(struct dpu_encoder_phys *encoder);
102
101
int (*atomic_check)(struct dpu_encoder_phys *encoder,
+14
-18
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+14
-18
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
···
142
142
dpu_encoder_underrun_callback(phys_enc->parent, phys_enc);
143
143
}
144
144
145
-
static void dpu_encoder_phys_cmd_atomic_mode_set(
146
-
struct dpu_encoder_phys *phys_enc,
147
-
struct drm_crtc_state *crtc_state,
148
-
struct drm_connector_state *conn_state)
149
-
{
150
-
phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
151
-
152
-
phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
153
-
154
-
if (phys_enc->has_intf_te)
155
-
phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr;
156
-
else
157
-
phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr;
158
-
159
-
phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
160
-
}
161
-
162
145
static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
163
146
struct dpu_encoder_phys *phys_enc)
164
147
{
···
280
297
phys_enc->hw_pp->idx - PINGPONG_0,
281
298
phys_enc->vblank_refcount);
282
299
300
+
phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start;
301
+
phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done;
302
+
303
+
if (phys_enc->has_intf_te)
304
+
phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr;
305
+
else
306
+
phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr;
307
+
283
308
dpu_core_irq_register_callback(phys_enc->dpu_kms,
284
309
phys_enc->irq[INTR_IDX_PINGPONG],
285
310
dpu_encoder_phys_cmd_pp_tx_done_irq,
···
318
327
dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]);
319
328
dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
320
329
dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]);
330
+
331
+
phys_enc->irq[INTR_IDX_CTL_START] = 0;
332
+
phys_enc->irq[INTR_IDX_PINGPONG] = 0;
333
+
phys_enc->irq[INTR_IDX_RDPTR] = 0;
321
334
}
322
335
323
336
static void dpu_encoder_phys_cmd_tearcheck_config(
···
701
706
struct dpu_encoder_phys_ops *ops)
702
707
{
703
708
ops->is_master = dpu_encoder_phys_cmd_is_master;
704
-
ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set;
705
709
ops->enable = dpu_encoder_phys_cmd_enable;
706
710
ops->disable = dpu_encoder_phys_cmd_disable;
707
711
ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;
···
739
745
740
746
dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
741
747
phys_enc->intf_mode = INTF_MODE_CMD;
748
+
phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
749
+
742
750
cmd_enc->stream_sel = 0;
743
751
744
752
if (!phys_enc->hw_intf) {
+2
-11
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+2
-11
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
···
350
350
return phys_enc->split_role != ENC_ROLE_SOLO;
351
351
}
352
352
353
-
static void dpu_encoder_phys_vid_atomic_mode_set(
354
-
struct dpu_encoder_phys *phys_enc,
355
-
struct drm_crtc_state *crtc_state,
356
-
struct drm_connector_state *conn_state)
357
-
{
358
-
phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
359
-
360
-
phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
361
-
}
362
-
363
353
static int dpu_encoder_phys_vid_control_vblank_irq(
364
354
struct dpu_encoder_phys *phys_enc,
365
355
bool enable)
···
677
687
static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
678
688
{
679
689
ops->is_master = dpu_encoder_phys_vid_is_master;
680
-
ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set;
681
690
ops->enable = dpu_encoder_phys_vid_enable;
682
691
ops->disable = dpu_encoder_phys_vid_disable;
683
692
ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
···
715
726
716
727
dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
717
728
phys_enc->intf_mode = INTF_MODE_VIDEO;
729
+
phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync;
730
+
phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun;
718
731
719
732
DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);
720
733
+1
-10
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+1
-10
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
···
539
539
dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
540
540
}
541
541
542
-
static void dpu_encoder_phys_wb_atomic_mode_set(
543
-
struct dpu_encoder_phys *phys_enc,
544
-
struct drm_crtc_state *crtc_state,
545
-
struct drm_connector_state *conn_state)
546
-
{
547
-
548
-
phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
549
-
}
550
-
551
542
static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
552
543
struct dpu_encoder_phys *phys_enc)
553
544
{
···
775
784
static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
776
785
{
777
786
ops->is_master = dpu_encoder_phys_wb_is_master;
778
-
ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
779
787
ops->enable = dpu_encoder_phys_wb_enable;
780
788
ops->disable = dpu_encoder_phys_wb_disable;
781
789
ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
···
821
831
822
832
dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
823
833
phys_enc->intf_mode = INTF_MODE_WB_LINE;
834
+
phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
824
835
825
836
atomic_set(&wb_enc->wbirq_refcount, 0);
826
837