Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clocksource/drivers: Add Realtek system timer driver
Add a system timer driver for Realtek SoCs.
This driver registers the 1 MHz global hardware counter on Realtek
platforms as a clock event device. Since this hardware counter starts
counting automatically after SoC power-on, no clock initialization is
required. Because the counter does not stop or get affected by CPU power
down, and it supports oneshot mode, it is typically used as a tick
broadcast timer.
Signed-off-by: Hao-Wen Ting <haowen.ting@realtek.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/20251126060110.198330-3-haowen.ting@realtek.com
authored by
Hao-Wen Ting
and committed by
Daniel Lezcano
d1780dce
40caba2b
+167
+5
MAINTAINERS
+5
MAINTAINERS
···
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F: Documentation/devicetree/bindings/spi/realtek,rtl9301-snand.yaml
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F: drivers/spi/spi-realtek-rtl-snand.c
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REALTEK SYSTIMER DRIVER
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M: Hao-Wen Ting <haowen.ting@realtek.com>
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S: Maintained
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F: drivers/clocksource/timer-realtek.c
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REALTEK WIRELESS DRIVER (rtlwifi family)
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M: Ping-Ke Shih <pkshih@realtek.com>
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L: linux-wireless@vger.kernel.org
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drivers/clocksource/Kconfig
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drivers/clocksource/Kconfig
···
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Enables the support for NXP System Timer Module found in the
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s32g NXP platform series.
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config RTK_SYSTIMER
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bool "Realtek SYSTIMER support"
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depends on ARM || ARM64
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depends on ARCH_REALTEK || COMPILE_TEST
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select TIMER_OF
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help
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This option enables the driver that registers the global 1 MHz hardware
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counter as a clock event device on Realtek SoCs. Make sure to enable
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this option only when building for a Realtek platform or for compilation
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testing.
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endmenu
+1
drivers/clocksource/Makefile
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drivers/clocksource/Makefile
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drivers/clocksource/timer-realtek.c
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drivers/clocksource/timer-realtek.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 Realtek Semiconductor Corp.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/irqflags.h>
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#include <linux/interrupt.h>
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#include "timer-of.h"
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#define ENBL 1
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#define DSBL 0
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#define SYSTIMER_RATE 1000000
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#define SYSTIMER_MIN_DELTA 0x64
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#define SYSTIMER_MAX_DELTA ULONG_MAX
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/* SYSTIMER Register Offset (RTK Internal Use) */
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#define TS_LW_OFST 0x0
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#define TS_HW_OFST 0x4
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#define TS_CMP_VAL_LW_OFST 0x8
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#define TS_CMP_VAL_HW_OFST 0xC
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#define TS_CMP_CTRL_OFST 0x10
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#define TS_CMP_STAT_OFST 0x14
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/* SYSTIMER CMP CTRL REG Mask */
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#define TS_CMP_EN_MASK 0x1
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#define TS_WR_EN0_MASK 0x2
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static void __iomem *systimer_base;
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static u64 rtk_ts64_read(void)
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{
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u32 low, high;
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u64 ts;
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/* Caution: Read LSB word (TS_LW_OFST) first then MSB (TS_HW_OFST) */
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low = readl(systimer_base + TS_LW_OFST);
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high = readl(systimer_base + TS_HW_OFST);
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ts = ((u64)high << 32) | low;
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return ts;
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}
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static void rtk_cmp_value_write(u64 value)
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{
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u32 high, low;
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low = value & 0xFFFFFFFF;
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high = value >> 32;
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writel(high, systimer_base + TS_CMP_VAL_HW_OFST);
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writel(low, systimer_base + TS_CMP_VAL_LW_OFST);
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}
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static inline void rtk_cmp_en_write(bool cmp_en)
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{
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u32 val;
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val = TS_WR_EN0_MASK;
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if (cmp_en == ENBL)
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val |= TS_CMP_EN_MASK;
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writel(val, systimer_base + TS_CMP_CTRL_OFST);
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}
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static int rtk_syst_clkevt_next_event(unsigned long cycles, struct clock_event_device *clkevt)
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{
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u64 cmp_val;
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rtk_cmp_en_write(DSBL);
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cmp_val = rtk_ts64_read();
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/* Set CMP value to current timestamp plus delta_us */
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rtk_cmp_value_write(cmp_val + cycles);
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rtk_cmp_en_write(ENBL);
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return 0;
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}
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static irqreturn_t rtk_ts_match_intr_handler(int irq, void *dev_id)
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{
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struct clock_event_device *clkevt = dev_id;
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void __iomem *reg_base;
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u32 val;
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/* Disable TS CMP Match */
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rtk_cmp_en_write(DSBL);
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/* Clear TS CMP INTR */
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reg_base = systimer_base + TS_CMP_STAT_OFST;
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val = readl(reg_base) & TS_CMP_EN_MASK;
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writel(val | TS_CMP_EN_MASK, reg_base);
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clkevt->event_handler(clkevt);
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return IRQ_HANDLED;
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}
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static int rtk_syst_shutdown(struct clock_event_device *clkevt)
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{
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void __iomem *reg_base;
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u64 cmp_val = 0;
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/* Disable TS CMP Match */
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rtk_cmp_en_write(DSBL);
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/* Set compare value to 0 */
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rtk_cmp_value_write(cmp_val);
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/* Clear TS CMP INTR */
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reg_base = systimer_base + TS_CMP_STAT_OFST;
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writel(TS_CMP_EN_MASK, reg_base);
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return 0;
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}
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static struct timer_of rtk_timer_to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE,
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.clkevt = {
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.name = "rtk-clkevt",
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.rating = 300,
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.cpumask = cpu_possible_mask,
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.features = CLOCK_EVT_FEAT_DYNIRQ |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = rtk_syst_clkevt_next_event,
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.set_state_oneshot = rtk_syst_shutdown,
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.set_state_shutdown = rtk_syst_shutdown,
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},
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.of_irq = {
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = rtk_ts_match_intr_handler,
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},
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};
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static int __init rtk_systimer_init(struct device_node *node)
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{
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int ret;
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ret = timer_of_init(node, &rtk_timer_to);
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if (ret)
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return ret;
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systimer_base = timer_of_base(&rtk_timer_to);
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clockevents_config_and_register(&rtk_timer_to.clkevt, SYSTIMER_RATE,
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SYSTIMER_MIN_DELTA, SYSTIMER_MAX_DELTA);
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return 0;
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}
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TIMER_OF_DECLARE(rtk_systimer, "realtek,rtd1625-systimer", rtk_systimer_init);