Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: sc8180x: Add PCIe instances
This patch adds PCIe instances found on this SoC
Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230530162454.51708-11-vkoul@kernel.org
authored by
Vinod Koul
and committed by
Bjorn Andersson
d20b6c84
0018761d
+429
+429
arch/arm64/boot/dts/qcom/sc8180x.dtsi
+429
arch/arm64/boot/dts/qcom/sc8180x.dtsi
···
1681
1681
qcom,bcm-voters = <&apps_bcm_voter>;
1682
1682
};
1683
1683
1684
+
pcie0: pci@1c00000 {
1685
+
compatible = "qcom,pcie-sc8180x";
1686
+
reg = <0 0x01c00000 0 0x3000>,
1687
+
<0 0x60000000 0 0xf1d>,
1688
+
<0 0x60000f20 0 0xa8>,
1689
+
<0 0x60001000 0 0x1000>,
1690
+
<0 0x60100000 0 0x100000>;
1691
+
reg-names = "parf",
1692
+
"dbi",
1693
+
"elbi",
1694
+
"atu",
1695
+
"config";
1696
+
device_type = "pci";
1697
+
linux,pci-domain = <0>;
1698
+
bus-range = <0x00 0xff>;
1699
+
num-lanes = <2>;
1700
+
1701
+
#address-cells = <3>;
1702
+
#size-cells = <2>;
1703
+
1704
+
ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1705
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1706
+
1707
+
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1708
+
interrupt-names = "msi";
1709
+
#interrupt-cells = <1>;
1710
+
interrupt-map-mask = <0 0 0 0x7>;
1711
+
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1712
+
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1713
+
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1714
+
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1715
+
1716
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1717
+
<&gcc GCC_PCIE_0_AUX_CLK>,
1718
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1719
+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1720
+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1721
+
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1722
+
<&gcc GCC_PCIE_0_CLKREF_CLK>,
1723
+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1724
+
clock-names = "pipe",
1725
+
"aux",
1726
+
"cfg",
1727
+
"bus_master",
1728
+
"bus_slave",
1729
+
"slave_q2a",
1730
+
"ref",
1731
+
"tbu";
1732
+
1733
+
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1734
+
assigned-clock-rates = <19200000>;
1735
+
1736
+
iommus = <&apps_smmu 0x1d80 0x7f>;
1737
+
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1738
+
<0x100 &apps_smmu 0x1d81 0x1>;
1739
+
1740
+
resets = <&gcc GCC_PCIE_0_BCR>;
1741
+
reset-names = "pci";
1742
+
1743
+
power-domains = <&gcc PCIE_0_GDSC>;
1744
+
1745
+
interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1746
+
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1747
+
interconnect-names = "pcie-mem", "cpu-pcie";
1748
+
1749
+
phys = <&pcie0_lane>;
1750
+
phy-names = "pciephy";
1751
+
1752
+
status = "disabled";
1753
+
};
1754
+
1755
+
pcie0_phy: phy-wrapper@1c06000 {
1756
+
compatible = "qcom,sc8180x-qmp-pcie-phy";
1757
+
reg = <0 0x1c06000 0 0x1c0>;
1758
+
#address-cells = <2>;
1759
+
#size-cells = <2>;
1760
+
ranges;
1761
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1762
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1763
+
<&gcc GCC_PCIE_0_CLKREF_CLK>,
1764
+
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1765
+
clock-names = "aux", "cfg_ahb", "ref", "refgen";
1766
+
1767
+
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1768
+
reset-names = "phy";
1769
+
1770
+
assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1771
+
assigned-clock-rates = <100000000>;
1772
+
1773
+
status = "disabled";
1774
+
1775
+
pcie0_lane: phy@1c06200 {
1776
+
reg = <0 0x1c06200 0 0x170>, /* tx0 */
1777
+
<0 0x1c06400 0 0x200>, /* rx0 */
1778
+
<0 0x1c06a00 0 0x1f0>, /* pcs */
1779
+
<0 0x1c06600 0 0x170>, /* tx1 */
1780
+
<0 0x1c06800 0 0x200>, /* rx1 */
1781
+
<0 0x1c06e00 0 0xf4>; /* pcs_com */
1782
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1783
+
clock-names = "pipe0";
1784
+
1785
+
#clock-cells = <0>;
1786
+
clock-output-names = "pcie_0_pipe_clk";
1787
+
#phy-cells = <0>;
1788
+
};
1789
+
};
1790
+
1791
+
pcie3: pci@1c08000 {
1792
+
compatible = "qcom,pcie-sc8180x";
1793
+
reg = <0 0x01c08000 0 0x3000>,
1794
+
<0 0x40000000 0 0xf1d>,
1795
+
<0 0x40000f20 0 0xa8>,
1796
+
<0 0x40001000 0 0x1000>,
1797
+
<0 0x40100000 0 0x100000>;
1798
+
reg-names = "parf",
1799
+
"dbi",
1800
+
"elbi",
1801
+
"atu",
1802
+
"config";
1803
+
device_type = "pci";
1804
+
linux,pci-domain = <3>;
1805
+
bus-range = <0x00 0xff>;
1806
+
num-lanes = <2>;
1807
+
1808
+
#address-cells = <3>;
1809
+
#size-cells = <2>;
1810
+
1811
+
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1812
+
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1813
+
1814
+
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1815
+
interrupt-names = "msi";
1816
+
#interrupt-cells = <1>;
1817
+
interrupt-map-mask = <0 0 0 0x7>;
1818
+
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1819
+
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1820
+
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1821
+
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1822
+
1823
+
clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1824
+
<&gcc GCC_PCIE_3_AUX_CLK>,
1825
+
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1826
+
<&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1827
+
<&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1828
+
<&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1829
+
<&gcc GCC_PCIE_3_CLKREF_CLK>,
1830
+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1831
+
clock-names = "pipe",
1832
+
"aux",
1833
+
"cfg",
1834
+
"bus_master",
1835
+
"bus_slave",
1836
+
"slave_q2a",
1837
+
"ref",
1838
+
"tbu";
1839
+
1840
+
assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1841
+
assigned-clock-rates = <19200000>;
1842
+
1843
+
iommus = <&apps_smmu 0x1e00 0x7f>;
1844
+
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1845
+
<0x100 &apps_smmu 0x1e01 0x1>;
1846
+
1847
+
resets = <&gcc GCC_PCIE_3_BCR>;
1848
+
reset-names = "pci";
1849
+
1850
+
power-domains = <&gcc PCIE_3_GDSC>;
1851
+
1852
+
interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1853
+
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1854
+
interconnect-names = "pcie-mem", "cpu-pcie";
1855
+
1856
+
phys = <&pcie3_lane>;
1857
+
phy-names = "pciephy";
1858
+
1859
+
status = "disabled";
1860
+
};
1861
+
1862
+
pcie3_phy: phy-wrapper@1c0c000 {
1863
+
compatible = "qcom,sc8180x-qmp-pcie-phy";
1864
+
reg = <0 0x1c0c000 0 0x1c0>;
1865
+
#address-cells = <2>;
1866
+
#size-cells = <2>;
1867
+
ranges;
1868
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1869
+
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1870
+
<&gcc GCC_PCIE_3_CLKREF_CLK>,
1871
+
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1872
+
clock-names = "aux", "cfg_ahb", "ref", "refgen";
1873
+
1874
+
resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1875
+
reset-names = "phy";
1876
+
1877
+
assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1878
+
assigned-clock-rates = <100000000>;
1879
+
1880
+
status = "disabled";
1881
+
1882
+
pcie3_lane: phy@1c0c200 {
1883
+
reg = <0 0x1c0c200 0 0x170>, /* tx0 */
1884
+
<0 0x1c0c400 0 0x200>, /* rx0 */
1885
+
<0 0x1c0ca00 0 0x1f0>, /* pcs */
1886
+
<0 0x1c0c600 0 0x170>, /* tx1 */
1887
+
<0 0x1c0c800 0 0x200>, /* rx1 */
1888
+
<0 0x1c0ce00 0 0xf4>; /* pcs_com */
1889
+
clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
1890
+
clock-names = "pipe0";
1891
+
1892
+
#clock-cells = <0>;
1893
+
clock-output-names = "pcie_3_pipe_clk";
1894
+
#phy-cells = <0>;
1895
+
};
1896
+
};
1897
+
1898
+
pcie1: pci@1c10000 {
1899
+
compatible = "qcom,pcie-sc8180x";
1900
+
reg = <0 0x01c10000 0 0x3000>,
1901
+
<0 0x68000000 0 0xf1d>,
1902
+
<0 0x68000f20 0 0xa8>,
1903
+
<0 0x68001000 0 0x1000>,
1904
+
<0 0x68100000 0 0x100000>;
1905
+
reg-names = "parf",
1906
+
"dbi",
1907
+
"elbi",
1908
+
"atu",
1909
+
"config";
1910
+
device_type = "pci";
1911
+
linux,pci-domain = <1>;
1912
+
bus-range = <0x00 0xff>;
1913
+
num-lanes = <2>;
1914
+
1915
+
#address-cells = <3>;
1916
+
#size-cells = <2>;
1917
+
1918
+
ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1919
+
<0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1920
+
1921
+
interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
1922
+
interrupt-names = "msi";
1923
+
#interrupt-cells = <1>;
1924
+
interrupt-map-mask = <0 0 0 0x7>;
1925
+
interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1926
+
<0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1927
+
<0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1928
+
<0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1929
+
1930
+
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1931
+
<&gcc GCC_PCIE_1_AUX_CLK>,
1932
+
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1933
+
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1934
+
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1935
+
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1936
+
<&gcc GCC_PCIE_1_CLKREF_CLK>,
1937
+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1938
+
clock-names = "pipe",
1939
+
"aux",
1940
+
"cfg",
1941
+
"bus_master",
1942
+
"bus_slave",
1943
+
"slave_q2a",
1944
+
"ref",
1945
+
"tbu";
1946
+
1947
+
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1948
+
assigned-clock-rates = <19200000>;
1949
+
1950
+
iommus = <&apps_smmu 0x1c80 0x7f>;
1951
+
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1952
+
<0x100 &apps_smmu 0x1c81 0x1>;
1953
+
1954
+
resets = <&gcc GCC_PCIE_1_BCR>;
1955
+
reset-names = "pci";
1956
+
1957
+
power-domains = <&gcc PCIE_1_GDSC>;
1958
+
1959
+
interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1960
+
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1961
+
interconnect-names = "pcie-mem", "cpu-pcie";
1962
+
1963
+
phys = <&pcie1_lane>;
1964
+
phy-names = "pciephy";
1965
+
1966
+
status = "disabled";
1967
+
};
1968
+
1969
+
pcie1_phy: phy-wrapper@1c16000 {
1970
+
compatible = "qcom,sc8180x-qmp-pcie-phy";
1971
+
reg = <0 0x1c16000 0 0x1c0>;
1972
+
#address-cells = <2>;
1973
+
#size-cells = <2>;
1974
+
ranges;
1975
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1976
+
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1977
+
<&gcc GCC_PCIE_1_CLKREF_CLK>,
1978
+
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1979
+
clock-names = "aux", "cfg_ahb", "ref", "refgen";
1980
+
1981
+
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1982
+
reset-names = "phy";
1983
+
1984
+
assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1985
+
assigned-clock-rates = <100000000>;
1986
+
1987
+
status = "disabled";
1988
+
1989
+
pcie1_lane: phy@1c0e200 {
1990
+
reg = <0 0x1c16200 0 0x170>, /* tx0 */
1991
+
<0 0x1c16400 0 0x200>, /* rx0 */
1992
+
<0 0x1c16a00 0 0x1f0>, /* pcs */
1993
+
<0 0x1c16600 0 0x170>, /* tx1 */
1994
+
<0 0x1c16800 0 0x200>, /* rx1 */
1995
+
<0 0x1c16e00 0 0xf4>; /* pcs_com */
1996
+
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1997
+
clock-names = "pipe0";
1998
+
#clock-cells = <0>;
1999
+
clock-output-names = "pcie_1_pipe_clk";
2000
+
2001
+
#phy-cells = <0>;
2002
+
};
2003
+
};
2004
+
2005
+
pcie2: pci@1c18000 {
2006
+
compatible = "qcom,pcie-sc8180x";
2007
+
reg = <0 0x01c18000 0 0x3000>,
2008
+
<0 0x70000000 0 0xf1d>,
2009
+
<0 0x70000f20 0 0xa8>,
2010
+
<0 0x70001000 0 0x1000>,
2011
+
<0 0x70100000 0 0x100000>;
2012
+
reg-names = "parf",
2013
+
"dbi",
2014
+
"elbi",
2015
+
"atu",
2016
+
"config";
2017
+
device_type = "pci";
2018
+
linux,pci-domain = <2>;
2019
+
bus-range = <0x00 0xff>;
2020
+
num-lanes = <4>;
2021
+
2022
+
#address-cells = <3>;
2023
+
#size-cells = <2>;
2024
+
2025
+
ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2026
+
<0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2027
+
2028
+
interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>;
2029
+
interrupt-names = "msi";
2030
+
#interrupt-cells = <1>;
2031
+
interrupt-map-mask = <0 0 0 0x7>;
2032
+
interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2033
+
<0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2034
+
<0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2035
+
<0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2036
+
2037
+
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2038
+
<&gcc GCC_PCIE_2_AUX_CLK>,
2039
+
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2040
+
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2041
+
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2042
+
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2043
+
<&gcc GCC_PCIE_2_CLKREF_CLK>,
2044
+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2045
+
clock-names = "pipe",
2046
+
"aux",
2047
+
"cfg",
2048
+
"bus_master",
2049
+
"bus_slave",
2050
+
"slave_q2a",
2051
+
"ref",
2052
+
"tbu";
2053
+
2054
+
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2055
+
assigned-clock-rates = <19200000>;
2056
+
2057
+
iommus = <&apps_smmu 0x1d00 0x7f>;
2058
+
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2059
+
<0x100 &apps_smmu 0x1d01 0x1>;
2060
+
2061
+
resets = <&gcc GCC_PCIE_2_BCR>;
2062
+
reset-names = "pci";
2063
+
2064
+
power-domains = <&gcc PCIE_2_GDSC>;
2065
+
2066
+
interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2067
+
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2068
+
interconnect-names = "pcie-mem", "cpu-pcie";
2069
+
2070
+
phys = <&pcie2_lane>;
2071
+
phy-names = "pciephy";
2072
+
2073
+
status = "disabled";
2074
+
};
2075
+
2076
+
pcie2_phy: phy-wrapper@1c1c000 {
2077
+
compatible = "qcom,sc8180x-qmp-pcie-phy";
2078
+
reg = <0 0x1c1c000 0 0x1c0>;
2079
+
#address-cells = <2>;
2080
+
#size-cells = <2>;
2081
+
ranges;
2082
+
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2083
+
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2084
+
<&gcc GCC_PCIE_2_CLKREF_CLK>,
2085
+
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2086
+
clock-names = "aux", "cfg_ahb", "ref", "refgen";
2087
+
2088
+
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2089
+
reset-names = "phy";
2090
+
2091
+
assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2092
+
assigned-clock-rates = <100000000>;
2093
+
2094
+
status = "disabled";
2095
+
2096
+
pcie2_lane: phy@1c0e200 {
2097
+
reg = <0 0x1c1c200 0 0x170>, /* tx0 */
2098
+
<0 0x1c1c400 0 0x200>, /* rx0 */
2099
+
<0 0x1c1ca00 0 0x1f0>, /* pcs */
2100
+
<0 0x1c1c600 0 0x170>, /* tx1 */
2101
+
<0 0x1c1c800 0 0x200>, /* rx1 */
2102
+
<0 0x1c1ce00 0 0xf4>; /* pcs_com */
2103
+
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2104
+
clock-names = "pipe0";
2105
+
2106
+
#clock-cells = <0>;
2107
+
clock-output-names = "pcie_2_pipe_clk";
2108
+
2109
+
#phy-cells = <0>;
2110
+
};
2111
+
};
2112
+
1684
2113
ufs_mem_hc: ufshc@1d84000 {
1685
2114
compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
1686
2115
"jedec,ufs-2.0";