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clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllers

Add module clock and reset definitions for RIIC controllers 0-8, which
are available on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven d3c25dd1 82a0bc72

+27
+27
drivers/clk/renesas/r9a09g056-cpg.c
··· 154 154 BUS_MSTOP(12, BIT(0))), 155 155 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 156 156 BUS_MSTOP(3, BIT(14))), 157 + DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 158 + BUS_MSTOP(3, BIT(13))), 159 + DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 160 + BUS_MSTOP(1, BIT(1))), 161 + DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 162 + BUS_MSTOP(1, BIT(2))), 163 + DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 164 + BUS_MSTOP(1, BIT(3))), 165 + DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 166 + BUS_MSTOP(1, BIT(4))), 167 + DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 168 + BUS_MSTOP(1, BIT(5))), 169 + DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 170 + BUS_MSTOP(1, BIT(6))), 171 + DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 172 + BUS_MSTOP(1, BIT(7))), 173 + DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 174 + BUS_MSTOP(1, BIT(8))), 157 175 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 158 176 BUS_MSTOP(8, BIT(2))), 159 177 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, ··· 235 217 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 236 218 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 237 219 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 220 + DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 221 + DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 222 + DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 223 + DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 224 + DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 225 + DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 226 + DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 227 + DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 228 + DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 238 229 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 239 230 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 240 231 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */