Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: phy: micrel: Replace hardcoded pages with defines
The functions lan_*_page_reg gets as a second parameter the page
where the register is. In all the functions the page was hardcoded.
Replace the hardcoded values with defines to make it more clear
what are those parameters.
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://patch.msgid.link/20250818075121.1298170-4-horatiu.vultur@microchip.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
Horatiu Vultur
and committed by
Paolo Abeni
d471793a
a0de636e
+233
-109
+233
-109
drivers/net/phy/micrel.c
+233
-109
drivers/net/phy/micrel.c
···
2790
2790
return ret;
2791
2791
}
2792
2792
2793
+
/**
2794
+
* LAN8814_PAGE_AFE_PMA - Selects Extended Page 1.
2795
+
*
2796
+
* This page appears to control the Analog Front-End (AFE) and Physical
2797
+
* Medium Attachment (PMA) layers. It is used to access registers like
2798
+
* LAN8814_PD_CONTROLS and LAN8814_LINK_QUALITY.
2799
+
*/
2800
+
#define LAN8814_PAGE_AFE_PMA 1
2801
+
2802
+
/**
2803
+
* LAN8814_PAGE_PCS_DIGITAL - Selects Extended Page 2.
2804
+
*
2805
+
* This page seems dedicated to the Physical Coding Sublayer (PCS) and other
2806
+
* digital logic. It is used for MDI-X alignment (LAN8814_ALIGN_SWAP) and EEE
2807
+
* state (LAN8814_EEE_STATE) in the LAN8814, and is repurposed for statistics
2808
+
* and self-test counters in the LAN8842.
2809
+
*/
2810
+
#define LAN8814_PAGE_PCS_DIGITAL 2
2811
+
2812
+
/**
2813
+
* LAN8814_PAGE_COMMON_REGS - Selects Extended Page 4.
2814
+
*
2815
+
* This page contains device-common registers that affect the entire chip.
2816
+
* It includes controls for chip-level resets, strap status, GPIO,
2817
+
* QSGMII, the shared 1588 PTP block, and the PVT monitor.
2818
+
*/
2819
+
#define LAN8814_PAGE_COMMON_REGS 4
2820
+
2821
+
/**
2822
+
* LAN8814_PAGE_PORT_REGS - Selects Extended Page 5.
2823
+
*
2824
+
* This page contains port-specific registers that must be accessed
2825
+
* on a per-port basis. It includes controls for port LEDs, QSGMII PCS,
2826
+
* rate adaptation FIFOs, and the per-port 1588 TSU block.
2827
+
*/
2828
+
#define LAN8814_PAGE_PORT_REGS 5
2829
+
2830
+
/**
2831
+
* LAN8814_PAGE_SYSTEM_CTRL - Selects Extended Page 31.
2832
+
*
2833
+
* This page appears to hold fundamental system or global controls. In the
2834
+
* driver, it is used by the related LAN8804 to access the
2835
+
* LAN8814_CLOCK_MANAGEMENT register.
2836
+
*/
2837
+
#define LAN8814_PAGE_SYSTEM_CTRL 31
2838
+
2793
2839
#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2794
2840
#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2795
2841
#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
···
2917
2871
PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2918
2872
PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2919
2873
2920
-
return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2874
+
return lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2875
+
PTP_TSU_INT_EN, val);
2921
2876
}
2922
2877
2923
2878
static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2924
2879
u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2925
2880
{
2926
-
*seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2881
+
*seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2882
+
PTP_RX_INGRESS_SEC_HI);
2927
2883
*seconds = (*seconds << 16) |
2928
-
lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2884
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2885
+
PTP_RX_INGRESS_SEC_LO);
2929
2886
2930
-
*nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2887
+
*nano_seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2888
+
PTP_RX_INGRESS_NS_HI);
2931
2889
*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2932
-
lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2890
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2891
+
PTP_RX_INGRESS_NS_LO);
2933
2892
2934
-
*seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2893
+
*seq_id = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2894
+
PTP_RX_MSG_HEADER2);
2935
2895
}
2936
2896
2937
2897
static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2938
2898
u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2939
2899
{
2940
-
*seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2900
+
*seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2901
+
PTP_TX_EGRESS_SEC_HI);
2941
2902
*seconds = *seconds << 16 |
2942
-
lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2903
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2904
+
PTP_TX_EGRESS_SEC_LO);
2943
2905
2944
-
*nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2906
+
*nano_seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2907
+
PTP_TX_EGRESS_NS_HI);
2945
2908
*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2946
-
lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2909
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2910
+
PTP_TX_EGRESS_NS_LO);
2947
2911
2948
-
*seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2912
+
*seq_id = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2913
+
PTP_TX_MSG_HEADER2);
2949
2914
}
2950
2915
2951
2916
static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *info)
···
2990
2933
int i;
2991
2934
2992
2935
for (i = 0; i < FIFO_SIZE; ++i)
2993
-
lanphy_read_page_reg(phydev, 5,
2936
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
2994
2937
egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2995
2938
2996
2939
/* Read to clear overflow status bit */
2997
-
lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2940
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_TSU_INT_STS);
2998
2941
}
2999
2942
3000
2943
static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
···
3044
2987
rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3045
2988
txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3046
2989
}
3047
-
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
3048
-
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2990
+
lanphy_write_page_reg(ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
2991
+
PTP_RX_PARSE_CONFIG, rxcfg);
2992
+
lanphy_write_page_reg(ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
2993
+
PTP_TX_PARSE_CONFIG, txcfg);
3049
2994
3050
2995
pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3051
2996
PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3052
-
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3053
-
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2997
+
lanphy_write_page_reg(ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
2998
+
PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2999
+
lanphy_write_page_reg(ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3000
+
PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3054
3001
3055
3002
if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
3056
-
lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
3003
+
lanphy_modify_page_reg(ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3004
+
PTP_TX_MOD,
3057
3005
PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3058
3006
PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
3059
3007
} else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
3060
-
lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
3008
+
lanphy_modify_page_reg(ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3009
+
PTP_TX_MOD,
3061
3010
PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3062
3011
0);
3063
3012
}
···
3187
3124
static void lan8814_ptp_clock_set(struct phy_device *phydev,
3188
3125
time64_t sec, u32 nsec)
3189
3126
{
3190
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
3191
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
3192
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
3193
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
3194
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
3127
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3128
+
PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
3129
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3130
+
PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
3131
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3132
+
PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
3133
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3134
+
PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
3135
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3136
+
PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
3195
3137
3196
-
lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
3138
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
3139
+
PTP_CMD_CTL_PTP_CLOCK_LOAD_);
3197
3140
}
3198
3141
3199
3142
static void lan8814_ptp_clock_get(struct phy_device *phydev,
3200
3143
time64_t *sec, u32 *nsec)
3201
3144
{
3202
-
lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
3145
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
3146
+
PTP_CMD_CTL_PTP_CLOCK_READ_);
3203
3147
3204
-
*sec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_HI);
3148
+
*sec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3149
+
PTP_CLOCK_READ_SEC_HI);
3205
3150
*sec <<= 16;
3206
-
*sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
3151
+
*sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3152
+
PTP_CLOCK_READ_SEC_MID);
3207
3153
*sec <<= 16;
3208
-
*sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
3154
+
*sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3155
+
PTP_CLOCK_READ_SEC_LO);
3209
3156
3210
-
*nsec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
3157
+
*nsec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3158
+
PTP_CLOCK_READ_NS_HI);
3211
3159
*nsec <<= 16;
3212
-
*nsec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
3160
+
*nsec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3161
+
PTP_CLOCK_READ_NS_LO);
3213
3162
}
3214
3163
3215
3164
static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
···
3260
3185
s64 start_sec, u32 start_nsec)
3261
3186
{
3262
3187
/* Set the start time */
3263
-
lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),
3188
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3189
+
LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),
3264
3190
lower_16_bits(start_sec));
3265
-
lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),
3191
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3192
+
LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),
3266
3193
upper_16_bits(start_sec));
3267
3194
3268
-
lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_LO(event),
3195
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3196
+
LAN8814_PTP_CLOCK_TARGET_NS_LO(event),
3269
3197
lower_16_bits(start_nsec));
3270
-
lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_HI(event),
3198
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3199
+
LAN8814_PTP_CLOCK_TARGET_NS_HI(event),
3271
3200
upper_16_bits(start_nsec) & 0x3fff);
3272
3201
}
3273
3202
···
3369
3290
adjustment_value_lo = adjustment_value & 0xffff;
3370
3291
adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3371
3292
3372
-
lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3293
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3294
+
PTP_LTC_STEP_ADJ_LO,
3373
3295
adjustment_value_lo);
3374
-
lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3296
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3297
+
PTP_LTC_STEP_ADJ_HI,
3375
3298
PTP_LTC_STEP_ADJ_DIR_ |
3376
3299
adjustment_value_hi);
3377
3300
seconds -= ((s32)adjustment_value);
···
3391
3310
adjustment_value_lo = adjustment_value & 0xffff;
3392
3311
adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3393
3312
3394
-
lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3313
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3314
+
PTP_LTC_STEP_ADJ_LO,
3395
3315
adjustment_value_lo);
3396
-
lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3316
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3317
+
PTP_LTC_STEP_ADJ_HI,
3397
3318
adjustment_value_hi);
3398
3319
seconds += ((s32)adjustment_value);
3399
3320
···
3403
3320
set_seconds += adjustment_value;
3404
3321
lan8814_ptp_update_target(phydev, set_seconds);
3405
3322
}
3406
-
lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
3407
-
PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
3323
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3324
+
PTP_CMD_CTL, PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
3408
3325
}
3409
3326
if (nano_seconds) {
3410
3327
u16 nano_seconds_lo;
···
3413
3330
nano_seconds_lo = nano_seconds & 0xffff;
3414
3331
nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
3415
3332
3416
-
lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3333
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3334
+
PTP_LTC_STEP_ADJ_LO,
3417
3335
nano_seconds_lo);
3418
-
lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3336
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3337
+
PTP_LTC_STEP_ADJ_HI,
3419
3338
PTP_LTC_STEP_ADJ_DIR_ |
3420
3339
nano_seconds_hi);
3421
-
lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
3340
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
3422
3341
PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
3423
3342
}
3424
3343
}
···
3462
3377
kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
3463
3378
3464
3379
mutex_lock(&shared->shared_lock);
3465
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
3466
-
lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
3380
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CLOCK_RATE_ADJ_HI,
3381
+
kszphy_rate_adj_hi);
3382
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CLOCK_RATE_ADJ_LO,
3383
+
kszphy_rate_adj_lo);
3467
3384
mutex_unlock(&shared->shared_lock);
3468
3385
3469
3386
return 0;
···
3474
3387
static void lan8814_ptp_set_reload(struct phy_device *phydev, int event,
3475
3388
s64 period_sec, u32 period_nsec)
3476
3389
{
3477
-
lanphy_write_page_reg(phydev, 4,
3390
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3478
3391
LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event),
3479
3392
lower_16_bits(period_sec));
3480
-
lanphy_write_page_reg(phydev, 4,
3393
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3481
3394
LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event),
3482
3395
upper_16_bits(period_sec));
3483
3396
3484
-
lanphy_write_page_reg(phydev, 4,
3397
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3485
3398
LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event),
3486
3399
lower_16_bits(period_nsec));
3487
-
lanphy_write_page_reg(phydev, 4,
3400
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3488
3401
LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event),
3489
3402
upper_16_bits(period_nsec) & 0x3fff);
3490
3403
}
···
3497
3410
* local time reaches or pass it
3498
3411
* Set the polarity high
3499
3412
*/
3500
-
lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG,
3413
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, LAN8814_PTP_GENERAL_CONFIG,
3501
3414
LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) |
3502
3415
LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) |
3503
3416
LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) |
···
3512
3425
lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0);
3513
3426
3514
3427
/* And then reload once it recheas the target */
3515
-
lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG,
3428
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, LAN8814_PTP_GENERAL_CONFIG,
3516
3429
LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event),
3517
3430
LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3518
3431
}
···
3523
3436
* 1: select as gpio,
3524
3437
* 0: select alt func
3525
3438
*/
3526
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin),
3439
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3440
+
LAN8814_GPIO_EN_ADDR(pin),
3527
3441
LAN8814_GPIO_EN_BIT(pin),
3528
3442
LAN8814_GPIO_EN_BIT(pin));
3529
3443
3530
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3444
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3445
+
LAN8814_GPIO_DIR_ADDR(pin),
3531
3446
LAN8814_GPIO_DIR_BIT(pin),
3532
3447
0);
3533
3448
3534
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin),
3449
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3450
+
LAN8814_GPIO_BUF_ADDR(pin),
3535
3451
LAN8814_GPIO_BUF_BIT(pin),
3536
3452
0);
3537
3453
}
···
3542
3452
static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)
3543
3453
{
3544
3454
/* Set as gpio output */
3545
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3455
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3456
+
LAN8814_GPIO_DIR_ADDR(pin),
3546
3457
LAN8814_GPIO_DIR_BIT(pin),
3547
3458
LAN8814_GPIO_DIR_BIT(pin));
3548
3459
3549
3460
/* Enable gpio 0:for alternate function, 1:gpio */
3550
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin),
3461
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3462
+
LAN8814_GPIO_EN_ADDR(pin),
3551
3463
LAN8814_GPIO_EN_BIT(pin),
3552
3464
0);
3553
3465
3554
3466
/* Set buffer type to push pull */
3555
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin),
3467
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3468
+
LAN8814_GPIO_BUF_ADDR(pin),
3556
3469
LAN8814_GPIO_BUF_BIT(pin),
3557
3470
LAN8814_GPIO_BUF_BIT(pin));
3558
3471
}
···
3673
3580
static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)
3674
3581
{
3675
3582
/* Set as gpio input */
3676
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3583
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3584
+
LAN8814_GPIO_DIR_ADDR(pin),
3677
3585
LAN8814_GPIO_DIR_BIT(pin),
3678
3586
0);
3679
3587
3680
3588
/* Map the pin to ltc pin 0 of the capture map registers */
3681
-
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO,
3682
-
pin,
3683
-
pin);
3589
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3590
+
PTP_GPIO_CAP_MAP_LO, pin, pin);
3684
3591
3685
3592
/* Enable capture on the edges of the ltc pin */
3686
3593
if (flags & PTP_RISING_EDGE)
3687
-
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN,
3594
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3595
+
PTP_GPIO_CAP_EN,
3688
3596
PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0),
3689
3597
PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0));
3690
3598
if (flags & PTP_FALLING_EDGE)
3691
-
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN,
3599
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3600
+
PTP_GPIO_CAP_EN,
3692
3601
PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0),
3693
3602
PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0));
3694
3603
3695
3604
/* Enable interrupt top interrupt */
3696
-
lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA,
3605
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_COMMON_INT_ENA,
3697
3606
PTP_COMMON_INT_ENA_GPIO_CAP_EN,
3698
3607
PTP_COMMON_INT_ENA_GPIO_CAP_EN);
3699
3608
}
···
3703
3608
static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)
3704
3609
{
3705
3610
/* Set as gpio out */
3706
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3611
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3612
+
LAN8814_GPIO_DIR_ADDR(pin),
3707
3613
LAN8814_GPIO_DIR_BIT(pin),
3708
3614
LAN8814_GPIO_DIR_BIT(pin));
3709
3615
3710
3616
/* Enable alternate, 0:for alternate function, 1:gpio */
3711
-
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin),
3617
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3618
+
LAN8814_GPIO_EN_ADDR(pin),
3712
3619
LAN8814_GPIO_EN_BIT(pin),
3713
3620
0);
3714
3621
3715
3622
/* Clear the mapping of pin to registers 0 of the capture registers */
3716
-
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO,
3623
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3624
+
PTP_GPIO_CAP_MAP_LO,
3717
3625
GENMASK(3, 0),
3718
3626
0);
3719
3627
3720
3628
/* Disable capture on both of the edges */
3721
-
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN,
3629
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_GPIO_CAP_EN,
3722
3630
PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
3723
3631
PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
3724
3632
0);
3725
3633
3726
3634
/* Disable interrupt top interrupt */
3727
-
lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA,
3635
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_COMMON_INT_ENA,
3728
3636
PTP_COMMON_INT_ENA_GPIO_CAP_EN,
3729
3637
0);
3730
3638
}
···
3859
3761
/* If other timestamps are available in the FIFO,
3860
3762
* process them.
3861
3763
*/
3862
-
reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3764
+
reg = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3765
+
PTP_CAP_INFO);
3863
3766
} while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
3864
3767
}
3865
3768
···
3933
3834
/* If other timestamps are available in the FIFO,
3934
3835
* process them.
3935
3836
*/
3936
-
reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3837
+
reg = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3838
+
PTP_CAP_INFO);
3937
3839
} while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
3938
3840
}
3939
3841
···
3971
3871
/* This is 0 because whatever was the input pin it was mapped it to
3972
3872
* ltc gpio pin 0
3973
3873
*/
3974
-
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_SEL,
3874
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_GPIO_SEL,
3975
3875
PTP_GPIO_SEL_GPIO_SEL(0),
3976
3876
PTP_GPIO_SEL_GPIO_SEL(0));
3977
3877
3978
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS);
3878
+
tmp = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3879
+
PTP_GPIO_CAP_STS);
3979
3880
if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&
3980
3881
!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0)))
3981
3882
return -1;
3982
3883
3983
3884
if (tmp & BIT(0)) {
3984
-
sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_HI_CAP);
3885
+
sec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3886
+
PTP_GPIO_RE_LTC_SEC_HI_CAP);
3985
3887
sec <<= 16;
3986
-
sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_LO_CAP);
3888
+
sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3889
+
PTP_GPIO_RE_LTC_SEC_LO_CAP);
3987
3890
3988
-
nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3891
+
nsec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3892
+
PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3989
3893
nsec <<= 16;
3990
-
nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3894
+
nsec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3895
+
PTP_GPIO_RE_LTC_NS_LO_CAP);
3991
3896
} else {
3992
-
sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_HI_CAP);
3897
+
sec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3898
+
PTP_GPIO_FE_LTC_SEC_HI_CAP);
3993
3899
sec <<= 16;
3994
-
sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_LO_CAP);
3900
+
sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3901
+
PTP_GPIO_FE_LTC_SEC_LO_CAP);
3995
3902
3996
-
nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3903
+
nsec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3904
+
PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3997
3905
nsec <<= 16;
3998
-
nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3906
+
nsec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3907
+
PTP_GPIO_RE_LTC_NS_LO_CAP);
3999
3908
}
4000
3909
4001
3910
ptp_event.index = 0;
···
4030
3921
static int lan8804_config_init(struct phy_device *phydev)
4031
3922
{
4032
3923
/* MDI-X setting for swap A,B transmit */
4033
-
lanphy_modify_page_reg(phydev, 2, LAN8804_ALIGN_SWAP,
3924
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL, LAN8804_ALIGN_SWAP,
4034
3925
LAN8804_ALIGN_TX_A_B_SWAP_MASK,
4035
3926
LAN8804_ALIGN_TX_A_B_SWAP);
4036
3927
4037
3928
/* Make sure that the PHY will not stop generating the clock when the
4038
3929
* link partner goes down
4039
3930
*/
4040
-
lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
4041
-
lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3931
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_SYSTEM_CTRL,
3932
+
LAN8814_CLOCK_MANAGEMENT, 0x27e);
3933
+
lanphy_read_page_reg(phydev, LAN8814_PAGE_AFE_PMA, LAN8814_LINK_QUALITY);
4042
3934
4043
3935
return 0;
4044
3936
}
···
4121
4011
}
4122
4012
4123
4013
while (true) {
4124
-
irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
4014
+
irq_status = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4015
+
PTP_TSU_INT_STS);
4125
4016
if (!irq_status)
4126
4017
break;
4127
4018
···
4150
4039
{
4151
4040
int err;
4152
4041
4153
-
lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
4042
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, LAN8814_INTR_CTRL_REG,
4154
4043
LAN8814_INTR_CTRL_REG_POLARITY |
4155
4044
LAN8814_INTR_CTRL_REG_INTR_ENABLE);
4156
4045
···
4181
4070
!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4182
4071
return;
4183
4072
4184
-
lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
4073
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4074
+
TSU_HARD_RESET, TSU_HARD_RESET_);
4185
4075
4186
-
lanphy_modify_page_reg(phydev, 5, PTP_TX_MOD,
4076
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_TX_MOD,
4187
4077
PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_,
4188
4078
PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_);
4189
4079
4190
-
lanphy_modify_page_reg(phydev, 5, PTP_RX_MOD,
4080
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_RX_MOD,
4191
4081
PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_,
4192
4082
PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_);
4193
4083
4194
-
lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
4195
-
lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
4084
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4085
+
PTP_RX_PARSE_CONFIG, 0);
4086
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4087
+
PTP_TX_PARSE_CONFIG, 0);
4196
4088
4197
4089
/* Removing default registers configs related to L2 and IP */
4198
-
lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
4199
-
lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
4200
-
lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
4201
-
lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
4090
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4091
+
PTP_TX_PARSE_L2_ADDR_EN, 0);
4092
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4093
+
PTP_RX_PARSE_L2_ADDR_EN, 0);
4094
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4095
+
PTP_TX_PARSE_IP_ADDR_EN, 0);
4096
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4097
+
PTP_RX_PARSE_IP_ADDR_EN, 0);
4202
4098
4203
4099
/* Disable checking for minorVersionPTP field */
4204
-
lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
4100
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_RX_VERSION,
4205
4101
PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
4206
-
lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
4102
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_TX_VERSION,
4207
4103
PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
4208
4104
4209
4105
skb_queue_head_init(&ptp_priv->tx_queue);
···
4295
4177
/* The EP.4 is shared between all the PHYs in the package and also it
4296
4178
* can be accessed by any of the PHYs
4297
4179
*/
4298
-
lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
4299
-
lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
4180
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4181
+
LTC_HARD_RESET, LTC_HARD_RESET_);
4182
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_OPERATING_MODE,
4300
4183
PTP_OPERATING_MODE_STANDALONE_);
4301
4184
4302
4185
/* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */
4303
-
lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_ENABLE_);
4186
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
4187
+
PTP_CMD_CTL_PTP_ENABLE_);
4304
4188
4305
4189
return 0;
4306
4190
}
···
4311
4191
{
4312
4192
int temp;
4313
4193
4314
-
temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
4194
+
temp = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4195
+
LAN8814_LED_CTRL_1);
4315
4196
4316
4197
if (val)
4317
4198
temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
4318
4199
else
4319
4200
temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
4320
4201
4321
-
lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
4202
+
lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4203
+
LAN8814_LED_CTRL_1, temp);
4322
4204
}
4323
4205
4324
4206
static int lan8814_config_init(struct phy_device *phydev)
···
4328
4206
struct kszphy_priv *lan8814 = phydev->priv;
4329
4207
4330
4208
/* Reset the PHY */
4331
-
lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET,
4209
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4210
+
LAN8814_QSGMII_SOFT_RESET,
4332
4211
LAN8814_QSGMII_SOFT_RESET_BIT,
4333
4212
LAN8814_QSGMII_SOFT_RESET_BIT);
4334
4213
4335
4214
/* Disable ANEG with QSGMII PCS Host side */
4336
-
lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_PCS1G_ANEG_CONFIG,
4215
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4216
+
LAN8814_QSGMII_PCS1G_ANEG_CONFIG,
4337
4217
LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA,
4338
4218
0);
4339
4219
4340
4220
/* MDI-X setting for swap A,B transmit */
4341
-
lanphy_modify_page_reg(phydev, 2, LAN8814_ALIGN_SWAP,
4221
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL, LAN8814_ALIGN_SWAP,
4342
4222
LAN8814_ALIGN_TX_A_B_SWAP_MASK,
4343
4223
LAN8814_ALIGN_TX_A_B_SWAP);
4344
4224
···
4377
4253
* cable is removed then the LED was still one even though there is no
4378
4254
* link
4379
4255
*/
4380
-
lanphy_modify_page_reg(phydev, 2, LAN8814_EEE_STATE,
4256
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL, LAN8814_EEE_STATE,
4381
4257
LAN8814_EEE_STATE_MASK2P5P,
4382
4258
0);
4383
4259
}
···
4388
4264
* longer than 100m to be used. This configuration can be used
4389
4265
* regardless of the mode of operation of the PHY
4390
4266
*/
4391
-
lanphy_modify_page_reg(phydev, 1, LAN8814_PD_CONTROLS,
4267
+
lanphy_modify_page_reg(phydev, LAN8814_PAGE_AFE_PMA, LAN8814_PD_CONTROLS,
4392
4268
LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK,
4393
4269
LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL);
4394
4270
}
···
4413
4289
/* Strap-in value for PHY address, below register read gives starting
4414
4290
* phy address value
4415
4291
*/
4416
-
addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
4292
+
addr = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, 0) & 0x1F;
4417
4293
devm_phy_package_join(&phydev->mdio.dev, phydev,
4418
4294
addr, sizeof(struct lan8814_shared_priv));
4419
4295