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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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os
linux
Merge tag 'mvebu-dt64-6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
mvebu dt64 for 6.20 (part 1)
Add support for Armada 7020 Express Type 7 CPU module board by Marvell, including:
- COM Express CPU module and carrier board (Marvell DB-98CX85x0)
- DDR4 memory, 1Gbit OOB Ethernet, 10G KR Ethernet, NAND/SPI flash, PCIe, SATA, USB, and UART interfaces
Add SoC-specific compatibles for SafeXcel crypto engine on Armada 37xx and CP11x
Fix regulator type from "regulator-gpio" to "regulator-fixed" where no GPIO control is present
Add missing GPIO properties for "nxp,pca9536" on cn9131-cf-solidwan
Fix and clean up pinctrl-names properties and typos
Add missing "#phy-cells" to "usb-nop-xceiv" nodes
MAINTAINERS: Add Falcon DB to the list of maintained Marvell Armada dts files
* tag 'mvebu-dt64-6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
arm64: dts: marvell: Add SoC specific compatibles to SafeXcel crypto
arm64: dts: marvell: change regulator-gpio to regulator-fixed
arm64: dts: marvell: cn9131-cf-solidwan: Add missing GPIO properties on "nxp,pca9536"
arm64: dts: marvell: Fix stray and typo "pinctrl-names" properties
arm64: dts: marvell: Add missing "#phy-cells" to "usb-nop-xceiv"
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+243
-18
+1
MAINTAINERS
+1
MAINTAINERS
···
2943
2943
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
2944
2944
F: Documentation/devicetree/bindings/arm/marvell/
2945
2945
F: arch/arm/boot/dts/marvell/armada*
2946
+
F: arch/arm/boot/dts/marvell/db-falcon*
2946
2947
F: arch/arm/boot/dts/marvell/kirkwood*
2947
2948
F: arch/arm/configs/mvebu_*_defconfig
2948
2949
F: arch/arm/mach-mvebu/
+1
arch/arm64/boot/dts/marvell/Makefile
+1
arch/arm64/boot/dts/marvell/Makefile
···
11
11
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb
12
12
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
13
13
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
14
+
dtb-$(CONFIG_ARCH_MVEBU) += db-falcon-carrier-a7k.dtb
14
15
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
15
16
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-mochabin.dtb
16
17
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
+1
arch/arm64/boot/dts/marvell/armada-3720-db.dts
+1
arch/arm64/boot/dts/marvell/armada-3720-db.dts
+1
-1
arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
+1
-1
arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
+2
-7
arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
+2
-7
arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
···
26
26
};
27
27
28
28
vcc_sd_reg1: regulator {
29
-
compatible = "regulator-gpio";
29
+
compatible = "regulator-fixed";
30
30
regulator-name = "vcc_sd1";
31
-
regulator-min-microvolt = <1800000>;
31
+
regulator-min-microvolt = <3300000>;
32
32
regulator-max-microvolt = <3300000>;
33
33
regulator-boot-on;
34
-
35
-
gpios-states = <0>;
36
-
states = <1800000 0x1
37
-
3300000 0x0>;
38
-
enable-active-high;
39
34
};
40
35
41
36
keys {
+2
-1
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+2
-1
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
···
427
427
};
428
428
429
429
crypto: crypto@90000 {
430
-
compatible = "inside-secure,safexcel-eip97ies";
430
+
compatible = "marvell,armada-3700-crypto",
431
+
"inside-secure,safexcel-eip97ies";
431
432
reg = <0x90000 0x20000>;
432
433
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
433
434
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+161
arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
+161
arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (C) 2023 Marvell Technology Group Ltd.
4
+
*
5
+
* Device Tree file for Marvell Armada 7020 Com Express CPU module board.
6
+
*/
7
+
8
+
#include "armada-7020.dtsi"
9
+
10
+
/ {
11
+
model = "Marvell Armada-7020 COMEXPRESS board setup";
12
+
compatible = "marvell,armada7020-cpu-module", "marvell,armada7020",
13
+
"marvell,armada-ap806-dual", "marvell,armada-ap806";
14
+
15
+
memory@0 {
16
+
device_type = "memory";
17
+
reg = <0x0 0x0 0x2 0x00000000>;
18
+
};
19
+
20
+
chosen {
21
+
stdout-path = "serial0:115200n8";
22
+
};
23
+
24
+
aliases {
25
+
ethernet0 = &cp0_eth0;
26
+
ethernet1 = &cp0_eth1;
27
+
};
28
+
};
29
+
30
+
&ap_clk {
31
+
status = "okay";
32
+
};
33
+
34
+
&gic {
35
+
status = "okay";
36
+
};
37
+
38
+
&i2c0 {
39
+
status = "okay";
40
+
clock-frequency = <100000>;
41
+
};
42
+
43
+
&spi0 {
44
+
status = "okay";
45
+
};
46
+
47
+
&uart0 {
48
+
status = "okay";
49
+
};
50
+
51
+
&cp0_mdio {
52
+
status = "okay";
53
+
54
+
phy0: ethernet-phy@10 {
55
+
reg = <0x10>;
56
+
};
57
+
};
58
+
59
+
&cp0_ethernet {
60
+
status = "okay";
61
+
};
62
+
63
+
&cp0_eth0 {
64
+
status = "okay";
65
+
phy-mode = "10gbase-r";
66
+
managed = "in-band-status";
67
+
/* Generic PHY, providing serdes lanes */
68
+
phys = <&cp0_comphy4 0>;
69
+
};
70
+
71
+
&cp0_eth1 {
72
+
status = "okay";
73
+
phy = <&phy0>;
74
+
phy-mode = "rgmii-id";
75
+
};
76
+
77
+
&cp0_usb3_0 {
78
+
status = "okay";
79
+
};
80
+
81
+
&cp0_usb3_1 {
82
+
status = "okay";
83
+
};
84
+
85
+
&cp0_clk {
86
+
status = "okay";
87
+
};
88
+
89
+
&cp0_i2c0 {
90
+
status = "okay";
91
+
clock-frequency = <100000>;
92
+
};
93
+
94
+
&cp0_nand_controller {
95
+
status = "okay";
96
+
97
+
nand@0 {
98
+
reg = <0>;
99
+
label = "main-storage";
100
+
nand-rb = <0>;
101
+
nand-ecc-mode = "hw";
102
+
nand-on-flash-bbt;
103
+
nand-ecc-strength = <8>;
104
+
nand-ecc-step-size = <512>;
105
+
106
+
partitions {
107
+
compatible = "fixed-partitions";
108
+
#address-cells = <1>;
109
+
#size-cells = <1>;
110
+
111
+
partition@0 {
112
+
label = "U-Boot";
113
+
reg = <0 0x400000>;
114
+
};
115
+
partition@200000 {
116
+
label = "Linux";
117
+
reg = <0x400000 0x100000>;
118
+
};
119
+
partition@1000000 {
120
+
label = "Filesystem";
121
+
reg = <0x500000 0x1e00000>;
122
+
};
123
+
};
124
+
};
125
+
};
126
+
127
+
&cp0_pcie0 {
128
+
status = "okay";
129
+
num-lanes = <4>;
130
+
num-viewport = <8>;
131
+
132
+
ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000
133
+
0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>;
134
+
135
+
/* Generic PHY, providing serdes lanes */
136
+
phys = <&cp0_comphy0 0
137
+
&cp0_comphy1 0
138
+
&cp0_comphy2 0
139
+
&cp0_comphy3 0>;
140
+
};
141
+
142
+
&cp0_sata0 {
143
+
/* CPM Lane 0 - U29 */
144
+
status = "okay";
145
+
146
+
sata-port@1 {
147
+
status = "okay";
148
+
/* Generic PHY, providing serdes lanes */
149
+
phys = <&cp0_comphy5 1>;
150
+
};
151
+
};
152
+
153
+
&cp0_sdhci0 {
154
+
pinctrl-names = "default";
155
+
pinctrl-0 = <&sdhci_pins>;
156
+
status = "okay";
157
+
bus-width = <4>;
158
+
no-1-8-v;
159
+
broken-cd;
160
+
};
161
+
+7
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+7
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
···
47
47
cp0_pinctrl: pinctrl {
48
48
compatible = "marvell,armada-7k-pinctrl";
49
49
50
+
51
+
sdhci_pins: sdhci-pins {
52
+
marvell,pins = "mpp56", "mpp57", "mpp58",
53
+
"mpp59", "mpp60", "mpp61", "mpp62";
54
+
marvell,function = "sdio";
55
+
};
56
+
50
57
nand_pins: nand-pins {
51
58
marvell,pins =
52
59
"mpp15", "mpp16", "mpp17", "mpp18",
+2
arch/arm64/boot/dts/marvell/armada-8040-db.dts
+2
arch/arm64/boot/dts/marvell/armada-8040-db.dts
···
51
51
52
52
cp0_usb3_0_phy: cp0-usb3-0-phy {
53
53
compatible = "usb-nop-xceiv";
54
+
#phy-cells = <0>;
54
55
vcc-supply = <&cp0_reg_usb3_0_vbus>;
55
56
};
56
57
···
66
65
67
66
cp1_usb3_0_phy: cp1-usb3-0-phy {
68
67
compatible = "usb-nop-xceiv";
68
+
#phy-cells = <0>;
69
69
vcc-supply = <&cp1_reg_usb3_0_vbus>;
70
70
};
71
71
};
+2
-2
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+2
-2
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+2
-1
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+2
-1
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
···
512
512
};
513
513
514
514
CP11X_LABEL(crypto): crypto@800000 {
515
-
compatible = "inside-secure,safexcel-eip197b";
515
+
compatible = "marvell,armada-cp110-crypto",
516
+
"inside-secure,safexcel-eip197b";
516
517
reg = <0x800000 0x200000>;
517
518
interrupts = <88 IRQ_TYPE_LEVEL_HIGH>,
518
519
<89 IRQ_TYPE_LEVEL_HIGH>,
+1
-1
arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
+1
-1
arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
+2
-1
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+2
-1
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
···
47
47
48
48
cp0_usb3_0_phy0: usb-phy-1 {
49
49
compatible = "usb-nop-xceiv";
50
+
#phy-cells = <0>;
50
51
};
51
52
52
53
cp0_usb3_0_phy1: usb-phy-2 {
53
54
compatible = "usb-nop-xceiv";
55
+
#phy-cells = <0>;
54
56
vcc-supply = <&cp0_reg_usb3_vbus1>;
55
57
};
56
58
···
93
91
94
92
/* on-board eMMC U6 */
95
93
&ap_sdhci0 {
96
-
pinctrl-names = "default";
97
94
bus-width = <8>;
98
95
status = "okay";
99
96
mmc-ddr-1_8v;
+2
-2
arch/arm64/boot/dts/marvell/cn9130-db.dtsi
+2
-2
arch/arm64/boot/dts/marvell/cn9130-db.dtsi
···
50
50
51
51
cp0_usb3_0_phy0: usb-phy-1 {
52
52
compatible = "usb-nop-xceiv";
53
+
#phy-cells = <0>;
53
54
vcc-supply = <&cp0_reg_usb3_vbus0>;
54
55
};
55
56
···
65
64
66
65
cp0_usb3_0_phy1: usb-phy-2 {
67
66
compatible = "usb-nop-xceiv";
67
+
#phy-cells = <0>;
68
68
vcc-supply = <&cp0_reg_usb3_vbus1>;
69
69
};
70
70
···
111
109
112
110
/* on-board eMMC - U9 */
113
111
&ap_sdhci0 {
114
-
pinctrl-names = "default";
115
112
bus-width = <8>;
116
113
vqmmc-supply = <&ap0_reg_sd_vccq>;
117
114
status = "okay";
···
165
164
/* U36 */
166
165
expander0: pca953x@21 {
167
166
compatible = "nxp,pca9555";
168
-
pinctrl-names = "default";
169
167
gpio-controller;
170
168
#gpio-cells = <2>;
171
169
reg = <0x21>;
+2
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
+2
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
+2
-1
arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
+2
-1
arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
+1
arch/arm64/boot/dts/marvell/cn9131-db.dtsi
+1
arch/arm64/boot/dts/marvell/cn9131-db.dtsi
+2
-1
arch/arm64/boot/dts/marvell/cn9132-db.dtsi
+2
-1
arch/arm64/boot/dts/marvell/cn9132-db.dtsi
···
28
28
29
29
cp2_usb3_0_phy0: usb-phy-4 {
30
30
compatible = "usb-nop-xceiv";
31
+
#phy-cells = <0>;
31
32
vcc-supply = <&cp2_reg_usb3_vbus0>;
32
33
};
33
34
···
43
42
44
43
cp2_usb3_0_phy1: usb-phy-5 {
45
44
compatible = "usb-nop-xceiv";
45
+
#phy-cells = <0>;
46
46
vcc-supply = <&cp2_reg_usb3_vbus1>;
47
47
};
48
48
···
142
140
/* U12 */
143
141
cp2_module_expander1: pca9555@21 {
144
142
compatible = "nxp,pca9555";
145
-
pinctrl-names = "default";
146
143
gpio-controller;
147
144
#gpio-cells = <2>;
148
145
reg = <0x21>;
+27
arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts
+27
arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (C) 2023 Marvell International Ltd.
4
+
*
5
+
* Device tree for the Falcon DB Type 7 Com Express carrier board,
6
+
* Utilizing the Armada 7020 COM Express CPU module board.
7
+
* This specific carrier board (DB-98CX8540/80)
8
+
* only maintains a PCIe link with the CPU module,
9
+
* which does not require any special DTS definitions.
10
+
*
11
+
* There is no Linux CPU booting in this mode on the carrier, only on the
12
+
* Armada 7020 COM Express CPU module.
13
+
* What runs the Linux is the Armada 7020 on the COM Express CPU module,
14
+
* And it accesses the switch end-point on the Falcon DB portion of the carrier
15
+
* via PCIe.
16
+
*/
17
+
18
+
#include "armada-7020-comexpress.dtsi"
19
+
#include "db-falcon-carrier.dtsi"
20
+
21
+
/ {
22
+
model = "Marvell Falcon DB COM EXPRESS type 7 carrier board with Armada 7020 CPU module";
23
+
compatible = "marvell,armada7020-falcon-carrier", "marvell,db-falcon-carrier",
24
+
"marvell,armada7020-cpu-module", "marvell,armada7020",
25
+
"marvell,armada-ap806-dual", "marvell,armada-ap806";
26
+
27
+
};
+22
arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi
+22
arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (C) 2023 Marvell International Ltd.
4
+
*
5
+
* Device tree for the Falcon DB Type 7 Com Express carrier board,
6
+
* This (DB-98CX8540/80) specific carrier board only maintains
7
+
* a PCIe link with the COM Express CPU module, which does not
8
+
* require any special DTS definitions.
9
+
*
10
+
* The board contains the 98CX8540/80 Switch, which connects by
11
+
* PCIe to the COM Express CPU module.
12
+
* This CPU module can be any standard COM Express CPU module with
13
+
* PCIe support.
14
+
*
15
+
* There is no Linux CPU booting in this mode on the carrier,
16
+
* only on the COM Express CPU module.
17
+
*/
18
+
19
+
/ {
20
+
model = "Marvell Armada Falcon DB COM EXPRESS type 7 carrier board";
21
+
compatible = "marvell,db-falcon-carrier";
22
+
};