Merge tag 'mediatek-drm-next-20260117' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next

+27 -2

Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

··· 26 26 - enum: 27 27 - mediatek,mt7623-hdmi-phy 28 28 - const: mediatek,mt2701-hdmi-phy 29 + - items: 30 + - enum: 31 + - mediatek,mt8188-hdmi-phy 32 + - const: mediatek,mt8195-hdmi-phy 29 33 - const: mediatek,mt2701-hdmi-phy 30 34 - const: mediatek,mt8173-hdmi-phy 31 35 - const: mediatek,mt8195-hdmi-phy ··· 38 34 maxItems: 1 39 35 40 36 clocks: 37 + minItems: 1 41 38 items: 42 39 - description: PLL reference clock 40 + - description: HDMI 26MHz clock 41 + - description: HDMI PLL1 clock 42 + - description: HDMI PLL2 clock 43 43 44 44 clock-names: 45 + minItems: 1 45 46 items: 46 47 - const: pll_ref 48 + - const: 26m 49 + - const: pll1 50 + - const: pll2 47 51 48 52 clock-output-names: 49 - items: 50 - - const: hdmitx_dig_cts 53 + maxItems: 1 51 54 52 55 "#phy-cells": 53 56 const: 0 ··· 86 75 - clock-output-names 87 76 - "#phy-cells" 88 77 - "#clock-cells" 78 + 79 + allOf: 80 + - if: 81 + not: 82 + properties: 83 + compatible: 84 + contains: 85 + const: mediatek,mt8195-hdmi-phy 86 + then: 87 + properties: 88 + clocks: 89 + maxItems: 1 90 + clock-names: 91 + maxItems: 1 89 92 90 93 additionalProperties: false 91 94

+15 -9

drivers/gpu/drm/mediatek/mtk_crtc.c

··· 225 225 226 226 static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc) 227 227 { 228 + struct drm_device *dev = mtk_crtc->base.dev; 228 229 int ret; 229 230 int i; 230 231 231 232 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 232 233 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); 233 234 if (ret) { 234 - DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 235 + drm_err(dev, "Failed to enable clock %d: %d\n", i, ret); 235 236 goto err; 236 237 } 237 238 } ··· 344 343 struct drm_connector *connector; 345 344 struct drm_encoder *encoder; 346 345 struct drm_connector_list_iter conn_iter; 346 + struct drm_device *dev = mtk_crtc->base.dev; 347 347 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 348 348 int ret; 349 349 int i; ··· 373 371 374 372 ret = pm_runtime_resume_and_get(crtc->dev->dev); 375 373 if (ret < 0) { 376 - DRM_ERROR("Failed to enable power domain: %d\n", ret); 374 + drm_err(dev, "Failed to enable power domain: %d\n", ret); 377 375 return ret; 378 376 } 379 377 380 378 ret = mtk_mutex_prepare(mtk_crtc->mutex); 381 379 if (ret < 0) { 382 - DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 380 + drm_err(dev, "Failed to enable mutex clock: %d\n", ret); 383 381 goto err_pm_runtime_put; 384 382 } 385 383 386 384 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 387 385 if (ret < 0) { 388 - DRM_ERROR("Failed to enable component clocks: %d\n", ret); 386 + drm_err(dev, "Failed to enable component clocks: %d\n", ret); 389 387 goto err_mutex_unprepare; 390 388 } 391 389 ··· 650 648 struct mtk_drm_private *priv = crtc->dev->dev_private; 651 649 652 650 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 651 + struct drm_device *dev = mtk_crtc->base.dev; 653 652 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan) 654 653 mtk_crtc_ddp_config(crtc, NULL); 655 654 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0) 656 - DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n", 657 - drm_crtc_index(&mtk_crtc->base)); 655 + drm_err(dev, "mtk_crtc %d CMDQ execute command timeout!\n", 656 + drm_crtc_index(&mtk_crtc->base)); 658 657 #else 659 658 if (!priv->data->shadow_register) 660 659 mtk_crtc_ddp_config(crtc, NULL); ··· 779 776 { 780 777 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); 781 778 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 779 + struct drm_device *dev = mtk_crtc->base.dev; 782 780 int ret; 783 781 784 - DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 782 + drm_dbg_driver(dev, "%s %d\n", __func__, crtc->base.id); 785 783 786 784 ret = mtk_ddp_comp_power_on(comp); 787 785 if (ret < 0) { ··· 807 803 { 808 804 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); 809 805 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 806 + struct drm_device *dev = mtk_crtc->base.dev; 810 807 int i; 811 808 812 - DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 809 + drm_dbg_driver(dev, "%s %d\n", __func__, crtc->base.id); 813 810 if (!mtk_crtc->enabled) 814 811 return; 815 812 ··· 850 845 crtc); 851 846 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state); 852 847 struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); 848 + struct drm_device *dev = mtk_crtc->base.dev; 853 849 unsigned long flags; 854 850 855 851 if (mtk_crtc->event && mtk_crtc_state->base.event) 856 - DRM_ERROR("new event while there is still a pending event\n"); 852 + drm_err(dev, "new event while there is still a pending event\n"); 857 853 858 854 if (mtk_crtc_state->base.event) { 859 855 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);

+38 -19

drivers/gpu/drm/mediatek/mtk_dp.c

··· 1976 1976 struct mtk_dp *mtk_dp = dev; 1977 1977 unsigned long flags; 1978 1978 u32 status; 1979 + int ret; 1979 1980 1980 1981 if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in) 1981 1982 msleep(100); ··· 1995 1994 memset(&mtk_dp->info.audio_cur_cfg, 0, 1996 1995 sizeof(mtk_dp->info.audio_cur_cfg)); 1997 1996 1997 + mtk_dp->enabled = false; 1998 + /* power off aux */ 1999 + mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, 2000 + DP_PWR_STATE_BANDGAP_TPLL, 2001 + DP_PWR_STATE_MASK); 2002 + 1998 2003 mtk_dp->need_debounce = false; 1999 2004 mod_timer(&mtk_dp->debounce_timer, 2000 2005 jiffies + msecs_to_jiffies(100) - 1); 2006 + } else { 2007 + mtk_dp_aux_panel_poweron(mtk_dp, true); 2008 + 2009 + ret = mtk_dp_parse_capabilities(mtk_dp); 2010 + if (ret) 2011 + drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); 2012 + 2013 + /* Training */ 2014 + ret = mtk_dp_training(mtk_dp); 2015 + if (ret) 2016 + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); 2017 + 2018 + mtk_dp->enabled = true; 2001 2019 } 2002 2020 } 2003 2021 ··· 2188 2168 * Parse capability here to let atomic_get_input_bus_fmts and 2189 2169 * mode_valid use the capability to calculate sink bitrates. 2190 2170 */ 2191 - if (mtk_dp_parse_capabilities(mtk_dp)) { 2171 + if (mtk_dp->bridge.type == DRM_MODE_CONNECTOR_eDP && 2172 + mtk_dp_parse_capabilities(mtk_dp)) { 2192 2173 drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n"); 2193 2174 drm_edid_free(drm_edid); 2194 2175 drm_edid = NULL; ··· 2387 2366 return; 2388 2367 } 2389 2368 2390 - mtk_dp_aux_panel_poweron(mtk_dp, true); 2369 + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) { 2370 + mtk_dp_aux_panel_poweron(mtk_dp, true); 2391 2371 2392 - /* Training */ 2393 - ret = mtk_dp_training(mtk_dp); 2394 - if (ret) { 2395 - drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); 2396 - goto power_off_aux; 2372 + /* Training */ 2373 + ret = mtk_dp_training(mtk_dp); 2374 + if (ret) { 2375 + drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret); 2376 + goto power_off_aux; 2377 + } 2397 2378 } 2398 2379 2399 2380 ret = mtk_dp_video_config(mtk_dp); ··· 2415 2392 sizeof(mtk_dp->info.audio_cur_cfg)); 2416 2393 } 2417 2394 2418 - mtk_dp->enabled = true; 2395 + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) 2396 + mtk_dp->enabled = true; 2397 + 2419 2398 mtk_dp_update_plugged_status(mtk_dp); 2420 2399 2421 2400 return; ··· 2432 2407 { 2433 2408 struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); 2434 2409 2435 - mtk_dp->enabled = false; 2410 + if (mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) { 2411 + mtk_dp->enabled = false; 2412 + mtk_dp_aux_panel_poweron(mtk_dp, false); 2413 + } 2414 + 2436 2415 mtk_dp_update_plugged_status(mtk_dp); 2437 2416 mtk_dp_video_enable(mtk_dp, false); 2438 2417 mtk_dp_audio_mute(mtk_dp, true); 2439 - 2440 - if (mtk_dp->train_info.cable_plugged_in) { 2441 - drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); 2442 - usleep_range(2000, 3000); 2443 - } 2444 - 2445 - /* power off aux */ 2446 - mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, 2447 - DP_PWR_STATE_BANDGAP_TPLL, 2448 - DP_PWR_STATE_MASK); 2449 2418 2450 2419 /* SDP path reset sw*/ 2451 2420 mtk_dp_sdp_path_reset(mtk_dp);

+4

drivers/gpu/drm/mediatek/mtk_dsi.c

··· 152 152 #define SHORT_PACKET 0 153 153 #define LONG_PACKET 2 154 154 #define BTA BIT(2) 155 + #define HSTX BIT(3) 155 156 #define DATA_ID GENMASK(15, 8) 156 157 #define DATA_0 GENMASK(23, 16) 157 158 #define DATA_1 GENMASK(31, 24) ··· 1080 1079 config = BTA; 1081 1080 else 1082 1081 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET; 1082 + 1083 + if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 1084 + config |= HSTX; 1083 1085 1084 1086 if (msg->tx_len > 2) { 1085 1087 cmdq_size = 1 + (msg->tx_len + 3) / 4;

+3 -3

drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

··· 746 746 case HDMI_COLORSPACE_YUV420: 747 747 mtk_hdmi_yuv420_downsampling(hdmi, true); 748 748 break; 749 - }; 749 + } 750 750 } 751 751 752 752 static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi, ··· 1157 1157 case HDMI_INFOFRAME_TYPE_DRM: 1158 1158 default: 1159 1159 break; 1160 - }; 1160 + } 1161 1161 1162 1162 return 0; 1163 1163 } ··· 1185 1185 default: 1186 1186 dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type); 1187 1187 break; 1188 - }; 1188 + } 1189 1189 1190 1190 return 0; 1191 1191 }

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