Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rproc-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull remoteproc updates from Bjorn Andersson:
- Move requesting of IRQs in TI Keystone driver to probe time instead
of remoteproc start, to allow better handling of errors.
- Introduce support for more than 10 entries in the Qualcomm minidump
implementation.
- Add audio DSP remoteproc support for the Qualcomm Eliza platform. Add
modem remoteproc support for the Qualcomm MDM9607, MSM8917, MSM8937,
and MSM8940 platforms.
- Add list of Qualcomm QMI service ids to the QMI header file, in order
to avoid sprinkling them across the various drivers using them.
Migrate sysmon to use this constant.
- Fix several issues related to DeviceTree parsing and mailbox handling
in the Xilinx R5F remote processor driver.
- Fix incorrect error checks in reserved memory handling and polish the
code across i.MX and TI drivers.
* tag 'rproc-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (35 commits)
remoteproc: qcom: pas: Add Eliza ADSP support
dt-bindings: remoteproc: qcom,milos-pas: Document Eliza ADSP
remoteproc: qcom: Add missing space before closing bracket
dt-bindings: remoteproc: qcom: Drop types for firmware-name
remoteproc: qcom: Fix minidump out-of-bounds access on subsystems array
dt-bindings: remoteproc: k3-r5f: Add memory-region-names
dt-bindings: remoteproc: k3-r5f: Split up memory regions
remoteproc: use SIZE_MAX in rproc_u64_fit_in_size_t()
dt-bindings: remoteproc: qcom,sm8550-pas: Add Glymur CDSP
dt-bindings: remoteproc: qcom,sm8550-pas: Add Glymur ADSP
remoteproc: xlnx: Release mailbox channels on shutdown
remoteproc: sysmon: Use the unified QMI service ID instead of defining it locally
remoteproc: xlnx: Only access buffer information if IPI is buffered
remoteproc: xlnx: Avoid mailbox setup
remoteproc: keystone: Request IRQs in probe()
remoteproc: pru: Remove empty remove callback
remoteproc: pru: Use rproc_of_parse_firmware() to get firmware name
remoteproc: da8xx: Reorder resource fetching in probe()
remoteproc: da8xx: Remove unused local struct data
remoteproc: da8xx: Use dev_err_probe()
...
+486
-227
+3
Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml
+3
Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml
···
16
16
properties:
17
17
compatible:
18
18
enum:
19
+
- qcom,eliza-adsp-pas
19
20
- qcom,milos-adsp-pas
20
21
- qcom,milos-cdsp-pas
21
22
- qcom,milos-mpss-pas
···
70
69
properties:
71
70
compatible:
72
71
enum:
72
+
- qcom,eliza-adsp-pas
73
73
- qcom,milos-adsp-pas
74
74
- qcom,milos-cdsp-pas
75
75
then:
···
91
89
compatible:
92
90
contains:
93
91
enum:
92
+
- qcom,eliza-adsp-pas
94
93
- qcom,milos-adsp-pas
95
94
then:
96
95
properties:
+12
-2
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
+12
-2
Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
···
17
17
compatible:
18
18
oneOf:
19
19
- enum:
20
+
- qcom,mdm9607-mss-pil
20
21
- qcom,msm8226-mss-pil
21
22
- qcom,msm8909-mss-pil
22
23
- qcom,msm8916-mss-pil
24
+
- qcom,msm8917-mss-pil
23
25
- qcom,msm8926-mss-pil
26
+
- qcom,msm8937-mss-pil
27
+
- qcom,msm8940-mss-pil
24
28
- qcom,msm8953-mss-pil
25
29
- qcom,msm8974-mss-pil
26
30
···
93
89
description: PLL proxy supply (control handed over after startup)
94
90
95
91
mss-supply:
96
-
description: MSS power domain supply (only valid for qcom,msm8974-mss-pil)
92
+
description: MSS power domain supply
97
93
98
94
resets:
99
95
items:
···
141
137
- description: MPSS reserved region
142
138
143
139
firmware-name:
144
-
$ref: /schemas/types.yaml#/definitions/string-array
145
140
items:
146
141
- description: Name of MBA firmware
147
142
- description: Name of modem firmware
···
229
226
compatible:
230
227
contains:
231
228
enum:
229
+
- qcom,mdm9607-mss-pil
232
230
- qcom,msm8909-mss-pil
233
231
- qcom,msm8916-mss-pil
232
+
- qcom,msm8917-mss-pil
233
+
- qcom,msm8937-mss-pil
234
+
- qcom,msm8940-mss-pil
234
235
then:
235
236
properties:
236
237
power-domains:
···
278
271
contains:
279
272
enum:
280
273
- qcom,msm8926-mss-pil
274
+
- qcom,msm8917-mss-pil
275
+
- qcom,msm8937-mss-pil
276
+
- qcom,msm8940-mss-pil
281
277
- qcom,msm8974-mss-pil
282
278
then:
283
279
required:
-1
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml
+1
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml
+1
-1
Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml
+1
-1
Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml
+1
-1
Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml
+13
-2
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
+13
-2
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
···
28
28
- qcom,x1e80100-adsp-pas
29
29
- qcom,x1e80100-cdsp-pas
30
30
- items:
31
-
- const: qcom,sm8750-adsp-pas
31
+
- enum:
32
+
- qcom,glymur-adsp-pas
33
+
- qcom,kaanapali-adsp-pas
34
+
- qcom,sm8750-adsp-pas
32
35
- const: qcom,sm8550-adsp-pas
36
+
- items:
37
+
- enum:
38
+
- qcom,glymur-cdsp-pas
39
+
- qcom,kaanapali-cdsp-pas
40
+
- const: qcom,sm8550-cdsp-pas
33
41
- items:
34
42
- const: qcom,sm8750-cdsp-pas
35
43
- const: qcom,sm8650-cdsp-pas
···
60
52
smd-edge: false
61
53
62
54
firmware-name:
63
-
$ref: /schemas/types.yaml#/definitions/string-array
64
55
items:
65
56
- description: Firmware name of the Hexagon core
66
57
- description: Firmware name of the Hexagon Devicetree
···
102
95
compatible:
103
96
contains:
104
97
enum:
98
+
- qcom,glymur-adsp-pas
99
+
- qcom,glymur-cdsp-pas
100
+
- qcom,kaanapali-adsp-pas
101
+
- qcom,kaanapali-cdsp-pas
105
102
- qcom,sm8750-adsp-pas
106
103
then:
107
104
properties:
+45
-10
Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml
+45
-10
Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml
···
154
154
memory-region:
155
155
description: |
156
156
phandle to the reserved memory nodes to be associated with the
157
-
remoteproc device. There should be at least two reserved memory nodes
158
-
defined. The reserved memory nodes should be carveout nodes, and
159
-
should be defined with a "no-map" property as per the bindings in
157
+
remoteproc device. There should be two reserved memory nodes defined
158
+
for the basic layout or 6 partitions for a detailed layout. The
159
+
reserved memory nodes should be carveout nodes, and should be defined
160
+
with a "no-map" property as per the bindings in
160
161
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
161
-
minItems: 2
162
-
maxItems: 8
163
-
items:
164
-
- description: region used for dynamic DMA allocations like vrings and
165
-
vring buffers
166
-
- description: region reserved for firmware image sections
167
-
additionalItems: true
162
+
oneOf:
163
+
- description: Basic layout
164
+
items:
165
+
- description: region used for dynamic DMA allocations like vrings and
166
+
vring buffers
167
+
- description: region reserved for firmware image sections
168
+
- description: Detailed layout
169
+
items:
170
+
- description: region used for dynamic DMA allocations like vrings and
171
+
vring buffers
172
+
- description: region reserved for IPC resources
173
+
- description: LPM FS stub binary
174
+
- description: LPM metadata
175
+
- description: LPM FS context data and reserved sections
176
+
- description: DM RM/PM trace and firmware code/data
177
+
178
+
memory-region-names:
179
+
description: |
180
+
Names for the memory regions specified in the memory-region property.
181
+
The names must correspond with the entries in memory-region.
182
+
oneOf:
183
+
- description: Basic layout
184
+
items:
185
+
- const: dma
186
+
- const: firmware
187
+
- description: Detailed layout
188
+
items:
189
+
- const: dma
190
+
- const: ipc
191
+
- const: lpm-stub
192
+
- const: lpm-metadata
193
+
- const: lpm-context
194
+
- const: dm-firmware
168
195
169
196
# Optional properties:
170
197
# --------------------
···
244
217
- ti,sci-proc-ids
245
218
- resets
246
219
- firmware-name
220
+
221
+
if:
222
+
required:
223
+
- memory-region
224
+
then:
225
+
required:
226
+
- memory-region-names
247
227
248
228
unevaluatedProperties: false
249
229
···
355
321
mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
356
322
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
357
323
<&mcu_r5fss0_core0_memory_region>;
324
+
memory-region-names = "dma", "firmware";
358
325
sram = <&mcu_r5fss0_core0_sram>;
359
326
};
360
327
+39
-58
drivers/remoteproc/da8xx_remoteproc.c
+39
-58
drivers/remoteproc/da8xx_remoteproc.c
···
57
57
* @mem: internal memory regions data
58
58
* @num_mems: number of internal memory regions
59
59
* @dsp_clk: placeholder for platform's DSP clk
60
-
* @ack_fxn: chip-specific ack function for ack'ing irq
60
+
* @dsp_reset: control for local reset
61
61
* @irq_data: ack_fxn function parameter
62
62
* @chipsig: virt ptr to DSP interrupt registers (CHIPSIG & CHIPSIG_CLR)
63
63
* @bootreg: virt ptr to DSP boot address register (HOST1CFG)
64
-
* @irq: irq # used by this instance
65
64
*/
66
65
struct da8xx_rproc {
67
66
struct rproc *rproc;
···
68
69
int num_mems;
69
70
struct clk *dsp_clk;
70
71
struct reset_control *dsp_reset;
71
-
void (*ack_fxn)(struct irq_data *data);
72
72
struct irq_data *irq_data;
73
73
void __iomem *chipsig;
74
74
void __iomem *bootreg;
75
-
int irq;
76
75
};
77
76
78
77
/**
···
119
122
* we need to ack it after taking down the level else we'll
120
123
* be called again immediately after returning.
121
124
*/
122
-
drproc->ack_fxn(drproc->irq_data);
125
+
drproc->irq_data->chip->irq_ack(drproc->irq_data);
123
126
124
127
return IRQ_WAKE_THREAD;
125
128
}
···
242
245
struct device *dev = &pdev->dev;
243
246
struct da8xx_rproc *drproc;
244
247
struct rproc *rproc;
245
-
struct irq_data *irq_data;
246
-
struct clk *dsp_clk;
247
-
struct reset_control *dsp_reset;
248
-
void __iomem *chipsig;
249
-
void __iomem *bootreg;
250
248
int irq;
251
249
int ret;
252
-
253
-
irq = platform_get_irq(pdev, 0);
254
-
if (irq < 0)
255
-
return irq;
256
-
257
-
irq_data = irq_get_irq_data(irq);
258
-
if (!irq_data)
259
-
return dev_err_probe(dev, -EINVAL, "irq_get_irq_data(%d): NULL\n", irq);
260
-
261
-
bootreg = devm_platform_ioremap_resource_byname(pdev, "host1cfg");
262
-
if (IS_ERR(bootreg))
263
-
return PTR_ERR(bootreg);
264
-
265
-
chipsig = devm_platform_ioremap_resource_byname(pdev, "chipsig");
266
-
if (IS_ERR(chipsig))
267
-
return PTR_ERR(chipsig);
268
-
269
-
dsp_clk = devm_clk_get(dev, NULL);
270
-
if (IS_ERR(dsp_clk))
271
-
return dev_err_probe(dev, PTR_ERR(dsp_clk), "clk_get error\n");
272
-
273
-
dsp_reset = devm_reset_control_get_exclusive(dev, NULL);
274
-
if (IS_ERR(dsp_reset))
275
-
return dev_err_probe(dev, PTR_ERR(dsp_reset), "unable to get reset control\n");
276
-
277
-
if (dev->of_node) {
278
-
ret = of_reserved_mem_device_init(dev);
279
-
if (ret)
280
-
return dev_err_probe(dev, ret, "device does not have specific CMA pool\n");
281
-
devm_add_action_or_reset(&pdev->dev, da8xx_rproc_mem_release, &pdev->dev);
282
-
}
283
250
284
251
rproc = devm_rproc_alloc(dev, "dsp", &da8xx_rproc_ops, da8xx_fw_name,
285
252
sizeof(*drproc));
···
255
294
256
295
drproc = rproc->priv;
257
296
drproc->rproc = rproc;
258
-
drproc->dsp_clk = dsp_clk;
259
-
drproc->dsp_reset = dsp_reset;
260
297
rproc->has_iommu = false;
298
+
299
+
drproc->dsp_clk = devm_clk_get(dev, NULL);
300
+
if (IS_ERR(drproc->dsp_clk))
301
+
return dev_err_probe(dev, PTR_ERR(drproc->dsp_clk), "clk_get error\n");
302
+
303
+
drproc->dsp_reset = devm_reset_control_get_exclusive(dev, NULL);
304
+
if (IS_ERR(drproc->dsp_reset))
305
+
return dev_err_probe(dev, PTR_ERR(drproc->dsp_reset),
306
+
"unable to get reset control\n");
307
+
308
+
if (dev->of_node) {
309
+
ret = of_reserved_mem_device_init(dev);
310
+
if (ret)
311
+
return dev_err_probe(dev, ret, "device does not have specific CMA pool\n");
312
+
devm_add_action_or_reset(&pdev->dev, da8xx_rproc_mem_release, &pdev->dev);
313
+
}
261
314
262
315
ret = da8xx_rproc_get_internal_memories(pdev, drproc);
263
316
if (ret)
264
317
return ret;
265
318
319
+
irq = platform_get_irq(pdev, 0);
320
+
if (irq < 0)
321
+
return irq;
322
+
323
+
drproc->irq_data = irq_get_irq_data(irq);
324
+
if (!drproc->irq_data)
325
+
return dev_err_probe(dev, -EINVAL, "irq_get_irq_data(%d): NULL\n", irq);
326
+
327
+
drproc->chipsig = devm_platform_ioremap_resource_byname(pdev, "chipsig");
328
+
if (IS_ERR(drproc->chipsig))
329
+
return PTR_ERR(drproc->chipsig);
330
+
331
+
drproc->bootreg = devm_platform_ioremap_resource_byname(pdev, "host1cfg");
332
+
if (IS_ERR(drproc->bootreg))
333
+
return PTR_ERR(drproc->bootreg);
334
+
266
335
/* everything the ISR needs is now setup, so hook it up */
267
336
ret = devm_request_threaded_irq(dev, irq, da8xx_rproc_callback,
268
337
handle_event, 0, "da8xx-remoteproc",
269
338
rproc);
270
-
if (ret) {
271
-
dev_err(dev, "devm_request_threaded_irq error: %d\n", ret);
272
-
return ret;
273
-
}
339
+
if (ret)
340
+
return dev_err_probe(dev, ret, "devm_request_threaded_irq error\n");
274
341
275
342
/*
276
343
* rproc_add() can end up enabling the DSP's clk with the DSP
277
344
* *not* in reset, but da8xx_rproc_start() needs the DSP to be
278
345
* held in reset at the time it is called.
279
346
*/
280
-
ret = reset_control_assert(dsp_reset);
347
+
ret = reset_control_assert(drproc->dsp_reset);
281
348
if (ret)
282
349
return ret;
283
350
284
-
drproc->chipsig = chipsig;
285
-
drproc->bootreg = bootreg;
286
-
drproc->ack_fxn = irq_data->chip->irq_ack;
287
-
drproc->irq_data = irq_data;
288
-
drproc->irq = irq;
289
-
290
351
ret = devm_rproc_add(dev, rproc);
291
-
if (ret) {
292
-
dev_err(dev, "rproc_add failed: %d\n", ret);
293
-
return ret;
294
-
}
352
+
if (ret)
353
+
return dev_err_probe(dev, ret, "rproc_add failed\n");
295
354
296
355
return 0;
297
356
}
+6
-2
drivers/remoteproc/imx_rproc.c
+6
-2
drivers/remoteproc/imx_rproc.c
···
812
812
813
813
/* Not use resource version, because we might share region */
814
814
priv->mem[b].cpu_addr = devm_ioremap_resource_wc(&pdev->dev, &res);
815
-
if (!priv->mem[b].cpu_addr) {
815
+
if (IS_ERR(priv->mem[b].cpu_addr)) {
816
816
dev_err(dev, "failed to remap %pr\n", &res);
817
817
return -ENOMEM;
818
818
}
···
1007
1007
}
1008
1008
1009
1009
priv->regmap = regmap;
1010
-
regmap_attach_dev(dev, regmap, &config);
1010
+
ret = regmap_attach_dev(dev, regmap, &config);
1011
+
if (ret) {
1012
+
dev_err(dev, "regmap attach failed\n");
1013
+
return ret;
1014
+
}
1011
1015
1012
1016
if (priv->gpr) {
1013
1017
ret = regmap_read(priv->gpr, dcfg->gpr_reg, &val);
+16
-27
drivers/remoteproc/keystone_remoteproc.c
+16
-27
drivers/remoteproc/keystone_remoteproc.c
···
173
173
174
174
INIT_WORK(&ksproc->workqueue, handle_event);
175
175
176
-
ret = request_irq(ksproc->irq_ring, keystone_rproc_vring_interrupt, 0,
177
-
dev_name(ksproc->dev), ksproc);
178
-
if (ret) {
179
-
dev_err(ksproc->dev, "failed to enable vring interrupt, ret = %d\n",
180
-
ret);
181
-
goto out;
182
-
}
183
-
184
-
ret = request_irq(ksproc->irq_fault, keystone_rproc_exception_interrupt,
185
-
0, dev_name(ksproc->dev), ksproc);
186
-
if (ret) {
187
-
dev_err(ksproc->dev, "failed to enable exception interrupt, ret = %d\n",
188
-
ret);
189
-
goto free_vring_irq;
190
-
}
176
+
enable_irq(ksproc->irq_ring);
177
+
enable_irq(ksproc->irq_fault);
191
178
192
179
ret = keystone_rproc_dsp_boot(ksproc, rproc->bootaddr);
193
-
if (ret)
194
-
goto free_exc_irq;
180
+
if (ret) {
181
+
flush_work(&ksproc->workqueue);
182
+
return ret;
183
+
}
195
184
196
185
return 0;
197
-
198
-
free_exc_irq:
199
-
free_irq(ksproc->irq_fault, ksproc);
200
-
free_vring_irq:
201
-
free_irq(ksproc->irq_ring, ksproc);
202
-
flush_work(&ksproc->workqueue);
203
-
out:
204
-
return ret;
205
186
}
206
187
207
188
/*
···
196
215
struct keystone_rproc *ksproc = rproc->priv;
197
216
198
217
keystone_rproc_dsp_reset(ksproc);
199
-
free_irq(ksproc->irq_fault, ksproc);
200
-
free_irq(ksproc->irq_ring, ksproc);
218
+
disable_irq(ksproc->irq_fault);
219
+
disable_irq(ksproc->irq_ring);
201
220
flush_work(&ksproc->workqueue);
202
221
203
222
return 0;
···
408
427
ksproc->irq_ring = platform_get_irq_byname(pdev, "vring");
409
428
if (ksproc->irq_ring < 0)
410
429
return ksproc->irq_ring;
430
+
ret = devm_request_irq(dev, ksproc->irq_ring, keystone_rproc_vring_interrupt,
431
+
IRQF_NO_AUTOEN, dev_name(dev), ksproc);
432
+
if (ret)
433
+
return dev_err_probe(dev, ret, "failed to request vring interrupt\n");
411
434
412
435
ksproc->irq_fault = platform_get_irq_byname(pdev, "exception");
413
436
if (ksproc->irq_fault < 0)
414
437
return ksproc->irq_fault;
438
+
ret = devm_request_irq(dev, ksproc->irq_fault, keystone_rproc_exception_interrupt,
439
+
IRQF_NO_AUTOEN, dev_name(dev), ksproc);
440
+
if (ret)
441
+
return dev_err_probe(dev, ret, "failed to enable exception interrupt\n");
415
442
416
443
ksproc->kick_gpio = devm_gpiod_get(dev, "kick", GPIOD_ASIS);
417
444
ret = PTR_ERR_OR_ZERO(ksproc->kick_gpio);
+3
-14
drivers/remoteproc/pru_rproc.c
+3
-14
drivers/remoteproc/pru_rproc.c
···
1003
1003
if (!data)
1004
1004
return -ENODEV;
1005
1005
1006
-
ret = of_property_read_string(np, "firmware-name", &fw_name);
1007
-
if (ret) {
1008
-
dev_err(dev, "unable to retrieve firmware-name %d\n", ret);
1009
-
return ret;
1010
-
}
1006
+
ret = rproc_of_parse_firmware(dev, 0, &fw_name);
1007
+
if (ret)
1008
+
return dev_err_probe(dev, ret, "unable to retrieve firmware-name\n");
1011
1009
1012
1010
rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name,
1013
1011
sizeof(*pru));
···
1078
1080
return 0;
1079
1081
}
1080
1082
1081
-
static void pru_rproc_remove(struct platform_device *pdev)
1082
-
{
1083
-
struct device *dev = &pdev->dev;
1084
-
struct rproc *rproc = platform_get_drvdata(pdev);
1085
-
1086
-
dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name);
1087
-
}
1088
-
1089
1083
static const struct pru_private_data pru_data = {
1090
1084
.type = PRU_TYPE_PRU,
1091
1085
};
···
1123
1133
.suppress_bind_attrs = true,
1124
1134
},
1125
1135
.probe = pru_rproc_probe,
1126
-
.remove = pru_rproc_remove,
1127
1136
};
1128
1137
module_platform_driver(pru_rproc_driver);
1129
1138
+14
-3
drivers/remoteproc/qcom_common.c
+14
-3
drivers/remoteproc/qcom_common.c
···
28
28
#define to_ssr_subdev(d) container_of(d, struct qcom_rproc_ssr, subdev)
29
29
#define to_pdm_subdev(d) container_of(d, struct qcom_rproc_pdm, subdev)
30
30
31
-
#define MAX_NUM_OF_SS 10
32
31
#define MAX_REGION_NAME_LENGTH 16
33
32
#define SBL_MINIDUMP_SMEM_ID 602
34
33
#define MINIDUMP_REGION_VALID ('V' << 24 | 'A' << 16 | 'L' << 8 | 'I' << 0)
···
79
80
__le32 status;
80
81
__le32 md_revision;
81
82
__le32 enabled;
82
-
struct minidump_subsystem subsystems[MAX_NUM_OF_SS];
83
+
struct minidump_subsystem subsystems[];
83
84
};
84
85
85
86
struct qcom_ssr_subsystem {
···
150
151
int ret;
151
152
struct minidump_subsystem *subsystem;
152
153
struct minidump_global_toc *toc;
154
+
unsigned int num_ss;
155
+
size_t toc_size;
153
156
154
157
/* Get Global minidump ToC*/
155
-
toc = qcom_smem_get(QCOM_SMEM_HOST_ANY, SBL_MINIDUMP_SMEM_ID, NULL);
158
+
toc = qcom_smem_get(QCOM_SMEM_HOST_ANY, SBL_MINIDUMP_SMEM_ID, &toc_size);
156
159
157
160
/* check if global table pointer exists and init is set */
158
161
if (IS_ERR(toc) || !toc->status) {
159
162
dev_err(&rproc->dev, "Minidump TOC not found in SMEM\n");
163
+
return;
164
+
}
165
+
166
+
/* Derive the number of subsystems from the actual SMEM item size */
167
+
num_ss = (toc_size - offsetof(struct minidump_global_toc, subsystems)) /
168
+
sizeof(struct minidump_subsystem);
169
+
170
+
if (minidump_id >= num_ss) {
171
+
dev_err(&rproc->dev, "Minidump id %d is out of range: %d\n",
172
+
minidump_id, num_ss);
160
173
return;
161
174
}
162
175
+242
-21
drivers/remoteproc/qcom_q6v5_mss.c
+242
-21
drivers/remoteproc/qcom_q6v5_mss.c
···
124
124
#define QDSP6v56_CLAMP_QMC_MEM BIT(22)
125
125
#define QDSP6SS_XO_CBCR 0x0038
126
126
#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
127
+
#define QDSP6SS_ACC_OVERRIDE_VAL_9607 0x80800000
127
128
#define QDSP6v55_BHS_EN_REST_ACK BIT(0)
128
129
129
130
/* QDSP6v65 parameters */
···
163
162
char **proxy_pd_names;
164
163
int version;
165
164
bool need_mem_protection;
165
+
bool need_pas_mem_setup;
166
166
bool has_alt_reset;
167
167
bool has_mba_logs;
168
168
bool has_spare_reg;
···
242
240
struct qcom_sysmon *sysmon;
243
241
struct platform_device *bam_dmux;
244
242
bool need_mem_protection;
243
+
bool need_pas_mem_setup;
245
244
bool has_alt_reset;
246
245
bool has_mba_logs;
247
246
bool has_spare_reg;
···
257
254
};
258
255
259
256
enum {
257
+
MSS_MDM9607,
260
258
MSS_MSM8226,
261
259
MSS_MSM8909,
262
260
MSS_MSM8916,
261
+
MSS_MSM8917,
263
262
MSS_MSM8926,
263
+
MSS_MSM8937,
264
+
MSS_MSM8940,
264
265
MSS_MSM8953,
265
266
MSS_MSM8974,
266
267
MSS_MSM8996,
···
752
745
return ret;
753
746
}
754
747
goto pbl_wait;
755
-
} else if (qproc->version == MSS_MSM8909 ||
748
+
} else if (qproc->version == MSS_MDM9607 ||
749
+
qproc->version == MSS_MSM8909 ||
750
+
qproc->version == MSS_MSM8917 ||
751
+
qproc->version == MSS_MSM8937 ||
752
+
qproc->version == MSS_MSM8940 ||
756
753
qproc->version == MSS_MSM8953 ||
757
754
qproc->version == MSS_MSM8996 ||
758
755
qproc->version == MSS_MSM8998 ||
759
756
qproc->version == MSS_SDM660) {
760
757
761
-
if (qproc->version != MSS_MSM8909 &&
762
-
qproc->version != MSS_MSM8953)
763
-
/* Override the ACC value if required */
758
+
/* Override the ACC value if required */
759
+
if (qproc->version == MSS_MDM9607 ||
760
+
qproc->version == MSS_MSM8917 ||
761
+
qproc->version == MSS_MSM8937 ||
762
+
qproc->version == MSS_MSM8940)
763
+
writel(QDSP6SS_ACC_OVERRIDE_VAL_9607,
764
+
qproc->reg_base + QDSP6SS_STRAP_ACC);
765
+
else if (qproc->version != MSS_MSM8909 &&
766
+
qproc->version != MSS_MSM8953)
764
767
writel(QDSP6SS_ACC_OVERRIDE_VAL,
765
768
qproc->reg_base + QDSP6SS_STRAP_ACC);
766
769
···
816
799
817
800
if (qproc->version != MSS_MSM8909) {
818
801
int mem_pwr_ctl;
802
+
int reverse;
819
803
820
804
/* Deassert QDSP6 compiler memory clamp */
821
805
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
···
828
810
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
829
811
830
812
/* Turn on L1, L2, ETB and JU memories 1 at a time */
831
-
if (qproc->version == MSS_MSM8953 ||
813
+
if (qproc->version == MSS_MSM8940 ||
814
+
qproc->version == MSS_MSM8953 ||
832
815
qproc->version == MSS_MSM8996) {
833
816
mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
834
817
i = 19;
818
+
reverse = 0;
819
+
} else if (qproc->version == MSS_MDM9607 ||
820
+
qproc->version == MSS_MSM8917 ||
821
+
qproc->version == MSS_MSM8937) {
822
+
mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
823
+
i = 19;
824
+
/*
825
+
* Set first 5 bits in reverse to avoid
826
+
* "inrush current" issues.
827
+
*/
828
+
reverse = 6;
835
829
} else {
836
830
/* MSS_MSM8998, MSS_SDM660 */
837
831
mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
838
832
i = 28;
833
+
reverse = 0;
839
834
}
835
+
840
836
val = readl(qproc->reg_base + mem_pwr_ctl);
841
-
for (; i >= 0; i--) {
837
+
for (; i >= reverse; i--) {
838
+
val |= BIT(i);
839
+
writel(val, qproc->reg_base + mem_pwr_ctl);
840
+
val = readl(qproc->reg_base + mem_pwr_ctl);
841
+
udelay(1);
842
+
}
843
+
for (i = 0; i < reverse; i++) {
842
844
val |= BIT(i);
843
845
writel(val, qproc->reg_base + mem_pwr_ctl);
844
846
/*
···
866
828
* wait for 1us for both memory peripheral and data
867
829
* array to turn on.
868
830
*/
869
-
val |= readl(qproc->reg_base + mem_pwr_ctl);
831
+
val = readl(qproc->reg_base + mem_pwr_ctl);
870
832
udelay(1);
871
833
}
872
834
} else {
···
1479
1441
max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1480
1442
}
1481
1443
1482
-
if (qproc->version == MSS_MSM8953) {
1444
+
if (qproc->need_pas_mem_setup) {
1483
1445
ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size);
1484
1446
if (ret) {
1485
1447
dev_err(qproc->dev,
···
2262
2224
NULL
2263
2225
},
2264
2226
.need_mem_protection = true,
2227
+
.need_pas_mem_setup = false,
2265
2228
.has_alt_reset = false,
2266
2229
.has_mba_logs = true,
2267
2230
.has_spare_reg = true,
···
2292
2253
NULL
2293
2254
},
2294
2255
.need_mem_protection = true,
2256
+
.need_pas_mem_setup = false,
2295
2257
.has_alt_reset = false,
2296
2258
.has_mba_logs = true,
2297
2259
.has_spare_reg = false,
···
2325
2285
NULL
2326
2286
},
2327
2287
.need_mem_protection = true,
2288
+
.need_pas_mem_setup = false,
2328
2289
.has_alt_reset = false,
2329
2290
.has_mba_logs = false,
2330
2291
.has_spare_reg = false,
···
2362
2321
NULL
2363
2322
},
2364
2323
.need_mem_protection = true,
2324
+
.need_pas_mem_setup = false,
2365
2325
.has_alt_reset = true,
2366
2326
.has_mba_logs = false,
2367
2327
.has_spare_reg = false,
···
2395
2353
NULL
2396
2354
},
2397
2355
.need_mem_protection = true,
2356
+
.need_pas_mem_setup = false,
2398
2357
.has_alt_reset = false,
2399
2358
.has_mba_logs = false,
2400
2359
.has_spare_reg = false,
···
2435
2392
NULL
2436
2393
},
2437
2394
.need_mem_protection = true,
2395
+
.need_pas_mem_setup = false,
2438
2396
.has_alt_reset = false,
2439
2397
.has_mba_logs = false,
2440
2398
.has_spare_reg = false,
···
2444
2400
.has_ext_cntl_regs = false,
2445
2401
.has_vq6 = false,
2446
2402
.version = MSS_MSM8996,
2403
+
};
2404
+
2405
+
static const struct rproc_hexagon_res mdm9607_mss = {
2406
+
.hexagon_mba_image = "mba.mbn",
2407
+
.proxy_supply = (struct qcom_mss_reg_res[]) {
2408
+
{
2409
+
.supply = "pll",
2410
+
.uA = 100000,
2411
+
},
2412
+
{}
2413
+
},
2414
+
.proxy_clk_names = (char*[]){
2415
+
"xo",
2416
+
NULL
2417
+
},
2418
+
.active_clk_names = (char*[]){
2419
+
"iface",
2420
+
"bus",
2421
+
"mem",
2422
+
NULL
2423
+
},
2424
+
.proxy_pd_names = (char*[]){
2425
+
"mx",
2426
+
"cx",
2427
+
NULL
2428
+
},
2429
+
.need_mem_protection = false,
2430
+
.has_alt_reset = false,
2431
+
.has_mba_logs = false,
2432
+
.has_spare_reg = false,
2433
+
.has_qaccept_regs = false,
2434
+
.has_ext_bhs_reg = false,
2435
+
.has_ext_cntl_regs = false,
2436
+
.has_vq6 = false,
2437
+
.version = MSS_MDM9607,
2447
2438
};
2448
2439
2449
2440
static const struct rproc_hexagon_res msm8909_mss = {
···
2506
2427
NULL
2507
2428
},
2508
2429
.need_mem_protection = false,
2430
+
.need_pas_mem_setup = false,
2509
2431
.has_alt_reset = false,
2510
2432
.has_mba_logs = false,
2511
2433
.has_spare_reg = false,
···
2553
2473
NULL
2554
2474
},
2555
2475
.need_mem_protection = false,
2476
+
.need_pas_mem_setup = false,
2556
2477
.has_alt_reset = false,
2557
2478
.has_mba_logs = false,
2558
2479
.has_spare_reg = false,
···
2562
2481
.has_ext_cntl_regs = false,
2563
2482
.has_vq6 = false,
2564
2483
.version = MSS_MSM8916,
2484
+
};
2485
+
2486
+
static const struct rproc_hexagon_res msm8917_mss = {
2487
+
.hexagon_mba_image = "mba.mbn",
2488
+
.proxy_supply = (struct qcom_mss_reg_res[]) {
2489
+
{
2490
+
.supply = "pll",
2491
+
.uA = 100000,
2492
+
},
2493
+
{}
2494
+
},
2495
+
.active_supply = (struct qcom_mss_reg_res[]) {
2496
+
{
2497
+
.supply = "mss",
2498
+
.uV = 1050000,
2499
+
.uA = 100000,
2500
+
},
2501
+
{}
2502
+
},
2503
+
.proxy_clk_names = (char*[]){
2504
+
"xo",
2505
+
NULL
2506
+
},
2507
+
.active_clk_names = (char*[]){
2508
+
"iface",
2509
+
"bus",
2510
+
"mem",
2511
+
NULL
2512
+
},
2513
+
.proxy_pd_names = (char*[]) {
2514
+
"cx",
2515
+
"mx",
2516
+
NULL
2517
+
},
2518
+
.need_mem_protection = false,
2519
+
.need_pas_mem_setup = false,
2520
+
.has_alt_reset = false,
2521
+
.has_mba_logs = false,
2522
+
.has_spare_reg = false,
2523
+
.has_qaccept_regs = false,
2524
+
.has_ext_bhs_reg = false,
2525
+
.has_ext_cntl_regs = false,
2526
+
.has_vq6 = false,
2527
+
.version = MSS_MSM8917,
2528
+
};
2529
+
2530
+
static const struct rproc_hexagon_res msm8937_mss = {
2531
+
.hexagon_mba_image = "mba.mbn",
2532
+
.proxy_supply = (struct qcom_mss_reg_res[]) {
2533
+
{
2534
+
.supply = "pll",
2535
+
.uA = 100000,
2536
+
},
2537
+
{}
2538
+
},
2539
+
.active_supply = (struct qcom_mss_reg_res[]) {
2540
+
{
2541
+
.supply = "mss",
2542
+
.uV = 1050000,
2543
+
.uA = 100000,
2544
+
},
2545
+
{}
2546
+
},
2547
+
.proxy_clk_names = (char*[]){
2548
+
"xo",
2549
+
NULL
2550
+
},
2551
+
.active_clk_names = (char*[]){
2552
+
"iface",
2553
+
"bus",
2554
+
"mem",
2555
+
NULL
2556
+
},
2557
+
.proxy_pd_names = (char*[]) {
2558
+
"cx",
2559
+
"mx",
2560
+
NULL
2561
+
},
2562
+
.need_mem_protection = false,
2563
+
.need_pas_mem_setup = true,
2564
+
.has_alt_reset = false,
2565
+
.has_mba_logs = false,
2566
+
.has_spare_reg = false,
2567
+
.has_qaccept_regs = false,
2568
+
.has_ext_bhs_reg = false,
2569
+
.has_ext_cntl_regs = false,
2570
+
.has_vq6 = false,
2571
+
.version = MSS_MSM8937,
2572
+
};
2573
+
2574
+
static const struct rproc_hexagon_res msm8940_mss = {
2575
+
.hexagon_mba_image = "mba.mbn",
2576
+
.proxy_supply = (struct qcom_mss_reg_res[]) {
2577
+
{
2578
+
.supply = "pll",
2579
+
.uA = 100000,
2580
+
},
2581
+
{}
2582
+
},
2583
+
.active_supply = (struct qcom_mss_reg_res[]) {
2584
+
{
2585
+
.supply = "mss",
2586
+
.uV = 1050000,
2587
+
.uA = 100000,
2588
+
},
2589
+
{}
2590
+
},
2591
+
.proxy_clk_names = (char*[]){
2592
+
"xo",
2593
+
NULL
2594
+
},
2595
+
.active_clk_names = (char*[]){
2596
+
"iface",
2597
+
"bus",
2598
+
"mem",
2599
+
NULL
2600
+
},
2601
+
.proxy_pd_names = (char*[]) {
2602
+
"cx",
2603
+
"mx",
2604
+
NULL
2605
+
},
2606
+
.need_mem_protection = false,
2607
+
.need_pas_mem_setup = true,
2608
+
.has_alt_reset = false,
2609
+
.has_mba_logs = false,
2610
+
.has_spare_reg = false,
2611
+
.has_qaccept_regs = false,
2612
+
.has_ext_bhs_reg = false,
2613
+
.has_ext_cntl_regs = false,
2614
+
.has_vq6 = false,
2615
+
.version = MSS_MSM8940,
2565
2616
};
2566
2617
2567
2618
static const struct rproc_hexagon_res msm8953_mss = {
···
2722
2509
NULL
2723
2510
},
2724
2511
.need_mem_protection = false,
2512
+
.need_pas_mem_setup = true,
2725
2513
.has_alt_reset = false,
2726
2514
.has_mba_logs = false,
2727
2515
.has_spare_reg = false,
···
2776
2562
NULL
2777
2563
},
2778
2564
.need_mem_protection = false,
2565
+
.need_pas_mem_setup = false,
2779
2566
.has_alt_reset = false,
2780
2567
.has_mba_logs = false,
2781
2568
.has_spare_reg = false,
···
2815
2600
NULL
2816
2601
},
2817
2602
.need_mem_protection = false,
2603
+
.need_pas_mem_setup = false,
2818
2604
.has_alt_reset = false,
2819
2605
.has_mba_logs = false,
2820
2606
.has_spare_reg = false,
···
2862
2646
NULL
2863
2647
},
2864
2648
.need_mem_protection = false,
2649
+
.need_pas_mem_setup = false,
2865
2650
.has_alt_reset = false,
2866
2651
.has_mba_logs = false,
2867
2652
.has_spare_reg = false,
···
2874
2657
};
2875
2658
2876
2659
static const struct of_device_id q6v5_of_match[] = {
2877
-
{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2878
-
{ .compatible = "qcom,msm8226-mss-pil", .data = &msm8226_mss},
2879
-
{ .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss},
2880
-
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2881
-
{ .compatible = "qcom,msm8926-mss-pil", .data = &msm8926_mss},
2882
-
{ .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss},
2883
-
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2884
-
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2885
-
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2886
-
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2887
-
{ .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2888
-
{ .compatible = "qcom,sdm660-mss-pil", .data = &sdm660_mss},
2889
-
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2660
+
{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss },
2661
+
{ .compatible = "qcom,mdm9607-mss-pil", .data = &mdm9607_mss },
2662
+
{ .compatible = "qcom,msm8226-mss-pil", .data = &msm8226_mss },
2663
+
{ .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss },
2664
+
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss },
2665
+
{ .compatible = "qcom,msm8917-mss-pil", .data = &msm8917_mss },
2666
+
{ .compatible = "qcom,msm8926-mss-pil", .data = &msm8926_mss },
2667
+
{ .compatible = "qcom,msm8937-mss-pil", .data = &msm8937_mss },
2668
+
{ .compatible = "qcom,msm8940-mss-pil", .data = &msm8940_mss },
2669
+
{ .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss },
2670
+
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss },
2671
+
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss },
2672
+
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss },
2673
+
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss },
2674
+
{ .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss },
2675
+
{ .compatible = "qcom,sdm660-mss-pil", .data = &sdm660_mss },
2676
+
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss },
2890
2677
{ },
2891
2678
};
2892
2679
MODULE_DEVICE_TABLE(of, q6v5_of_match);
+70
-69
drivers/remoteproc/qcom_q6v5_pas.c
+70
-69
drivers/remoteproc/qcom_q6v5_pas.c
···
1531
1531
};
1532
1532
1533
1533
static const struct of_device_id qcom_pas_of_match[] = {
1534
-
{ .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource},
1535
-
{ .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource},
1536
-
{ .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource},
1537
-
{ .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource},
1538
-
{ .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource},
1539
-
{ .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource},
1540
-
{ .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource},
1541
-
{ .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource},
1542
-
{ .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init},
1543
-
{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource},
1544
-
{ .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init},
1534
+
{ .compatible = "qcom,eliza-adsp-pas", .data = &sm8550_adsp_resource },
1535
+
{ .compatible = "qcom,milos-adsp-pas", .data = &sm8550_adsp_resource },
1536
+
{ .compatible = "qcom,milos-cdsp-pas", .data = &milos_cdsp_resource },
1537
+
{ .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource },
1538
+
{ .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource },
1539
+
{ .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource },
1540
+
{ .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource },
1541
+
{ .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource },
1542
+
{ .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource },
1543
+
{ .compatible = "qcom,msm8996-slpi-pil", .data = &msm8996_slpi_resource_init },
1544
+
{ .compatible = "qcom,msm8998-adsp-pas", .data = &msm8996_adsp_resource },
1545
+
{ .compatible = "qcom,msm8998-slpi-pas", .data = &msm8996_slpi_resource_init },
1545
1546
{ .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
1546
1547
{ .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
1547
1548
{ .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
1548
-
{ .compatible = "qcom,sa8775p-adsp-pas", .data = &sa8775p_adsp_resource},
1549
-
{ .compatible = "qcom,sa8775p-cdsp0-pas", .data = &sa8775p_cdsp0_resource},
1550
-
{ .compatible = "qcom,sa8775p-cdsp1-pas", .data = &sa8775p_cdsp1_resource},
1551
-
{ .compatible = "qcom,sa8775p-gpdsp0-pas", .data = &sa8775p_gpdsp0_resource},
1552
-
{ .compatible = "qcom,sa8775p-gpdsp1-pas", .data = &sa8775p_gpdsp1_resource},
1553
-
{ .compatible = "qcom,sar2130p-adsp-pas", .data = &sm8350_adsp_resource},
1554
-
{ .compatible = "qcom,sc7180-adsp-pas", .data = &sm8250_adsp_resource},
1555
-
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
1556
-
{ .compatible = "qcom,sc7280-adsp-pas", .data = &sm8350_adsp_resource},
1557
-
{ .compatible = "qcom,sc7280-cdsp-pas", .data = &sm6350_cdsp_resource},
1558
-
{ .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init},
1559
-
{ .compatible = "qcom,sc7280-wpss-pas", .data = &sc7280_wpss_resource},
1560
-
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource},
1561
-
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource},
1562
-
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource},
1563
-
{ .compatible = "qcom,sc8280xp-adsp-pas", .data = &sm8250_adsp_resource},
1564
-
{ .compatible = "qcom,sc8280xp-nsp0-pas", .data = &sc8280xp_nsp0_resource},
1565
-
{ .compatible = "qcom,sc8280xp-nsp1-pas", .data = &sc8280xp_nsp1_resource},
1566
-
{ .compatible = "qcom,sdm660-adsp-pas", .data = &adsp_resource_init},
1567
-
{ .compatible = "qcom,sdm660-cdsp-pas", .data = &cdsp_resource_init},
1568
-
{ .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init},
1569
-
{ .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init},
1570
-
{ .compatible = "qcom,sdm845-slpi-pas", .data = &sdm845_slpi_resource_init},
1571
-
{ .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource},
1572
-
{ .compatible = "qcom,sdx75-mpss-pas", .data = &sm8650_mpss_resource},
1573
-
{ .compatible = "qcom,sm6115-adsp-pas", .data = &adsp_resource_init},
1574
-
{ .compatible = "qcom,sm6115-cdsp-pas", .data = &cdsp_resource_init},
1575
-
{ .compatible = "qcom,sm6115-mpss-pas", .data = &sc8180x_mpss_resource},
1576
-
{ .compatible = "qcom,sm6350-adsp-pas", .data = &sm6350_adsp_resource},
1577
-
{ .compatible = "qcom,sm6350-cdsp-pas", .data = &sm6350_cdsp_resource},
1578
-
{ .compatible = "qcom,sm6350-mpss-pas", .data = &mpss_resource_init},
1579
-
{ .compatible = "qcom,sm6375-adsp-pas", .data = &sm6350_adsp_resource},
1580
-
{ .compatible = "qcom,sm6375-cdsp-pas", .data = &sm8150_cdsp_resource},
1581
-
{ .compatible = "qcom,sm6375-mpss-pas", .data = &sm6375_mpss_resource},
1582
-
{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
1583
-
{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
1584
-
{ .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
1585
-
{ .compatible = "qcom,sm8150-slpi-pas", .data = &sdm845_slpi_resource_init},
1586
-
{ .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource},
1587
-
{ .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource},
1588
-
{ .compatible = "qcom,sm8250-slpi-pas", .data = &sdm845_slpi_resource_init},
1589
-
{ .compatible = "qcom,sm8350-adsp-pas", .data = &sm8350_adsp_resource},
1590
-
{ .compatible = "qcom,sm8350-cdsp-pas", .data = &sm8350_cdsp_resource},
1591
-
{ .compatible = "qcom,sm8350-slpi-pas", .data = &sdm845_slpi_resource_init},
1592
-
{ .compatible = "qcom,sm8350-mpss-pas", .data = &mpss_resource_init},
1593
-
{ .compatible = "qcom,sm8450-adsp-pas", .data = &sm8350_adsp_resource},
1594
-
{ .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource},
1595
-
{ .compatible = "qcom,sm8450-slpi-pas", .data = &sdm845_slpi_resource_init},
1596
-
{ .compatible = "qcom,sm8450-mpss-pas", .data = &sm8450_mpss_resource},
1597
-
{ .compatible = "qcom,sm8550-adsp-pas", .data = &sm8550_adsp_resource},
1598
-
{ .compatible = "qcom,sm8550-cdsp-pas", .data = &sm8550_cdsp_resource},
1599
-
{ .compatible = "qcom,sm8550-mpss-pas", .data = &sm8550_mpss_resource},
1600
-
{ .compatible = "qcom,sm8650-adsp-pas", .data = &sm8550_adsp_resource},
1601
-
{ .compatible = "qcom,sm8650-cdsp-pas", .data = &sm8650_cdsp_resource},
1602
-
{ .compatible = "qcom,sm8650-mpss-pas", .data = &sm8650_mpss_resource},
1603
-
{ .compatible = "qcom,sm8750-mpss-pas", .data = &sm8750_mpss_resource},
1604
-
{ .compatible = "qcom,x1e80100-adsp-pas", .data = &x1e80100_adsp_resource},
1605
-
{ .compatible = "qcom,x1e80100-cdsp-pas", .data = &x1e80100_cdsp_resource},
1549
+
{ .compatible = "qcom,sa8775p-adsp-pas", .data = &sa8775p_adsp_resource },
1550
+
{ .compatible = "qcom,sa8775p-cdsp0-pas", .data = &sa8775p_cdsp0_resource },
1551
+
{ .compatible = "qcom,sa8775p-cdsp1-pas", .data = &sa8775p_cdsp1_resource },
1552
+
{ .compatible = "qcom,sa8775p-gpdsp0-pas", .data = &sa8775p_gpdsp0_resource },
1553
+
{ .compatible = "qcom,sa8775p-gpdsp1-pas", .data = &sa8775p_gpdsp1_resource },
1554
+
{ .compatible = "qcom,sar2130p-adsp-pas", .data = &sm8350_adsp_resource },
1555
+
{ .compatible = "qcom,sc7180-adsp-pas", .data = &sm8250_adsp_resource },
1556
+
{ .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init },
1557
+
{ .compatible = "qcom,sc7280-adsp-pas", .data = &sm8350_adsp_resource },
1558
+
{ .compatible = "qcom,sc7280-cdsp-pas", .data = &sm6350_cdsp_resource },
1559
+
{ .compatible = "qcom,sc7280-mpss-pas", .data = &mpss_resource_init },
1560
+
{ .compatible = "qcom,sc7280-wpss-pas", .data = &sc7280_wpss_resource },
1561
+
{ .compatible = "qcom,sc8180x-adsp-pas", .data = &sm8150_adsp_resource },
1562
+
{ .compatible = "qcom,sc8180x-cdsp-pas", .data = &sm8150_cdsp_resource },
1563
+
{ .compatible = "qcom,sc8180x-mpss-pas", .data = &sc8180x_mpss_resource },
1564
+
{ .compatible = "qcom,sc8280xp-adsp-pas", .data = &sm8250_adsp_resource },
1565
+
{ .compatible = "qcom,sc8280xp-nsp0-pas", .data = &sc8280xp_nsp0_resource },
1566
+
{ .compatible = "qcom,sc8280xp-nsp1-pas", .data = &sc8280xp_nsp1_resource },
1567
+
{ .compatible = "qcom,sdm660-adsp-pas", .data = &adsp_resource_init },
1568
+
{ .compatible = "qcom,sdm660-cdsp-pas", .data = &cdsp_resource_init },
1569
+
{ .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init },
1570
+
{ .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init },
1571
+
{ .compatible = "qcom,sdm845-slpi-pas", .data = &sdm845_slpi_resource_init },
1572
+
{ .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource },
1573
+
{ .compatible = "qcom,sdx75-mpss-pas", .data = &sm8650_mpss_resource },
1574
+
{ .compatible = "qcom,sm6115-adsp-pas", .data = &adsp_resource_init },
1575
+
{ .compatible = "qcom,sm6115-cdsp-pas", .data = &cdsp_resource_init },
1576
+
{ .compatible = "qcom,sm6115-mpss-pas", .data = &sc8180x_mpss_resource },
1577
+
{ .compatible = "qcom,sm6350-adsp-pas", .data = &sm6350_adsp_resource },
1578
+
{ .compatible = "qcom,sm6350-cdsp-pas", .data = &sm6350_cdsp_resource },
1579
+
{ .compatible = "qcom,sm6350-mpss-pas", .data = &mpss_resource_init },
1580
+
{ .compatible = "qcom,sm6375-adsp-pas", .data = &sm6350_adsp_resource },
1581
+
{ .compatible = "qcom,sm6375-cdsp-pas", .data = &sm8150_cdsp_resource },
1582
+
{ .compatible = "qcom,sm6375-mpss-pas", .data = &sm6375_mpss_resource },
1583
+
{ .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource },
1584
+
{ .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource },
1585
+
{ .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init },
1586
+
{ .compatible = "qcom,sm8150-slpi-pas", .data = &sdm845_slpi_resource_init },
1587
+
{ .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource },
1588
+
{ .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource },
1589
+
{ .compatible = "qcom,sm8250-slpi-pas", .data = &sdm845_slpi_resource_init },
1590
+
{ .compatible = "qcom,sm8350-adsp-pas", .data = &sm8350_adsp_resource },
1591
+
{ .compatible = "qcom,sm8350-cdsp-pas", .data = &sm8350_cdsp_resource },
1592
+
{ .compatible = "qcom,sm8350-slpi-pas", .data = &sdm845_slpi_resource_init },
1593
+
{ .compatible = "qcom,sm8350-mpss-pas", .data = &mpss_resource_init },
1594
+
{ .compatible = "qcom,sm8450-adsp-pas", .data = &sm8350_adsp_resource },
1595
+
{ .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource },
1596
+
{ .compatible = "qcom,sm8450-slpi-pas", .data = &sdm845_slpi_resource_init },
1597
+
{ .compatible = "qcom,sm8450-mpss-pas", .data = &sm8450_mpss_resource },
1598
+
{ .compatible = "qcom,sm8550-adsp-pas", .data = &sm8550_adsp_resource },
1599
+
{ .compatible = "qcom,sm8550-cdsp-pas", .data = &sm8550_cdsp_resource },
1600
+
{ .compatible = "qcom,sm8550-mpss-pas", .data = &sm8550_mpss_resource },
1601
+
{ .compatible = "qcom,sm8650-adsp-pas", .data = &sm8550_adsp_resource },
1602
+
{ .compatible = "qcom,sm8650-cdsp-pas", .data = &sm8650_cdsp_resource },
1603
+
{ .compatible = "qcom,sm8650-mpss-pas", .data = &sm8650_mpss_resource },
1604
+
{ .compatible = "qcom,sm8750-mpss-pas", .data = &sm8750_mpss_resource },
1605
+
{ .compatible = "qcom,x1e80100-adsp-pas", .data = &x1e80100_adsp_resource },
1606
+
{ .compatible = "qcom,x1e80100-cdsp-pas", .data = &x1e80100_cdsp_resource },
1606
1607
{ },
1607
1608
};
1608
1609
MODULE_DEVICE_TABLE(of, qcom_pas_of_match);
+1
-1
drivers/remoteproc/qcom_sysmon.c
+1
-1
drivers/remoteproc/qcom_sysmon.c
+1
-1
drivers/remoteproc/remoteproc_internal.h
+1
-1
drivers/remoteproc/remoteproc_internal.h
+1
-1
drivers/remoteproc/ti_k3_common.c
+1
-1
drivers/remoteproc/ti_k3_common.c
···
513
513
kproc->rmem[i].dev_addr = (u32)res.start;
514
514
kproc->rmem[i].size = resource_size(&res);
515
515
kproc->rmem[i].cpu_addr = devm_ioremap_resource_wc(dev, &res);
516
-
if (!kproc->rmem[i].cpu_addr) {
516
+
if (IS_ERR(kproc->rmem[i].cpu_addr)) {
517
517
dev_err(dev, "failed to map reserved memory#%d at %pR\n",
518
518
i + 1, &res);
519
519
return -ENOMEM;
+18
-10
drivers/remoteproc/xlnx_r5_remoteproc.c
+18
-10
drivers/remoteproc/xlnx_r5_remoteproc.c
···
232
232
233
233
ipi = container_of(cl, struct mbox_info, mbox_cl);
234
234
235
-
/* copy data from ipi buffer to r5_core */
235
+
/* copy data from ipi buffer to r5_core if IPI is buffered. */
236
236
ipi_msg = (struct zynqmp_ipi_message *)msg;
237
-
buf_msg = (struct zynqmp_ipi_message *)ipi->rx_mc_buf;
238
-
len = ipi_msg->len;
239
-
if (len > IPI_BUF_LEN_MAX) {
240
-
dev_warn(cl->dev, "msg size exceeded than %d\n",
241
-
IPI_BUF_LEN_MAX);
242
-
len = IPI_BUF_LEN_MAX;
237
+
if (ipi_msg) {
238
+
buf_msg = (struct zynqmp_ipi_message *)ipi->rx_mc_buf;
239
+
len = ipi_msg->len;
240
+
if (len > IPI_BUF_LEN_MAX) {
241
+
dev_warn(cl->dev, "msg size exceeded than %d\n",
242
+
IPI_BUF_LEN_MAX);
243
+
len = IPI_BUF_LEN_MAX;
244
+
}
245
+
buf_msg->len = len;
246
+
memcpy(buf_msg->data, ipi_msg->data, len);
243
247
}
244
-
buf_msg->len = len;
245
-
memcpy(buf_msg->data, ipi_msg->data, len);
246
248
247
249
/* received and processed interrupt ack */
248
250
if (mbox_send_message(ipi->rx_chan, NULL) < 0)
···
266
264
{
267
265
struct mbox_client *mbox_cl;
268
266
struct mbox_info *ipi;
267
+
268
+
if (!of_property_present(dev_of_node(cdev), "mboxes") ||
269
+
!of_property_present(dev_of_node(cdev), "mbox-names"))
270
+
return NULL;
269
271
270
272
ipi = kzalloc_obj(*ipi);
271
273
if (!ipi)
···
1011
1005
}
1012
1006
1013
1007
/* Get SRAM device address */
1014
-
ret = of_property_read_reg(sram_np, i, &abs_addr, &size);
1008
+
ret = of_property_read_reg(sram_np, 0, &abs_addr, &size);
1015
1009
if (ret) {
1016
1010
dev_err(dev, "failed to get reg property\n");
1017
1011
goto fail_sram_get;
···
1490
1484
dev_err(cluster->dev, "failed to %s rproc %d\n",
1491
1485
rproc_state_str, rproc->index);
1492
1486
}
1487
+
1488
+
zynqmp_r5_free_mbox(r5_core->ipi);
1493
1489
}
1494
1490
}
1495
1491