+81

Documentation/devicetree/bindings/dma/loongson,ls2k0300-dma.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/dma/loongson,ls2k0300-dma.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Loongson-2 Multi-Channel DMA controller 8 8 + 9 9 + description: 10 10 + The Loongson-2 Multi-Channel DMA controller is used for transferring data 11 11 + between system memory and the peripherals on the APB bus. 12 12 + 13 13 + maintainers: 14 14 + - Binbin Zhou <zhoubinbin@loongson.cn> 15 15 + 16 16 + allOf: 17 17 + - $ref: dma-controller.yaml# 18 18 + 19 19 + properties: 20 20 + compatible: 21 21 + enum: 22 22 + - loongson,ls2k0300-dma 23 23 + - loongson,ls2k3000-dma 24 24 + 25 25 + reg: 26 26 + maxItems: 1 27 27 + 28 28 + interrupts: 29 29 + description: 30 30 + Should contain all of the per-channel DMA interrupts in ascending order 31 31 + with respect to the DMA channel index. 32 32 + minItems: 4 33 33 + maxItems: 8 34 34 + 35 35 + clocks: 36 36 + maxItems: 1 37 37 + 38 38 + '#dma-cells': 39 39 + const: 2 40 40 + description: | 41 41 + DMA request from clients consists of 2 cells: 42 42 + 1. Channel index 43 43 + 2. Transfer request factor number, If no transfer factor, use 0. 44 44 + The number is SoC-specific, and this should be specified with 45 45 + relation to the device to use the DMA controller. 46 46 + 47 47 + dma-channels: 48 48 + enum: [4, 8] 49 49 + 50 50 + required: 51 51 + - compatible 52 52 + - reg 53 53 + - interrupts 54 54 + - clocks 55 55 + - '#dma-cells' 56 56 + - dma-channels 57 57 + 58 58 + unevaluatedProperties: false 59 59 + 60 60 + examples: 61 61 + - | 62 62 + #include <dt-bindings/interrupt-controller/irq.h> 63 63 + #include <dt-bindings/clock/loongson,ls2k-clk.h> 64 64 + 65 65 + dma-controller@1612c000 { 66 66 + compatible = "loongson,ls2k0300-dma"; 67 67 + reg = <0x1612c000 0xff>; 68 68 + interrupt-parent = <&liointc0>; 69 69 + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>, 70 70 + <24 IRQ_TYPE_LEVEL_HIGH>, 71 71 + <25 IRQ_TYPE_LEVEL_HIGH>, 72 72 + <26 IRQ_TYPE_LEVEL_HIGH>, 73 73 + <27 IRQ_TYPE_LEVEL_HIGH>, 74 74 + <28 IRQ_TYPE_LEVEL_HIGH>, 75 75 + <29 IRQ_TYPE_LEVEL_HIGH>, 76 76 + <30 IRQ_TYPE_LEVEL_HIGH>; 77 77 + clocks = <&clk LS2K0300_CLK_APB_GATE>; 78 78 + #dma-cells = <2>; 79 79 + dma-channels = <8>; 80 80 + }; 81 81 + ...

+84 -18

Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml

reviewed

··· 19 19 - renesas,r9a07g044-dmac # RZ/G2{L,LC} 20 20 - renesas,r9a07g054-dmac # RZ/V2L 21 21 - renesas,r9a08g045-dmac # RZ/G3S 22 22 + - renesas,r9a08g046-dmac # RZ/G3L 22 23 - const: renesas,rz-dmac 23 24 24 25 - items: ··· 30 29 31 30 - const: renesas,r9a09g057-dmac # RZ/V2H(P) 32 31 32 32 + - const: renesas,r9a09g077-dmac # RZ/T2H 33 33 + 34 34 + - items: 35 35 + - enum: 36 36 + - renesas,r9a09g087-dmac # RZ/N2H 37 37 + - const: renesas,r9a09g077-dmac 38 38 + 33 39 reg: 34 40 items: 35 41 - description: Control and channel register block ··· 44 36 minItems: 1 45 37 46 38 interrupts: 39 39 + minItems: 16 47 40 maxItems: 17 48 41 49 42 interrupt-names: 50 50 - items: 51 51 - - const: error 52 52 - - const: ch0 53 53 - - const: ch1 54 54 - - const: ch2 55 55 - - const: ch3 56 56 - - const: ch4 57 57 - - const: ch5 58 58 - - const: ch6 59 59 - - const: ch7 60 60 - - const: ch8 61 61 - - const: ch9 62 62 - - const: ch10 63 63 - - const: ch11 64 64 - - const: ch12 65 65 - - const: ch13 66 66 - - const: ch14 67 67 - - const: ch15 43 43 + minItems: 16 44 44 + maxItems: 17 68 45 69 46 clocks: 70 47 items: ··· 120 127 compatible: 121 128 contains: 122 129 enum: 130 130 + - renesas,rz-dmac 131 131 + - renesas,r9a09g057-dmac 132 132 + then: 133 133 + properties: 134 134 + interrupt-names: 135 135 + items: 136 136 + - const: error 137 137 + - const: ch0 138 138 + - const: ch1 139 139 + - const: ch2 140 140 + - const: ch3 141 141 + - const: ch4 142 142 + - const: ch5 143 143 + - const: ch6 144 144 + - const: ch7 145 145 + - const: ch8 146 146 + - const: ch9 147 147 + - const: ch10 148 148 + - const: ch11 149 149 + - const: ch12 150 150 + - const: ch13 151 151 + - const: ch14 152 152 + - const: ch15 153 153 + 154 154 + - if: 155 155 + properties: 156 156 + compatible: 157 157 + contains: 158 158 + enum: 123 159 - renesas,r9a07g043-dmac 124 160 - renesas,r9a07g044-dmac 125 161 - renesas,r9a07g054-dmac 126 162 - renesas,r9a08g045-dmac 163 163 + - renesas,r9a08g046-dmac 127 164 then: 128 165 properties: 129 166 reg: ··· 211 188 - power-domains 212 189 - renesas,icu 213 190 - resets 191 191 + 192 192 + - if: 193 193 + properties: 194 194 + compatible: 195 195 + contains: 196 196 + const: renesas,r9a09g077-dmac 197 197 + then: 198 198 + properties: 199 199 + reg: 200 200 + maxItems: 1 201 201 + clocks: 202 202 + maxItems: 1 203 203 + 204 204 + clock-names: false 205 205 + resets: false 206 206 + reset-names: false 207 207 + 208 208 + interrupts: 209 209 + maxItems: 16 210 210 + 211 211 + interrupt-names: 212 212 + items: 213 213 + - const: ch0 214 214 + - const: ch1 215 215 + - const: ch2 216 216 + - const: ch3 217 217 + - const: ch4 218 218 + - const: ch5 219 219 + - const: ch6 220 220 + - const: ch7 221 221 + - const: ch8 222 222 + - const: ch9 223 223 + - const: ch10 224 224 + - const: ch11 225 225 + - const: ch12 226 226 + - const: ch13 227 227 + - const: ch14 228 228 + - const: ch15 229 229 + 230 230 + required: 231 231 + - clocks 232 232 + - power-domains 233 233 + - renesas,icu 214 234 215 235 additionalProperties: false 216 236

+3

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

reviewed

··· 21 21 - enum: 22 22 - snps,axi-dma-1.01a 23 23 - intel,kmb-axi-dma 24 24 + - sophgo,cv1800b-axi-dma 24 25 - starfive,jh7110-axi-dma 25 26 - starfive,jh8100-axi-dma 26 27 - items: ··· 68 67 maximum: 8 69 68 70 69 dma-noncoherent: true 70 70 + 71 71 + dma-coherent: true 71 72 72 73 resets: 73 74 minItems: 1

-111

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

reviewed

··· 1 1 - Xilinx AXI VDMA engine, it does transfers between memory and video devices. 2 2 - It can be configured to have one channel or two channels. If configured 3 3 - as two channels, one is to transmit to the video device and another is 4 4 - to receive from the video device. 5 5 - 6 6 - Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 7 7 - target devices. It can be configured to have one channel or two channels. 8 8 - If configured as two channels, one is to transmit to the device and another 9 9 - is to receive from the device. 10 10 - 11 11 - Xilinx AXI CDMA engine, it does transfers between memory-mapped source 12 12 - address and a memory-mapped destination address. 13 13 - 14 14 - Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream 15 15 - target devices. It can be configured to have up to 16 independent transmit 16 16 - and receive channels. 17 17 - 18 18 - Required properties: 19 19 - - compatible: Should be one of- 20 20 - "xlnx,axi-vdma-1.00.a" 21 21 - "xlnx,axi-dma-1.00.a" 22 22 - "xlnx,axi-cdma-1.00.a" 23 23 - "xlnx,axi-mcdma-1.00.a" 24 24 - - #dma-cells: Should be <1>, see "dmas" property below 25 25 - - reg: Should contain VDMA registers location and length. 26 26 - - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). 27 27 - - dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. 28 28 - - dma-channel child node: Should have at least one channel and can have up to 29 29 - two channels per device. This node specifies the properties of each 30 30 - DMA channel (see child node properties below). 31 31 - - clocks: Input clock specifier. Refer to common clock bindings. 32 32 - - clock-names: List of input clocks 33 33 - For VDMA: 34 34 - Required elements: "s_axi_lite_aclk" 35 35 - Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", 36 36 - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" 37 37 - For CDMA: 38 38 - Required elements: "s_axi_lite_aclk", "m_axi_aclk" 39 39 - For AXIDMA and MCDMA: 40 40 - Required elements: "s_axi_lite_aclk" 41 41 - Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 42 42 - "m_axi_sg_aclk" 43 43 - 44 44 - Required properties for VDMA: 45 45 - - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. 46 46 - 47 47 - Optional properties for AXI DMA and MCDMA: 48 48 - - xlnx,sg-length-width: Should be set to the width in bits of the length 49 49 - register as configured in h/w. Takes values {8...26}. If the property 50 50 - is missing or invalid then the default value 23 is used. This is the 51 51 - maximum value that is supported by all IP versions. 52 52 - 53 53 - Optional properties for AXI DMA: 54 54 - - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. 55 55 - - xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from 56 56 - 0-255. Setting this value to zero disables the delay timer interrupt. 57 57 - 1 timeout interval = 125 * clock period of SG clock. 58 58 - Optional properties for VDMA: 59 59 - - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. 60 60 - It takes following values: 61 61 - {1}, flush both channels 62 62 - {2}, flush mm2s channel 63 63 - {3}, flush s2mm channel 64 64 - 65 65 - Required child node properties: 66 66 - - compatible: 67 67 - For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or 68 68 - "xlnx,axi-vdma-s2mm-channel". 69 69 - For CDMA: It should be "xlnx,axi-cdma-channel". 70 70 - For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" 71 71 - or "xlnx,axi-dma-s2mm-channel". 72 72 - - interrupts: Should contain per channel VDMA interrupts. 73 73 - - xlnx,datawidth: Should contain the stream data width, take values 74 74 - {32,64...1024}. 75 75 - 76 76 - Optional child node properties: 77 77 - - xlnx,include-dre: Tells hardware is configured for Data 78 78 - Realignment Engine. 79 79 - Optional child node properties for VDMA: 80 80 - - xlnx,genlock-mode: Tells Genlock synchronization is 81 81 - enabled/disabled in hardware. 82 82 - - xlnx,enable-vert-flip: Tells vertical flip is 83 83 - enabled/disabled in hardware(S2MM path). 84 84 - Optional child node properties for MCDMA: 85 85 - - dma-channels: Number of dma channels in child node. 86 86 - 87 87 - Example: 88 88 - ++++++++ 89 89 - 90 90 - axi_vdma_0: axivdma@40030000 { 91 91 - compatible = "xlnx,axi-vdma-1.00.a"; 92 92 - #dma_cells = <1>; 93 93 - reg = < 0x40030000 0x10000 >; 94 94 - dma-ranges = <0x00000000 0x00000000 0x40000000>; 95 95 - xlnx,num-fstores = <0x8>; 96 96 - xlnx,flush-fsync = <0x1>; 97 97 - xlnx,addrwidth = <0x20>; 98 98 - clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 99 99 - clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 100 100 - "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; 101 101 - dma-channel@40030000 { 102 102 - compatible = "xlnx,axi-vdma-mm2s-channel"; 103 103 - interrupts = < 0 54 4 >; 104 104 - xlnx,datawidth = <0x40>; 105 105 - } ; 106 106 - dma-channel@40030030 { 107 107 - compatible = "xlnx,axi-vdma-s2mm-channel"; 108 108 - interrupts = < 0 53 4 >; 109 109 - xlnx,datawidth = <0x40>; 110 110 - } ; 111 111 - } ;

+299

Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP 8 8 + 9 9 + maintainers: 10 10 + - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 11 11 + - Abin Joseph <abin.joseph@amd.com> 12 12 + 13 13 + description: > 14 14 + Xilinx AXI VDMA engine, it does transfers between memory and video devices. 15 15 + It can be configured to have one channel or two channels. If configured 16 16 + as two channels, one is to transmit to the video device and another is 17 17 + to receive from the video device. 18 18 + 19 19 + Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 20 20 + target devices. It can be configured to have one channel or two channels. 21 21 + If configured as two channels, one is to transmit to the device and another 22 22 + is to receive from the device. 23 23 + 24 24 + Xilinx AXI CDMA engine, it does transfers between memory-mapped source 25 25 + address and a memory-mapped destination address. 26 26 + 27 27 + Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream 28 28 + target devices. It can be configured to have up to 16 independent transmit 29 29 + and receive channels. 30 30 + 31 31 + properties: 32 32 + compatible: 33 33 + enum: 34 34 + - xlnx,axi-cdma-1.00.a 35 35 + - xlnx,axi-dma-1.00.a 36 36 + - xlnx,axi-mcdma-1.00.a 37 37 + - xlnx,axi-vdma-1.00.a 38 38 + 39 39 + reg: 40 40 + maxItems: 1 41 41 + 42 42 + "#dma-cells": 43 43 + const: 1 44 44 + 45 45 + "#address-cells": 46 46 + const: 1 47 47 + 48 48 + "#size-cells": 49 49 + const: 1 50 50 + 51 51 + interrupts: 52 52 + items: 53 53 + - description: Interrupt for single channel (MM2S or S2MM) 54 54 + - description: Interrupt for dual channel configuration 55 55 + minItems: 1 56 56 + description: 57 57 + Interrupt lines for the DMA controller. Only used when 58 58 + xlnx,axistream-connected is present (DMA connected to AXI Stream 59 59 + IP). When child dma-channel nodes are present, interrupts are 60 60 + specified in the child nodes instead. 61 61 + 62 62 + clocks: 63 63 + minItems: 1 64 64 + maxItems: 5 65 65 + 66 66 + clock-names: 67 67 + minItems: 1 68 68 + maxItems: 5 69 69 + 70 70 + dma-ranges: true 71 71 + 72 72 + xlnx,addrwidth: 73 73 + $ref: /schemas/types.yaml#/definitions/uint32 74 74 + enum: [32, 64] 75 75 + description: The DMA addressing size in bits. 76 76 + 77 77 + xlnx,num-fstores: 78 78 + $ref: /schemas/types.yaml#/definitions/uint32 79 79 + minimum: 1 80 80 + maximum: 32 81 81 + description: Should be the number of framebuffers as configured in h/w. 82 82 + 83 83 + xlnx,flush-fsync: 84 84 + type: boolean 85 85 + description: Tells which channel to Flush on Frame sync. 86 86 + 87 87 + xlnx,sg-length-width: 88 88 + $ref: /schemas/types.yaml#/definitions/uint32 89 89 + minimum: 8 90 90 + maximum: 26 91 91 + default: 23 92 92 + description: 93 93 + Width in bits of the length register as configured in hardware. 94 94 + 95 95 + xlnx,irq-delay: 96 96 + $ref: /schemas/types.yaml#/definitions/uint32 97 97 + minimum: 0 98 98 + maximum: 255 99 99 + description: 100 100 + Tells the interrupt delay timeout value. Valid range is from 0-255. 101 101 + Setting this value to zero disables the delay timer interrupt. 102 102 + 1 timeout interval = 125 * clock period of SG clock. 103 103 + 104 104 + xlnx,axistream-connected: 105 105 + type: boolean 106 106 + description: Tells whether DMA is connected to AXI stream IP. 107 107 + 108 108 + patternProperties: 109 109 + "^dma-channel(-mm2s|-s2mm)?$": 110 110 + type: object 111 111 + description: 112 112 + Should have at least one channel and can have up to two channels per 113 113 + device. This node specifies the properties of each DMA channel. 114 114 + 115 115 + properties: 116 116 + compatible: 117 117 + enum: 118 118 + - xlnx,axi-vdma-mm2s-channel 119 119 + - xlnx,axi-vdma-s2mm-channel 120 120 + - xlnx,axi-cdma-channel 121 121 + - xlnx,axi-dma-mm2s-channel 122 122 + - xlnx,axi-dma-s2mm-channel 123 123 + 124 124 + interrupts: 125 125 + maxItems: 1 126 126 + 127 127 + xlnx,datawidth: 128 128 + $ref: /schemas/types.yaml#/definitions/uint32 129 129 + enum: [32, 64, 128, 256, 512, 1024] 130 130 + description: Should contain the stream data width, take values {32,64...1024}. 131 131 + 132 132 + xlnx,include-dre: 133 133 + type: boolean 134 134 + description: Tells hardware is configured for Data Realignment Engine. 135 135 + 136 136 + xlnx,genlock-mode: 137 137 + type: boolean 138 138 + description: Tells Genlock synchronization is enabled/disabled in hardware. 139 139 + 140 140 + xlnx,enable-vert-flip: 141 141 + type: boolean 142 142 + description: 143 143 + Tells vertical flip is enabled/disabled in hardware(S2MM path). 144 144 + 145 145 + dma-channels: 146 146 + $ref: /schemas/types.yaml#/definitions/uint32 147 147 + description: Number of dma channels in child node. 148 148 + 149 149 + required: 150 150 + - compatible 151 151 + - interrupts 152 152 + - xlnx,datawidth 153 153 + 154 154 + additionalProperties: false 155 155 + 156 156 + allOf: 157 157 + - $ref: ../dma-controller.yaml# 158 158 + 159 159 + - if: 160 160 + properties: 161 161 + compatible: 162 162 + contains: 163 163 + const: xlnx,axi-vdma-1.00.a 164 164 + then: 165 165 + properties: 166 166 + clock-names: 167 167 + items: 168 168 + - const: s_axi_lite_aclk 169 169 + - const: m_axi_mm2s_aclk 170 170 + - const: m_axi_s2mm_aclk 171 171 + - const: m_axis_mm2s_aclk 172 172 + - const: s_axis_s2mm_aclk 173 173 + minItems: 1 174 174 + interrupts: false 175 175 + patternProperties: 176 176 + "^dma-channel(-mm2s|-s2mm)?$": 177 177 + properties: 178 178 + compatible: 179 179 + enum: 180 180 + - xlnx,axi-vdma-mm2s-channel 181 181 + - xlnx,axi-vdma-s2mm-channel 182 182 + required: 183 183 + - xlnx,num-fstores 184 184 + 185 185 + - if: 186 186 + properties: 187 187 + compatible: 188 188 + contains: 189 189 + const: xlnx,axi-cdma-1.00.a 190 190 + then: 191 191 + properties: 192 192 + clock-names: 193 193 + items: 194 194 + - const: s_axi_lite_aclk 195 195 + - const: m_axi_aclk 196 196 + interrupts: false 197 197 + patternProperties: 198 198 + "^dma-channel(-mm2s|-s2mm)?$": 199 199 + properties: 200 200 + compatible: 201 201 + enum: 202 202 + - xlnx,axi-cdma-channel 203 203 + 204 204 + - if: 205 205 + properties: 206 206 + compatible: 207 207 + contains: 208 208 + enum: 209 209 + - xlnx,axi-dma-1.00.a 210 210 + - xlnx,axi-mcdma-1.00.a 211 211 + then: 212 212 + properties: 213 213 + clock-names: 214 214 + items: 215 215 + - const: s_axi_lite_aclk 216 216 + - const: m_axi_mm2s_aclk 217 217 + - const: m_axi_s2mm_aclk 218 218 + - const: m_axi_sg_aclk 219 219 + minItems: 1 220 220 + patternProperties: 221 221 + "^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$": 222 222 + properties: 223 223 + compatible: 224 224 + enum: 225 225 + - xlnx,axi-dma-mm2s-channel 226 226 + - xlnx,axi-dma-s2mm-channel 227 227 + 228 228 + required: 229 229 + - "#dma-cells" 230 230 + - reg 231 231 + - xlnx,addrwidth 232 232 + - dma-ranges 233 233 + - clocks 234 234 + - clock-names 235 235 + 236 236 + unevaluatedProperties: false 237 237 + 238 238 + examples: 239 239 + - | 240 240 + #include <dt-bindings/interrupt-controller/arm-gic.h> 241 241 + 242 242 + dma-controller@40030000 { 243 243 + compatible = "xlnx,axi-vdma-1.00.a"; 244 244 + reg = <0x40030000 0x10000>; 245 245 + #dma-cells = <1>; 246 246 + #address-cells = <1>; 247 247 + #size-cells = <1>; 248 248 + dma-ranges = <0x0 0x0 0x40000000>; 249 249 + clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 250 250 + clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", 251 251 + "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", 252 252 + "s_axis_s2mm_aclk"; 253 253 + xlnx,num-fstores = <8>; 254 254 + xlnx,flush-fsync; 255 255 + xlnx,addrwidth = <32>; 256 256 + 257 257 + dma-channel-mm2s { 258 258 + compatible = "xlnx,axi-vdma-mm2s-channel"; 259 259 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 260 260 + xlnx,datawidth = <64>; 261 261 + }; 262 262 + 263 263 + dma-channel-s2mm { 264 264 + compatible = "xlnx,axi-vdma-s2mm-channel"; 265 265 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 266 266 + xlnx,datawidth = <64>; 267 267 + }; 268 268 + }; 269 269 + 270 270 + - | 271 271 + #include <dt-bindings/interrupt-controller/arm-gic.h> 272 272 + 273 273 + dma-controller@a4030000 { 274 274 + compatible = "xlnx,axi-dma-1.00.a"; 275 275 + reg = <0xa4030000 0x10000>; 276 276 + #dma-cells = <1>; 277 277 + #address-cells = <1>; 278 278 + #size-cells = <1>; 279 279 + dma-ranges = <0x0 0x0 0x40000000>; 280 280 + clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>; 281 281 + clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", 282 282 + "m_axi_s2mm_aclk", "m_axi_sg_aclk"; 283 283 + xlnx,addrwidth = <32>; 284 284 + xlnx,sg-length-width = <14>; 285 285 + 286 286 + dma-channel-mm2s { 287 287 + compatible = "xlnx,axi-dma-mm2s-channel"; 288 288 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 289 289 + xlnx,datawidth = <64>; 290 290 + xlnx,include-dre; 291 291 + }; 292 292 + 293 293 + dma-channel-s2mm { 294 294 + compatible = "xlnx,axi-dma-s2mm-channel"; 295 295 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 296 296 + xlnx,datawidth = <64>; 297 297 + xlnx,include-dre; 298 298 + }; 299 299 + };

+12 -2

MAINTAINERS

reviewed

··· 15039 15039 F: Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml 15040 15040 F: drivers/gpio/gpio-loongson-64bit.c 15041 15041 15042 15042 - LOONGSON-2 APB DMA DRIVER 15042 15042 + LOONGSON-2 DMA DRIVER 15043 15043 M: Binbin Zhou <zhoubinbin@loongson.cn> 15044 15044 L: dmaengine@vger.kernel.org 15045 15045 S: Maintained 15046 15046 + F: Documentation/devicetree/bindings/dma/loongson,ls2k0300-dma.yaml 15046 15047 F: Documentation/devicetree/bindings/dma/loongson,ls2x-apbdma.yaml 15047 15047 - F: drivers/dma/loongson2-apb-dma.c 15048 15048 + F: drivers/dma/loongson/loongson2-apb-cmc-dma.c 15049 15049 + F: drivers/dma/loongson/loongson2-apb-dma.c 15048 15050 15049 15051 LOONGSON LS2X I2C DRIVER 15050 15052 M: Binbin Zhou <zhoubinbin@loongson.cn> ··· 17834 17832 F: arch/mips/configs/loongson1_defconfig 17835 17833 F: arch/mips/loongson32/ 17836 17834 F: drivers/*/*loongson1* 17835 17835 + F: drivers/dma/loongson/loongson1-apb-dma.c 17837 17836 F: drivers/mtd/nand/raw/loongson-nand-controller.c 17838 17837 F: drivers/net/ethernet/stmicro/stmmac/dwmac-loongson1.c 17839 17838 F: sound/soc/loongson/loongson1_ac97.c ··· 25726 25723 S: Supported 25727 25724 F: include/net/switchdev.h 25728 25725 F: net/switchdev/ 25726 25726 + 25727 25727 + SWITCHTEC DMA DRIVER 25728 25728 + M: Kelvin Cao <kelvin.cao@microchip.com> 25729 25729 + M: Logan Gunthorpe <logang@deltatee.com> 25730 25730 + L: dmaengine@vger.kernel.org 25731 25731 + S: Maintained 25732 25732 + F: drivers/dma/switchtec_dma.c 25729 25733 25730 25734 SY8106A REGULATOR DRIVER 25731 25735 M: Icenowy Zheng <icenowy@aosc.io>

+12 -24

drivers/dma/Kconfig

reviewed

··· 376 376 Support the DMA engine for Hisilicon K3 platform 377 377 devices. 378 378 379 379 - config LOONGSON1_APB_DMA 380 380 - tristate "Loongson1 APB DMA support" 381 381 - depends on MACH_LOONGSON32 || COMPILE_TEST 382 382 - select DMA_ENGINE 383 383 - select DMA_VIRTUAL_CHANNELS 384 384 - help 385 385 - This selects support for the APB DMA controller in Loongson1 SoCs, 386 386 - which is required by Loongson1 NAND and audio support. 387 387 - 388 388 - config LOONGSON2_APB_DMA 389 389 - tristate "Loongson2 APB DMA support" 390 390 - depends on LOONGARCH || COMPILE_TEST 391 391 - select DMA_ENGINE 392 392 - select DMA_VIRTUAL_CHANNELS 393 393 - help 394 394 - Support for the Loongson2 APB DMA controller driver. The 395 395 - DMA controller is having single DMA channel which can be 396 396 - configured for different peripherals like audio, nand, sdio 397 397 - etc which is in APB bus. 398 398 - 399 399 - This DMA controller transfers data from memory to peripheral fifo. 400 400 - It does not support memory to memory data transfer. 401 401 - 402 379 config LPC18XX_DMAMUX 403 380 bool "NXP LPC18xx/43xx DMA MUX for PL080" 404 381 depends on ARCH_LPC18XX || COMPILE_TEST ··· 482 505 platforms. 483 506 484 507 config MXS_DMA 485 485 - bool "MXS DMA support" 508 508 + tristate "MXS DMA support" 486 509 depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST 487 510 select STMP_DEVICE 488 511 select DMA_ENGINE ··· 586 609 select DMA_VIRTUAL_CHANNELS 587 610 help 588 611 Enable support for the on-chip DMA controller on Spreadtrum platform. 612 612 + 613 613 + config SWITCHTEC_DMA 614 614 + tristate "Switchtec PSX/PFX Switch DMA Engine Support" 615 615 + depends on PCI 616 616 + select DMA_ENGINE 617 617 + help 618 618 + Some Switchtec PSX/PFX PCIe Switches support additional DMA engines. 619 619 + These are exposed via an extra function on the switch's upstream 620 620 + port. 589 621 590 622 config TXX9_DMAC 591 623 tristate "Toshiba TXx9 SoC DMA support" ··· 759 773 source "drivers/dma/fsl-dpaa2-qdma/Kconfig" 760 774 761 775 source "drivers/dma/lgm/Kconfig" 776 776 + 777 777 + source "drivers/dma/loongson/Kconfig" 762 778 763 779 source "drivers/dma/stm32/Kconfig" 764 780

+2 -2

drivers/dma/Makefile

reviewed

··· 49 49 obj-$(CONFIG_INTEL_IOATDMA) += ioat/ 50 50 obj-y += idxd/ 51 51 obj-$(CONFIG_K3_DMA) += k3dma.o 52 52 - obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o 53 53 - obj-$(CONFIG_LOONGSON2_APB_DMA) += loongson2-apb-dma.o 54 52 obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o 55 53 obj-$(CONFIG_LPC32XX_DMAMUX) += lpc32xx-dmamux.o 56 54 obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o ··· 72 74 obj-$(CONFIG_SOPHGO_CV1800B_DMAMUX) += cv1800b-dmamux.o 73 75 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o 74 76 obj-$(CONFIG_SPRD_DMA) += sprd-dma.o 77 77 + obj-$(CONFIG_SWITCHTEC_DMA) += switchtec_dma.o 75 78 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o 76 79 obj-$(CONFIG_TEGRA186_GPC_DMA) += tegra186-gpc-dma.o 77 80 obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o ··· 86 87 obj-$(CONFIG_INTEL_LDMA) += lgm/ 87 88 88 89 obj-y += amd/ 90 90 + obj-y += loongson/ 89 91 obj-y += mediatek/ 90 92 obj-y += qcom/ 91 93 obj-y += stm32/

+149 -21

drivers/dma/dma-axi-dmac.c

reviewed

··· 134 134 struct axi_dmac_chan *chan; 135 135 136 136 bool cyclic; 137 137 + bool cyclic_eot; 137 138 bool have_partial_xfer; 138 139 139 140 unsigned int num_submitted; ··· 163 162 bool hw_cyclic; 164 163 bool hw_2d; 165 164 bool hw_sg; 165 165 + bool hw_cyclic_hotfix; 166 166 }; 167 167 168 168 struct axi_dmac { ··· 229 227 return true; 230 228 } 231 229 230 230 + static struct axi_dmac_desc *axi_dmac_active_desc(struct axi_dmac_chan *chan) 231 231 + { 232 232 + return list_first_entry_or_null(&chan->active_descs, 233 233 + struct axi_dmac_desc, vdesc.node); 234 234 + } 235 235 + 236 236 + static struct axi_dmac_desc *axi_dmac_get_next_desc(struct axi_dmac *dmac, 237 237 + struct axi_dmac_chan *chan) 238 238 + { 239 239 + struct axi_dmac_desc *active = axi_dmac_active_desc(chan); 240 240 + struct virt_dma_desc *vdesc; 241 241 + struct axi_dmac_desc *desc; 242 242 + unsigned int val; 243 243 + 244 244 + /* 245 245 + * Just play safe and ignore any SOF if we have an active cyclic transfer 246 246 + * flagged to end. We'll start it as soon as the current cyclic one ends. 247 247 + */ 248 248 + if (active && active->cyclic_eot) 249 249 + return NULL; 250 250 + 251 251 + /* 252 252 + * It means a SW cyclic transfer is in place so we should just return 253 253 + * the same descriptor. SW cyclic transfer termination is handled 254 254 + * in axi_dmac_transfer_done(). 255 255 + */ 256 256 + if (chan->next_desc) 257 257 + return chan->next_desc; 258 258 + 259 259 + vdesc = vchan_next_desc(&chan->vchan); 260 260 + if (!vdesc) 261 261 + return NULL; 262 262 + 263 263 + if (active && active->cyclic && !(vdesc->tx.flags & DMA_PREP_LOAD_EOT)) { 264 264 + struct device *dev = chan_to_axi_dmac(chan)->dma_dev.dev; 265 265 + 266 266 + dev_warn(dev, "Discarding non EOT transfer after cyclic\n"); 267 267 + list_del(&vdesc->node); 268 268 + return NULL; 269 269 + } 270 270 + 271 271 + list_move_tail(&vdesc->node, &chan->active_descs); 272 272 + desc = to_axi_dmac_desc(vdesc); 273 273 + chan->next_desc = desc; 274 274 + 275 275 + if (!active || !active->cyclic) 276 276 + return desc; 277 277 + 278 278 + active->cyclic_eot = true; 279 279 + 280 280 + if (chan->hw_sg) { 281 281 + unsigned long flags = AXI_DMAC_HW_FLAG_IRQ | AXI_DMAC_HW_FLAG_LAST; 282 282 + /* 283 283 + * Let's then stop the current cyclic transfer by making sure we 284 284 + * get an EOT interrupt and to open the cyclic loop by marking 285 285 + * the last segment. 286 286 + */ 287 287 + active->sg[active->num_sgs - 1].hw->flags = flags; 288 288 + return NULL; 289 289 + } 290 290 + 291 291 + /* 292 292 + * Clear the cyclic bit if there's no Scatter-Gather HW so that we get 293 293 + * at the end of the transfer. 294 294 + */ 295 295 + val = axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS); 296 296 + val &= ~AXI_DMAC_FLAG_CYCLIC; 297 297 + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, val); 298 298 + 299 299 + return NULL; 300 300 + } 301 301 + 232 302 static void axi_dmac_start_transfer(struct axi_dmac_chan *chan) 233 303 { 234 304 struct axi_dmac *dmac = chan_to_axi_dmac(chan); 235 235 - struct virt_dma_desc *vdesc; 236 305 struct axi_dmac_desc *desc; 237 306 struct axi_dmac_sg *sg; 238 307 unsigned int flags = 0; 239 308 unsigned int val; 240 309 310 310 + desc = axi_dmac_get_next_desc(dmac, chan); 311 311 + if (!desc) 312 312 + return; 313 313 + 241 314 val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER); 242 315 if (val) /* Queue is full, wait for the next SOT IRQ */ 243 316 return; 244 317 245 245 - desc = chan->next_desc; 246 246 - 247 247 - if (!desc) { 248 248 - vdesc = vchan_next_desc(&chan->vchan); 249 249 - if (!vdesc) 250 250 - return; 251 251 - list_move_tail(&vdesc->node, &chan->active_descs); 252 252 - desc = to_axi_dmac_desc(vdesc); 253 253 - chan->next_desc = desc; 254 254 - } 255 318 sg = &desc->sg[desc->num_submitted]; 256 319 257 320 /* Already queued in cyclic mode. Wait for it to finish */ ··· 358 291 * call, enable hw cyclic mode to avoid unnecessary interrupts. 359 292 */ 360 293 if (chan->hw_cyclic && desc->cyclic && !desc->vdesc.tx.callback) { 361 361 - if (chan->hw_sg) 294 294 + if (chan->hw_sg) { 362 295 desc->sg[desc->num_sgs - 1].hw->flags &= ~AXI_DMAC_HW_FLAG_IRQ; 363 363 - else if (desc->num_sgs == 1) 296 296 + } else if (desc->num_sgs == 1) { 297 297 + chan->next_desc = NULL; 364 298 flags |= AXI_DMAC_FLAG_CYCLIC; 299 299 + } 365 300 } 366 301 367 302 if (chan->hw_partial_xfer) ··· 379 310 } 380 311 axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags); 381 312 axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1); 382 382 - } 383 383 - 384 384 - static struct axi_dmac_desc *axi_dmac_active_desc(struct axi_dmac_chan *chan) 385 385 - { 386 386 - return list_first_entry_or_null(&chan->active_descs, 387 387 - struct axi_dmac_desc, vdesc.node); 388 313 } 389 314 390 315 static inline unsigned int axi_dmac_total_sg_bytes(struct axi_dmac_chan *chan, ··· 461 398 } 462 399 } 463 400 401 401 + static bool axi_dmac_handle_cyclic_eot(struct axi_dmac_chan *chan, 402 402 + struct axi_dmac_desc *active) 403 403 + { 404 404 + struct device *dev = chan_to_axi_dmac(chan)->dma_dev.dev; 405 405 + struct virt_dma_desc *vdesc; 406 406 + 407 407 + /* wrap around */ 408 408 + active->num_completed = 0; 409 409 + 410 410 + if (active->cyclic_eot) { 411 411 + /* 412 412 + * It means an HW cyclic transfer was marked to stop. And we 413 413 + * know we have something to schedule, so start the next 414 414 + * transfer now the cyclic one is done. 415 415 + */ 416 416 + list_del(&active->vdesc.node); 417 417 + vchan_cookie_complete(&active->vdesc); 418 418 + 419 419 + if (chan->hw_cyclic_hotfix) { 420 420 + struct axi_dmac *dmac = chan_to_axi_dmac(chan); 421 421 + /* 422 422 + * In older IP cores, ending a cyclic transfer by clearing 423 423 + * the CYCLIC flag does not guarantee a graceful end. 424 424 + * It can happen that some data (of the next frame) is 425 425 + * already prefetched and will be wrongly visible in the 426 426 + * next transfer. To workaround this, we need to reenable 427 427 + * the core so everything is flushed. Newer cores handles 428 428 + * this correctly and do not require this "hotfix". The 429 429 + * SG IP also does not require this. 430 430 + */ 431 431 + dev_dbg(dev, "HW cyclic hotfix\n"); 432 432 + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0); 433 433 + axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE); 434 434 + } 435 435 + 436 436 + return true; 437 437 + } 438 438 + 439 439 + vdesc = vchan_next_desc(&chan->vchan); 440 440 + if (!vdesc) 441 441 + return false; 442 442 + if (!(vdesc->tx.flags & DMA_PREP_LOAD_EOT)) { 443 443 + dev_warn(dev, "Discarding non EOT transfer after cyclic\n"); 444 444 + list_del(&vdesc->node); 445 445 + return false; 446 446 + } 447 447 + 448 448 + /* then let's end the cyclic transfer */ 449 449 + chan->next_desc = NULL; 450 450 + list_del(&active->vdesc.node); 451 451 + vchan_cookie_complete(&active->vdesc); 452 452 + 453 453 + return true; 454 454 + } 455 455 + 464 456 static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan, 465 457 unsigned int completed_transfers) 466 458 { ··· 534 416 if (chan->hw_sg) { 535 417 if (active->cyclic) { 536 418 vchan_cyclic_callback(&active->vdesc); 419 419 + start_next = axi_dmac_handle_cyclic_eot(chan, active); 537 420 } else { 538 421 list_del(&active->vdesc.node); 539 422 vchan_cookie_complete(&active->vdesc); ··· 564 445 if (active->num_completed == active->num_sgs || 565 446 sg->partial_len) { 566 447 if (active->cyclic) { 567 567 - active->num_completed = 0; /* wrap around */ 448 448 + /* keep start_next as is, if already true... */ 449 449 + start_next |= axi_dmac_handle_cyclic_eot(chan, active); 568 450 } else { 569 451 list_del(&active->vdesc.node); 570 452 vchan_cookie_complete(&active->vdesc); ··· 777 657 vecs[i].len, dsg); 778 658 } 779 659 780 780 - desc->cyclic = false; 660 660 + desc->cyclic = flags & DMA_PREP_REPEAT; 661 661 + if (desc->cyclic) { 662 662 + /* Chain the last descriptor to the first, and remove its "last" flag */ 663 663 + desc->sg[num_sgs - 1].hw->flags &= ~AXI_DMAC_HW_FLAG_LAST; 664 664 + desc->sg[num_sgs - 1].hw->next_sg_addr = desc->sg[0].hw_phys; 665 665 + } 781 666 782 667 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 783 668 } ··· 1177 1052 } else { 1178 1053 chan->length_align_mask = chan->address_align_mask; 1179 1054 } 1055 1055 + 1056 1056 + if (version < ADI_AXI_PCORE_VER(4, 6, 0) && !chan->hw_sg) 1057 1057 + chan->hw_cyclic_hotfix = true; 1180 1058 1181 1059 return 0; 1182 1060 }

+26 -24

drivers/dma/dmaengine.c

reviewed

··· 31 31 32 32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 33 34 34 - #include <linux/platform_device.h> 35 35 - #include <linux/dma-mapping.h> 36 36 - #include <linux/init.h> 37 37 - #include <linux/module.h> 38 38 - #include <linux/mm.h> 39 39 - #include <linux/device.h> 40 40 - #include <linux/dmaengine.h> 41 41 - #include <linux/hardirq.h> 42 42 - #include <linux/spinlock.h> 43 43 - #include <linux/of.h> 44 44 - #include <linux/property.h> 45 45 - #include <linux/percpu.h> 46 46 - #include <linux/rcupdate.h> 47 47 - #include <linux/mutex.h> 48 48 - #include <linux/jiffies.h> 49 49 - #include <linux/rculist.h> 50 50 - #include <linux/idr.h> 51 51 - #include <linux/slab.h> 52 34 #include <linux/acpi.h> 53 35 #include <linux/acpi_dma.h> 54 54 - #include <linux/of_dma.h> 36 36 + #include <linux/device.h> 37 37 + #include <linux/dma-mapping.h> 38 38 + #include <linux/dmaengine.h> 39 39 + #include <linux/hardirq.h> 40 40 + #include <linux/idr.h> 41 41 + #include <linux/init.h> 42 42 + #include <linux/jiffies.h> 55 43 #include <linux/mempool.h> 44 44 + #include <linux/mm.h> 45 45 + #include <linux/module.h> 46 46 + #include <linux/mutex.h> 56 47 #include <linux/numa.h> 48 48 + #include <linux/of.h> 49 49 + #include <linux/of_dma.h> 50 50 + #include <linux/percpu.h> 51 51 + #include <linux/platform_device.h> 52 52 + #include <linux/property.h> 53 53 + #include <linux/rculist.h> 54 54 + #include <linux/rcupdate.h> 55 55 + #include <linux/slab.h> 56 56 + #include <linux/spinlock.h> 57 57 58 58 #include "dmaengine.h" 59 59 ··· 765 765 mutex_lock(&dma_list_mutex); 766 766 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { 767 767 /* Finds a DMA controller with matching device node */ 768 768 - if (np && device->dev->of_node && np != device->dev->of_node) 768 768 + if (np && !device_match_of_node(device->dev, np)) 769 769 continue; 770 770 771 771 chan = find_candidate(device, mask, fn, fn_param); ··· 943 943 944 944 struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name) 945 945 { 946 946 - struct dma_chan *chan = dma_request_chan(dev, name); 947 947 - int ret = 0; 946 946 + struct dma_chan *chan; 947 947 + int ret; 948 948 949 949 - if (!IS_ERR(chan)) 950 950 - ret = devm_add_action_or_reset(dev, dmaenginem_release_channel, chan); 949 949 + chan = dma_request_chan(dev, name); 950 950 + if (IS_ERR(chan)) 951 951 + return chan; 951 952 953 953 + ret = devm_add_action_or_reset(dev, dmaenginem_release_channel, chan); 952 954 if (ret) 953 955 return ERR_PTR(ret); 954 956

+29 -13

drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

reviewed

··· 50 50 #define AXI_DMA_FLAG_HAS_APB_REGS BIT(0) 51 51 #define AXI_DMA_FLAG_HAS_RESETS BIT(1) 52 52 #define AXI_DMA_FLAG_USE_CFG2 BIT(2) 53 53 + #define AXI_DMA_FLAG_ARG0_AS_CHAN BIT(3) 53 54 54 55 static inline void 55 56 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) ··· 343 342 kfree(desc); 344 343 atomic_sub(descs_put, &chan->descs_allocated); 345 344 dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", 346 346 - axi_chan_name(chan), descs_put, 347 347 - atomic_read(&chan->descs_allocated)); 345 345 + axi_chan_name(chan), descs_put, 346 346 + atomic_read(&chan->descs_allocated)); 348 347 } 349 348 350 349 static void vchan_desc_put(struct virt_dma_desc *vdesc) ··· 354 353 355 354 static enum dma_status 356 355 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, 357 357 - struct dma_tx_state *txstate) 356 356 + struct dma_tx_state *txstate) 358 357 { 359 358 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 360 359 struct virt_dma_desc *vdesc; ··· 420 419 421 420 iowrite32(val, chan->chip->apb_regs + offset); 422 421 } 422 422 + 423 423 /* Called in chan locked context */ 424 424 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, 425 425 struct axi_dma_desc *first) ··· 493 491 494 492 desc = vd_to_axi_desc(vd); 495 493 dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan), 496 496 - vd->tx.cookie); 494 494 + vd->tx.cookie); 497 495 axi_chan_block_xfer_start(chan, desc); 498 496 } 499 497 ··· 594 592 (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 595 593 reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 596 594 lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 597 597 - 598 598 - return; 599 595 } 600 596 601 597 /* ··· 1162 1162 axi_chan_irq_clear(chan, status); 1163 1163 1164 1164 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n", 1165 1165 - axi_chan_name(chan), i, status); 1165 1165 + axi_chan_name(chan), i, status); 1166 1166 1167 1167 if (status & DWAXIDMAC_IRQ_ALL_ERR) 1168 1168 axi_chan_handle_err(chan, status); ··· 1358 1358 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec, 1359 1359 struct of_dma *ofdma) 1360 1360 { 1361 1361 + unsigned int handshake = dma_spec->args[0]; 1361 1362 struct dw_axi_dma *dw = ofdma->of_dma_data; 1362 1362 - struct axi_dma_chan *chan; 1363 1363 + struct axi_dma_chan *chan = NULL; 1363 1364 struct dma_chan *dchan; 1364 1365 1365 1365 - dchan = dma_get_any_slave_channel(&dw->dma); 1366 1366 + if (dw->hdata->use_handshake_as_channel_number) { 1367 1367 + if (handshake >= dw->hdata->nr_channels) 1368 1368 + return NULL; 1369 1369 + 1370 1370 + chan = &dw->chan[handshake]; 1371 1371 + dchan = dma_get_slave_channel(&chan->vc.chan); 1372 1372 + } else { 1373 1373 + dchan = dma_get_any_slave_channel(&dw->dma); 1374 1374 + } 1375 1375 + 1366 1376 if (!dchan) 1367 1377 return NULL; 1368 1378 1369 1369 - chan = dchan_to_axi_dma_chan(dchan); 1370 1370 - chan->hw_handshake_num = dma_spec->args[0]; 1379 1379 + if (!chan) 1380 1380 + chan = dchan_to_axi_dma_chan(dchan); 1381 1381 + chan->hw_handshake_num = handshake; 1371 1382 return dchan; 1372 1383 } 1373 1384 ··· 1462 1451 if (chip->irq[i] < 0) 1463 1452 return chip->irq[i]; 1464 1453 ret = devm_request_irq(chip->dev, chip->irq[i], dw_axi_dma_interrupt, 1465 1465 - IRQF_SHARED, KBUILD_MODNAME, chip); 1454 1454 + IRQF_SHARED, KBUILD_MODNAME, chip); 1466 1455 if (ret < 0) 1467 1456 return ret; 1468 1457 } ··· 1516 1505 if (ret) 1517 1506 return ret; 1518 1507 } 1508 1508 + 1509 1509 + chip->dw->hdata->use_handshake_as_channel_number = !!(flags & AXI_DMA_FLAG_ARG0_AS_CHAN); 1519 1510 1520 1511 chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2); 1521 1512 ··· 1658 1645 of_dma_controller_free(chip->dev->of_node); 1659 1646 1660 1647 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, 1661 1661 - vc.chan.device_node) { 1648 1648 + vc.chan.device_node) { 1662 1649 list_del(&chan->vc.chan.device_node); 1663 1650 tasklet_kill(&chan->vc.task); 1664 1651 } ··· 1674 1661 }, { 1675 1662 .compatible = "intel,kmb-axi-dma", 1676 1663 .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS, 1664 1664 + }, { 1665 1665 + .compatible = "sophgo,cv1800b-axi-dma", 1666 1666 + .data = (void *)AXI_DMA_FLAG_ARG0_AS_CHAN, 1677 1667 }, { 1678 1668 .compatible = "starfive,jh7110-axi-dma", 1679 1669 .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),

+1

drivers/dma/dw-axi-dmac/dw-axi-dmac.h

reviewed

··· 34 34 bool reg_map_8_channels; 35 35 bool restrict_axi_burst_len; 36 36 bool use_cfg2; 37 37 + bool use_handshake_as_channel_number; 37 38 }; 38 39 39 40 struct axi_dma_chan {

+168 -6

drivers/dma/dw-edma/dw-edma-core.c

reviewed

··· 223 223 struct dma_slave_config *config) 224 224 { 225 225 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan); 226 226 + bool cfg_non_ll; 227 227 + int non_ll = 0; 228 228 + 229 229 + chan->non_ll = false; 230 230 + if (chan->dw->chip->mf == EDMA_MF_HDMA_NATIVE) { 231 231 + if (config->peripheral_config && 232 232 + config->peripheral_size != sizeof(int)) { 233 233 + dev_err(dchan->device->dev, 234 234 + "config param peripheral size mismatch\n"); 235 235 + return -EINVAL; 236 236 + } 237 237 + 238 238 + /* 239 239 + * When there is no valid LLP base address available then the 240 240 + * default DMA ops will use the non-LL mode. 241 241 + * 242 242 + * Cases where LL mode is enabled and client wants to use the 243 243 + * non-LL mode then also client can do so via providing the 244 244 + * peripheral_config param. 245 245 + */ 246 246 + cfg_non_ll = chan->dw->chip->cfg_non_ll; 247 247 + if (config->peripheral_config) { 248 248 + non_ll = *(int *)config->peripheral_config; 249 249 + 250 250 + if (cfg_non_ll && !non_ll) { 251 251 + dev_err(dchan->device->dev, "invalid configuration\n"); 252 252 + return -EINVAL; 253 253 + } 254 254 + } 255 255 + 256 256 + if (cfg_non_ll || non_ll) 257 257 + chan->non_ll = true; 258 258 + } else if (config->peripheral_config) { 259 259 + dev_err(dchan->device->dev, 260 260 + "peripheral config param applicable only for HDMA\n"); 261 261 + return -EINVAL; 262 262 + } 226 263 227 264 memcpy(&chan->config, config, sizeof(*config)); 228 265 chan->configured = true; ··· 395 358 struct dw_edma_desc *desc; 396 359 u64 src_addr, dst_addr; 397 360 size_t fsz = 0; 361 361 + u32 bursts_max; 398 362 u32 cnt = 0; 399 363 int i; 400 364 ··· 453 415 return NULL; 454 416 } 455 417 418 418 + /* 419 419 + * For non-LL mode, only a single burst can be handled 420 420 + * in a single chunk unlike LL mode where multiple bursts 421 421 + * can be configured in a single chunk. 422 422 + */ 423 423 + bursts_max = chan->non_ll ? 1 : chan->ll_max; 424 424 + 456 425 desc = dw_edma_alloc_desc(chan); 457 426 if (unlikely(!desc)) 458 427 goto err_alloc; ··· 495 450 if (xfer->type == EDMA_XFER_SCATTER_GATHER && !sg) 496 451 break; 497 452 498 498 - if (chunk->bursts_alloc == chan->ll_max) { 453 453 + if (chunk->bursts_alloc == bursts_max) { 499 454 chunk = dw_edma_alloc_chunk(desc); 500 455 if (unlikely(!chunk)) 501 456 goto err_alloc; ··· 708 663 chan->status = EDMA_ST_IDLE; 709 664 } 710 665 711 711 - static inline irqreturn_t dw_edma_interrupt_write(int irq, void *data) 666 666 + static void dw_edma_emul_irq_ack(struct irq_data *d) 667 667 + { 668 668 + struct dw_edma *dw = irq_data_get_irq_chip_data(d); 669 669 + 670 670 + dw_edma_core_ack_emulated_irq(dw); 671 671 + } 672 672 + 673 673 + /* 674 674 + * irq_chip implementation for interrupt-emulation doorbells. 675 675 + * 676 676 + * The emulated source has no mask/unmask mechanism. With handle_level_irq(), 677 677 + * the flow is therefore: 678 678 + * 1) .irq_ack() deasserts the source 679 679 + * 2) registered handlers (if any) are dispatched 680 680 + * Since deassertion is already done in .irq_ack(), handlers do not need to take 681 681 + * care of it, hence IRQCHIP_ONESHOT_SAFE. 682 682 + */ 683 683 + static struct irq_chip dw_edma_emul_irqchip = { 684 684 + .name = "dw-edma-emul", 685 685 + .irq_ack = dw_edma_emul_irq_ack, 686 686 + .flags = IRQCHIP_ONESHOT_SAFE | IRQCHIP_SKIP_SET_WAKE, 687 687 + }; 688 688 + 689 689 + static int dw_edma_emul_irq_alloc(struct dw_edma *dw) 690 690 + { 691 691 + struct dw_edma_chip *chip = dw->chip; 692 692 + int virq; 693 693 + 694 694 + chip->db_irq = 0; 695 695 + chip->db_offset = ~0; 696 696 + 697 697 + /* 698 698 + * Only meaningful when the core provides the deassert sequence 699 699 + * for interrupt emulation. 700 700 + */ 701 701 + if (!dw->core->ack_emulated_irq) 702 702 + return 0; 703 703 + 704 704 + /* 705 705 + * Allocate a single, requestable Linux virtual IRQ number. 706 706 + * Use >= 1 so that 0 can remain a "not available" sentinel. 707 707 + */ 708 708 + virq = irq_alloc_desc(NUMA_NO_NODE); 709 709 + if (virq < 0) 710 710 + return virq; 711 711 + 712 712 + irq_set_chip_and_handler(virq, &dw_edma_emul_irqchip, handle_level_irq); 713 713 + irq_set_chip_data(virq, dw); 714 714 + irq_set_noprobe(virq); 715 715 + 716 716 + chip->db_irq = virq; 717 717 + chip->db_offset = dw_edma_core_db_offset(dw); 718 718 + 719 719 + return 0; 720 720 + } 721 721 + 722 722 + static void dw_edma_emul_irq_free(struct dw_edma *dw) 723 723 + { 724 724 + struct dw_edma_chip *chip = dw->chip; 725 725 + 726 726 + if (!chip) 727 727 + return; 728 728 + if (chip->db_irq <= 0) 729 729 + return; 730 730 + 731 731 + irq_free_descs(chip->db_irq, 1); 732 732 + chip->db_irq = 0; 733 733 + chip->db_offset = ~0; 734 734 + } 735 735 + 736 736 + static inline irqreturn_t dw_edma_interrupt_emulated(void *data) 737 737 + { 738 738 + struct dw_edma_irq *dw_irq = data; 739 739 + struct dw_edma *dw = dw_irq->dw; 740 740 + int db_irq = dw->chip->db_irq; 741 741 + 742 742 + if (db_irq > 0) { 743 743 + /* 744 744 + * Interrupt emulation may assert the IRQ line without updating the 745 745 + * normal DONE/ABORT status bits. With a shared IRQ handler we 746 746 + * cannot reliably detect such events by status registers alone, so 747 747 + * always perform the core-specific deassert sequence. 748 748 + */ 749 749 + generic_handle_irq(db_irq); 750 750 + return IRQ_HANDLED; 751 751 + } 752 752 + return IRQ_NONE; 753 753 + } 754 754 + 755 755 + static inline irqreturn_t dw_edma_interrupt_write_inner(int irq, void *data) 712 756 { 713 757 struct dw_edma_irq *dw_irq = data; 714 758 ··· 806 672 dw_edma_abort_interrupt); 807 673 } 808 674 809 809 - static inline irqreturn_t dw_edma_interrupt_read(int irq, void *data) 675 675 + static inline irqreturn_t dw_edma_interrupt_read_inner(int irq, void *data) 810 676 { 811 677 struct dw_edma_irq *dw_irq = data; 812 678 ··· 815 681 dw_edma_abort_interrupt); 816 682 } 817 683 818 818 - static irqreturn_t dw_edma_interrupt_common(int irq, void *data) 684 684 + static inline irqreturn_t dw_edma_interrupt_write(int irq, void *data) 819 685 { 820 686 irqreturn_t ret = IRQ_NONE; 821 687 822 822 - ret |= dw_edma_interrupt_write(irq, data); 823 823 - ret |= dw_edma_interrupt_read(irq, data); 688 688 + ret |= dw_edma_interrupt_write_inner(irq, data); 689 689 + ret |= dw_edma_interrupt_emulated(data); 690 690 + 691 691 + return ret; 692 692 + } 693 693 + 694 694 + static inline irqreturn_t dw_edma_interrupt_read(int irq, void *data) 695 695 + { 696 696 + irqreturn_t ret = IRQ_NONE; 697 697 + 698 698 + ret |= dw_edma_interrupt_read_inner(irq, data); 699 699 + ret |= dw_edma_interrupt_emulated(data); 700 700 + 701 701 + return ret; 702 702 + } 703 703 + 704 704 + static inline irqreturn_t dw_edma_interrupt_common(int irq, void *data) 705 705 + { 706 706 + irqreturn_t ret = IRQ_NONE; 707 707 + 708 708 + ret |= dw_edma_interrupt_write_inner(irq, data); 709 709 + ret |= dw_edma_interrupt_read_inner(irq, data); 710 710 + ret |= dw_edma_interrupt_emulated(data); 824 711 825 712 return ret; 826 713 } ··· 1132 977 if (err) 1133 978 return err; 1134 979 980 980 + /* Allocate a dedicated virtual IRQ for interrupt-emulation doorbells */ 981 981 + err = dw_edma_emul_irq_alloc(dw); 982 982 + if (err) 983 983 + dev_warn(dev, "Failed to allocate emulation IRQ: %d\n", err); 984 984 + 1135 985 /* Setup write/read channels */ 1136 986 err = dw_edma_channel_setup(dw, wr_alloc, rd_alloc); 1137 987 if (err) ··· 1152 992 err_irq_free: 1153 993 for (i = (dw->nr_irqs - 1); i >= 0; i--) 1154 994 free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]); 995 995 + dw_edma_emul_irq_free(dw); 1155 996 1156 997 return err; 1157 998 } ··· 1175 1014 /* Free irqs */ 1176 1015 for (i = (dw->nr_irqs - 1); i >= 0; i--) 1177 1016 free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]); 1017 1017 + dw_edma_emul_irq_free(dw); 1178 1018 1179 1019 /* Deregister eDMA device */ 1180 1020 dma_async_device_unregister(&dw->dma);

+18

drivers/dma/dw-edma/dw-edma-core.h

reviewed

··· 86 86 u8 configured; 87 87 88 88 struct dma_slave_config config; 89 89 + bool non_ll; 89 90 }; 90 91 91 92 struct dw_edma_irq { ··· 127 126 void (*start)(struct dw_edma_chunk *chunk, bool first); 128 127 void (*ch_config)(struct dw_edma_chan *chan); 129 128 void (*debugfs_on)(struct dw_edma *dw); 129 129 + void (*ack_emulated_irq)(struct dw_edma *dw); 130 130 + resource_size_t (*db_offset)(struct dw_edma *dw); 130 131 }; 131 132 132 133 struct dw_edma_sg { ··· 207 204 void dw_edma_core_debugfs_on(struct dw_edma *dw) 208 205 { 209 206 dw->core->debugfs_on(dw); 207 207 + } 208 208 + 209 209 + static inline int dw_edma_core_ack_emulated_irq(struct dw_edma *dw) 210 210 + { 211 211 + if (!dw->core->ack_emulated_irq) 212 212 + return -EOPNOTSUPP; 213 213 + 214 214 + dw->core->ack_emulated_irq(dw); 215 215 + return 0; 216 216 + } 217 217 + 218 218 + static inline resource_size_t 219 219 + dw_edma_core_db_offset(struct dw_edma *dw) 220 220 + { 221 221 + return dw->core->db_offset(dw); 210 222 } 211 223 212 224 #endif /* _DW_EDMA_CORE_H */

+200 -20

drivers/dma/dw-edma/dw-edma-pcie.c

reviewed

··· 14 14 #include <linux/pci-epf.h> 15 15 #include <linux/msi.h> 16 16 #include <linux/bitfield.h> 17 17 + #include <linux/sizes.h> 17 18 18 19 #include "dw-edma-core.h" 19 20 20 20 - #define DW_PCIE_VSEC_DMA_ID 0x6 21 21 - #define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) 22 22 - #define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) 23 23 - #define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) 24 24 - #define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) 21 21 + /* Synopsys */ 22 22 + #define DW_PCIE_SYNOPSYS_VSEC_DMA_ID 0x6 23 23 + #define DW_PCIE_SYNOPSYS_VSEC_DMA_BAR GENMASK(10, 8) 24 24 + #define DW_PCIE_SYNOPSYS_VSEC_DMA_MAP GENMASK(2, 0) 25 25 + #define DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH GENMASK(9, 0) 26 26 + #define DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH GENMASK(25, 16) 27 27 + 28 28 + /* AMD MDB (Xilinx) specific defines */ 29 29 + #define PCI_DEVICE_ID_XILINX_B054 0xb054 30 30 + 31 31 + #define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 32 32 + #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 33 33 + #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) 34 34 + #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) 35 35 + #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) 36 36 + #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) 37 37 + 38 38 + #define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc 39 39 + #define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8 40 40 + #define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL) 41 41 + 42 42 + #define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000 43 43 + #define DW_PCIE_XILINX_MDB_LL_SIZE 0x800 44 44 + #define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000 45 45 + #define DW_PCIE_XILINX_MDB_DT_SIZE 0x800 25 46 26 47 #define DW_BLOCK(a, b, c) \ 27 48 { \ ··· 71 50 u8 irqs; 72 51 u16 wr_ch_cnt; 73 52 u16 rd_ch_cnt; 53 53 + u64 devmem_phys_off; 74 54 }; 75 55 76 56 static const struct dw_edma_pcie_data snps_edda_data = { ··· 112 90 .rd_ch_cnt = 2, 113 91 }; 114 92 93 93 + static const struct dw_edma_pcie_data xilinx_mdb_data = { 94 94 + /* MDB registers location */ 95 95 + .rg.bar = BAR_0, 96 96 + .rg.off = SZ_4K, /* 4 Kbytes */ 97 97 + .rg.sz = SZ_8K, /* 8 Kbytes */ 98 98 + 99 99 + /* Other */ 100 100 + .mf = EDMA_MF_HDMA_NATIVE, 101 101 + .irqs = 1, 102 102 + .wr_ch_cnt = 8, 103 103 + .rd_ch_cnt = 8, 104 104 + }; 105 105 + 106 106 + static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, 107 107 + enum pci_barno bar, off_t start_off, 108 108 + off_t ll_off_gap, size_t ll_size, 109 109 + off_t dt_off_gap, size_t dt_size) 110 110 + { 111 111 + u16 wr_ch = pdata->wr_ch_cnt; 112 112 + u16 rd_ch = pdata->rd_ch_cnt; 113 113 + off_t off; 114 114 + u16 i; 115 115 + 116 116 + off = start_off; 117 117 + 118 118 + /* Write channel LL region */ 119 119 + for (i = 0; i < wr_ch; i++) { 120 120 + pdata->ll_wr[i].bar = bar; 121 121 + pdata->ll_wr[i].off = off; 122 122 + pdata->ll_wr[i].sz = ll_size; 123 123 + off += ll_off_gap; 124 124 + } 125 125 + 126 126 + /* Read channel LL region */ 127 127 + for (i = 0; i < rd_ch; i++) { 128 128 + pdata->ll_rd[i].bar = bar; 129 129 + pdata->ll_rd[i].off = off; 130 130 + pdata->ll_rd[i].sz = ll_size; 131 131 + off += ll_off_gap; 132 132 + } 133 133 + 134 134 + /* Write channel data region */ 135 135 + for (i = 0; i < wr_ch; i++) { 136 136 + pdata->dt_wr[i].bar = bar; 137 137 + pdata->dt_wr[i].off = off; 138 138 + pdata->dt_wr[i].sz = dt_size; 139 139 + off += dt_off_gap; 140 140 + } 141 141 + 142 142 + /* Read channel data region */ 143 143 + for (i = 0; i < rd_ch; i++) { 144 144 + pdata->dt_rd[i].bar = bar; 145 145 + pdata->dt_rd[i].off = off; 146 146 + pdata->dt_rd[i].sz = dt_size; 147 147 + off += dt_off_gap; 148 148 + } 149 149 + } 150 150 + 115 151 static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) 116 152 { 117 153 return pci_irq_vector(to_pci_dev(dev), nr); ··· 194 114 .pci_address = dw_edma_pcie_address, 195 115 }; 196 116 197 197 - static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev, 198 198 - struct dw_edma_pcie_data *pdata) 117 117 + static void dw_edma_pcie_get_synopsys_dma_data(struct pci_dev *pdev, 118 118 + struct dw_edma_pcie_data *pdata) 199 119 { 200 120 u32 val, map; 201 121 u16 vsec; 202 122 u64 off; 203 123 204 124 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, 205 205 - DW_PCIE_VSEC_DMA_ID); 125 125 + DW_PCIE_SYNOPSYS_VSEC_DMA_ID); 206 126 if (!vsec) 207 127 return; 208 128 ··· 211 131 PCI_VNDR_HEADER_LEN(val) != 0x18) 212 132 return; 213 133 214 214 - pci_dbg(pdev, "Detected PCIe Vendor-Specific Extended Capability DMA\n"); 134 134 + pci_dbg(pdev, "Detected Synopsys PCIe Vendor-Specific Extended Capability DMA\n"); 215 135 pci_read_config_dword(pdev, vsec + 0x8, &val); 216 216 - map = FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val); 136 136 + map = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_MAP, val); 217 137 if (map != EDMA_MF_EDMA_LEGACY && 218 138 map != EDMA_MF_EDMA_UNROLL && 219 139 map != EDMA_MF_HDMA_COMPAT && ··· 221 141 return; 222 142 223 143 pdata->mf = map; 224 224 - pdata->rg.bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val); 144 144 + pdata->rg.bar = FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_BAR, val); 225 145 226 146 pci_read_config_dword(pdev, vsec + 0xc, &val); 227 147 pdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt, 228 228 - FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val)); 148 148 + FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_WR_CH, val)); 229 149 pdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt, 230 230 - FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val)); 150 150 + FIELD_GET(DW_PCIE_SYNOPSYS_VSEC_DMA_RD_CH, val)); 231 151 232 152 pci_read_config_dword(pdev, vsec + 0x14, &val); 233 153 off = val; ··· 235 155 off <<= 32; 236 156 off |= val; 237 157 pdata->rg.off = off; 158 158 + } 159 159 + 160 160 + static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, 161 161 + struct dw_edma_pcie_data *pdata) 162 162 + { 163 163 + u32 val, map; 164 164 + u16 vsec; 165 165 + u64 off; 166 166 + 167 167 + pdata->devmem_phys_off = DW_PCIE_XILINX_MDB_INVALID_ADDR; 168 168 + 169 169 + vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, 170 170 + DW_PCIE_XILINX_MDB_VSEC_DMA_ID); 171 171 + if (!vsec) 172 172 + return; 173 173 + 174 174 + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); 175 175 + if (PCI_VNDR_HEADER_REV(val) != 0x00 || 176 176 + PCI_VNDR_HEADER_LEN(val) != 0x18) 177 177 + return; 178 178 + 179 179 + pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability DMA\n"); 180 180 + pci_read_config_dword(pdev, vsec + 0x8, &val); 181 181 + map = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val); 182 182 + if (map != EDMA_MF_HDMA_NATIVE) 183 183 + return; 184 184 + 185 185 + pdata->mf = map; 186 186 + pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); 187 187 + 188 188 + pci_read_config_dword(pdev, vsec + 0xc, &val); 189 189 + pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, 190 190 + FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); 191 191 + pdata->rd_ch_cnt = min(pdata->rd_ch_cnt, 192 192 + FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val)); 193 193 + 194 194 + pci_read_config_dword(pdev, vsec + 0x14, &val); 195 195 + off = val; 196 196 + pci_read_config_dword(pdev, vsec + 0x10, &val); 197 197 + off <<= 32; 198 198 + off |= val; 199 199 + pdata->rg.off = off; 200 200 + 201 201 + vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, 202 202 + DW_PCIE_XILINX_MDB_VSEC_ID); 203 203 + if (!vsec) 204 204 + return; 205 205 + 206 206 + pci_read_config_dword(pdev, 207 207 + vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH, 208 208 + &val); 209 209 + off = val; 210 210 + pci_read_config_dword(pdev, 211 211 + vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW, 212 212 + &val); 213 213 + off <<= 32; 214 214 + off |= val; 215 215 + pdata->devmem_phys_off = off; 216 216 + } 217 217 + 218 218 + static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, 219 219 + struct dw_edma_pcie_data *pdata, 220 220 + enum pci_barno bar) 221 221 + { 222 222 + if (pdev->vendor == PCI_VENDOR_ID_XILINX) 223 223 + return pdata->devmem_phys_off; 224 224 + return pci_bus_address(pdev, bar); 238 225 } 239 226 240 227 static int dw_edma_pcie_probe(struct pci_dev *pdev, ··· 312 165 struct dw_edma_chip *chip; 313 166 int err, nr_irqs; 314 167 int i, mask; 168 168 + bool non_ll = false; 315 169 316 170 struct dw_edma_pcie_data *vsec_data __free(kfree) = 317 171 kmalloc_obj(*vsec_data); ··· 332 184 * Tries to find if exists a PCIe Vendor-Specific Extended Capability 333 185 * for the DMA, if one exists, then reconfigures it. 334 186 */ 335 335 - dw_edma_pcie_get_vsec_dma_data(pdev, vsec_data); 187 187 + dw_edma_pcie_get_synopsys_dma_data(pdev, vsec_data); 188 188 + 189 189 + if (pdev->vendor == PCI_VENDOR_ID_XILINX) { 190 190 + dw_edma_pcie_get_xilinx_dma_data(pdev, vsec_data); 191 191 + 192 192 + /* 193 193 + * There is no valid address found for the LL memory 194 194 + * space on the device side. In the absence of LL base 195 195 + * address use the non-LL mode or simple mode supported by 196 196 + * the HDMA IP. 197 197 + */ 198 198 + if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR) 199 199 + non_ll = true; 200 200 + 201 201 + /* 202 202 + * Configure the channel LL and data blocks if number of 203 203 + * channels enabled in VSEC capability are more than the 204 204 + * channels configured in xilinx_mdb_data. 205 205 + */ 206 206 + if (!non_ll) 207 207 + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, 208 208 + DW_PCIE_XILINX_MDB_LL_OFF_GAP, 209 209 + DW_PCIE_XILINX_MDB_LL_SIZE, 210 210 + DW_PCIE_XILINX_MDB_DT_OFF_GAP, 211 211 + DW_PCIE_XILINX_MDB_DT_SIZE); 212 212 + } 336 213 337 214 /* Mapping PCI BAR regions */ 338 215 mask = BIT(vsec_data->rg.bar); ··· 404 231 chip->mf = vsec_data->mf; 405 232 chip->nr_irqs = nr_irqs; 406 233 chip->ops = &dw_edma_pcie_plat_ops; 234 234 + chip->cfg_non_ll = non_ll; 407 235 408 236 chip->ll_wr_cnt = vsec_data->wr_ch_cnt; 409 237 chip->ll_rd_cnt = vsec_data->rd_ch_cnt; ··· 413 239 if (!chip->reg_base) 414 240 return -ENOMEM; 415 241 416 416 - for (i = 0; i < chip->ll_wr_cnt; i++) { 242 242 + for (i = 0; i < chip->ll_wr_cnt && !non_ll; i++) { 417 243 struct dw_edma_region *ll_region = &chip->ll_region_wr[i]; 418 244 struct dw_edma_region *dt_region = &chip->dt_region_wr[i]; 419 245 struct dw_edma_block *ll_block = &vsec_data->ll_wr[i]; ··· 424 250 return -ENOMEM; 425 251 426 252 ll_region->vaddr.io += ll_block->off; 427 427 - ll_region->paddr = pci_bus_address(pdev, ll_block->bar); 253 253 + ll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 254 254 + ll_block->bar); 428 255 ll_region->paddr += ll_block->off; 429 256 ll_region->sz = ll_block->sz; 430 257 ··· 434 259 return -ENOMEM; 435 260 436 261 dt_region->vaddr.io += dt_block->off; 437 437 - dt_region->paddr = pci_bus_address(pdev, dt_block->bar); 262 262 + dt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 263 263 + dt_block->bar); 438 264 dt_region->paddr += dt_block->off; 439 265 dt_region->sz = dt_block->sz; 440 266 } 441 267 442 442 - for (i = 0; i < chip->ll_rd_cnt; i++) { 268 268 + for (i = 0; i < chip->ll_rd_cnt && !non_ll; i++) { 443 269 struct dw_edma_region *ll_region = &chip->ll_region_rd[i]; 444 270 struct dw_edma_region *dt_region = &chip->dt_region_rd[i]; 445 271 struct dw_edma_block *ll_block = &vsec_data->ll_rd[i]; ··· 451 275 return -ENOMEM; 452 276 453 277 ll_region->vaddr.io += ll_block->off; 454 454 - ll_region->paddr = pci_bus_address(pdev, ll_block->bar); 278 278 + ll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 279 279 + ll_block->bar); 455 280 ll_region->paddr += ll_block->off; 456 281 ll_region->sz = ll_block->sz; 457 282 ··· 461 284 return -ENOMEM; 462 285 463 286 dt_region->vaddr.io += dt_block->off; 464 464 - dt_region->paddr = pci_bus_address(pdev, dt_block->bar); 287 287 + dt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data, 288 288 + dt_block->bar); 465 289 dt_region->paddr += dt_block->off; 466 290 dt_region->sz = dt_block->sz; 467 291 } ··· 545 367 546 368 static const struct pci_device_id dw_edma_pcie_id_table[] = { 547 369 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, 370 370 + { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054), 371 371 + (kernel_ulong_t)&xilinx_mdb_data }, 548 372 { } 549 373 }; 550 374 MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);

+21

drivers/dma/dw-edma/dw-edma-v0-core.c

reviewed

··· 509 509 dw_edma_v0_debugfs_on(dw); 510 510 } 511 511 512 512 + static void dw_edma_v0_core_ack_emulated_irq(struct dw_edma *dw) 513 513 + { 514 514 + /* 515 515 + * Interrupt emulation may assert the IRQ without setting 516 516 + * DONE/ABORT status bits. A zero write to INT_CLEAR deasserts the 517 517 + * emulated IRQ, while being a no-op for real interrupts. 518 518 + */ 519 519 + SET_BOTH_32(dw, int_clear, 0); 520 520 + } 521 521 + 522 522 + static resource_size_t dw_edma_v0_core_db_offset(struct dw_edma *dw) 523 523 + { 524 524 + /* 525 525 + * rd_int_status is chosen arbitrarily, but wr_int_status would be 526 526 + * equally suitable. 527 527 + */ 528 528 + return offsetof(struct dw_edma_v0_regs, rd_int_status); 529 529 + } 530 530 + 512 531 static const struct dw_edma_core_ops dw_edma_v0_core = { 513 532 .off = dw_edma_v0_core_off, 514 533 .ch_count = dw_edma_v0_core_ch_count, ··· 536 517 .start = dw_edma_v0_core_start, 537 518 .ch_config = dw_edma_v0_core_ch_config, 538 519 .debugfs_on = dw_edma_v0_core_debugfs_on, 520 520 + .ack_emulated_irq = dw_edma_v0_core_ack_emulated_irq, 521 521 + .db_offset = dw_edma_v0_core_db_offset, 539 522 }; 540 523 541 524 void dw_edma_v0_core_register(struct dw_edma *dw)

+70 -1

drivers/dma/dw-edma/dw-hdma-v0-core.c

reviewed

··· 225 225 readl(chunk->ll_region.vaddr.io); 226 226 } 227 227 228 228 - static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) 228 228 + static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool first) 229 229 { 230 230 struct dw_edma_chan *chan = chunk->chan; 231 231 struct dw_edma *dw = chan->dw; ··· 263 263 SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); 264 264 } 265 265 266 266 + static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk) 267 267 + { 268 268 + struct dw_edma_chan *chan = chunk->chan; 269 269 + struct dw_edma *dw = chan->dw; 270 270 + struct dw_edma_burst *child; 271 271 + u32 val; 272 272 + 273 273 + child = list_first_entry_or_null(&chunk->burst->list, 274 274 + struct dw_edma_burst, list); 275 275 + if (!child) 276 276 + return; 277 277 + 278 278 + SET_CH_32(dw, chan->dir, chan->id, ch_en, HDMA_V0_CH_EN); 279 279 + 280 280 + /* Source address */ 281 281 + SET_CH_32(dw, chan->dir, chan->id, sar.lsb, 282 282 + lower_32_bits(child->sar)); 283 283 + SET_CH_32(dw, chan->dir, chan->id, sar.msb, 284 284 + upper_32_bits(child->sar)); 285 285 + 286 286 + /* Destination address */ 287 287 + SET_CH_32(dw, chan->dir, chan->id, dar.lsb, 288 288 + lower_32_bits(child->dar)); 289 289 + SET_CH_32(dw, chan->dir, chan->id, dar.msb, 290 290 + upper_32_bits(child->dar)); 291 291 + 292 292 + /* Transfer size */ 293 293 + SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); 294 294 + 295 295 + /* Interrupt setup */ 296 296 + val = GET_CH_32(dw, chan->dir, chan->id, int_setup) | 297 297 + HDMA_V0_STOP_INT_MASK | 298 298 + HDMA_V0_ABORT_INT_MASK | 299 299 + HDMA_V0_LOCAL_STOP_INT_EN | 300 300 + HDMA_V0_LOCAL_ABORT_INT_EN; 301 301 + 302 302 + if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) { 303 303 + val |= HDMA_V0_REMOTE_STOP_INT_EN | 304 304 + HDMA_V0_REMOTE_ABORT_INT_EN; 305 305 + } 306 306 + 307 307 + SET_CH_32(dw, chan->dir, chan->id, int_setup, val); 308 308 + 309 309 + /* Channel control setup */ 310 310 + val = GET_CH_32(dw, chan->dir, chan->id, control1); 311 311 + val &= ~HDMA_V0_LINKLIST_EN; 312 312 + SET_CH_32(dw, chan->dir, chan->id, control1, val); 313 313 + 314 314 + SET_CH_32(dw, chan->dir, chan->id, doorbell, 315 315 + HDMA_V0_DOORBELL_START); 316 316 + } 317 317 + 318 318 + static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) 319 319 + { 320 320 + struct dw_edma_chan *chan = chunk->chan; 321 321 + 322 322 + if (chan->non_ll) 323 323 + dw_hdma_v0_core_non_ll_start(chunk); 324 324 + else 325 325 + dw_hdma_v0_core_ll_start(chunk, first); 326 326 + } 327 327 + 266 328 static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) 267 329 { 268 330 struct dw_edma *dw = chan->dw; ··· 345 283 dw_hdma_v0_debugfs_on(dw); 346 284 } 347 285 286 286 + static resource_size_t dw_hdma_v0_core_db_offset(struct dw_edma *dw) 287 287 + { 288 288 + /* Implement once the correct offset is known. */ 289 289 + return ~0; 290 290 + } 291 291 + 348 292 static const struct dw_edma_core_ops dw_hdma_v0_core = { 349 293 .off = dw_hdma_v0_core_off, 350 294 .ch_count = dw_hdma_v0_core_ch_count, ··· 359 291 .start = dw_hdma_v0_core_start, 360 292 .ch_config = dw_hdma_v0_core_ch_config, 361 293 .debugfs_on = dw_hdma_v0_core_debugfs_on, 294 294 + .db_offset = dw_hdma_v0_core_db_offset, 362 295 }; 363 296 364 297 void dw_hdma_v0_core_register(struct dw_edma *dw)

+1

drivers/dma/dw-edma/dw-hdma-v0-regs.h

reviewed

··· 12 12 #include <linux/dmaengine.h> 13 13 14 14 #define HDMA_V0_MAX_NR_CH 8 15 15 + #define HDMA_V0_CH_EN BIT(0) 15 16 #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) 16 17 #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) 17 18 #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4)

+1 -2

drivers/dma/fsl-edma-common.c

reviewed

··· 905 905 fsl_chan->is_sw = false; 906 906 fsl_chan->srcid = 0; 907 907 fsl_chan->is_remote = false; 908 908 - if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK) 909 909 - clk_disable_unprepare(fsl_chan->clk); 908 908 + clk_disable_unprepare(fsl_chan->clk); 910 909 } 911 910 912 911 void fsl_edma_cleanup_vchan(struct dma_device *dmadev)

+22 -33

drivers/dma/fsl-edma-main.c

reviewed

··· 705 705 int ret, i; 706 706 707 707 drvdata = device_get_match_data(&pdev->dev); 708 708 - if (!drvdata) { 709 709 - dev_err(&pdev->dev, "unable to find driver data\n"); 710 710 - return -EINVAL; 711 711 - } 708 708 + if (!drvdata) 709 709 + return dev_err_probe(&pdev->dev, -EINVAL, 710 710 + "unable to find driver data\n"); 712 711 713 712 ret = of_property_read_u32(np, "dma-channels", &chans); 714 714 - if (ret) { 715 715 - dev_err(&pdev->dev, "Can't get dma-channels.\n"); 716 716 - return ret; 717 717 - } 713 713 + if (ret) 714 714 + return dev_err_probe(&pdev->dev, ret, 715 715 + "Can't get dma-channels.\n"); 718 716 719 717 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 720 718 GFP_KERNEL); ··· 736 738 737 739 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 738 740 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 739 739 - if (IS_ERR(fsl_edma->dmaclk)) { 740 740 - dev_err(&pdev->dev, "Missing DMA block clock.\n"); 741 741 - return PTR_ERR(fsl_edma->dmaclk); 742 742 - } 741 741 + if (IS_ERR(fsl_edma->dmaclk)) 742 742 + return dev_err_probe(&pdev->dev, 743 743 + PTR_ERR(fsl_edma->dmaclk), 744 744 + "Missing DMA block clock.\n"); 743 745 } 744 746 745 747 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); ··· 763 765 764 766 sprintf(clkname, "dmamux%d", i); 765 767 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 766 766 - if (IS_ERR(fsl_edma->muxclk[i])) { 767 767 - dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 768 768 - /* on error: disable all previously enabled clks */ 769 769 - return PTR_ERR(fsl_edma->muxclk[i]); 770 770 - } 768 768 + if (IS_ERR(fsl_edma->muxclk[i])) 769 769 + return dev_err_probe(&pdev->dev, 770 770 + PTR_ERR(fsl_edma->muxclk[i]), 771 771 + "Missing DMAMUX block clock.\n"); 771 772 } 772 773 773 774 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); ··· 875 878 876 879 platform_set_drvdata(pdev, fsl_edma); 877 880 878 878 - ret = dma_async_device_register(&fsl_edma->dma_dev); 879 879 - if (ret) { 880 880 - dev_err(&pdev->dev, 881 881 - "Can't register Freescale eDMA engine. (%d)\n", ret); 882 882 - return ret; 883 883 - } 881 881 + ret = dmaenginem_async_device_register(&fsl_edma->dma_dev); 882 882 + if (ret) 883 883 + return dev_err_probe(&pdev->dev, ret, 884 884 + "Can't register Freescale eDMA engine.\n"); 884 885 885 885 - ret = of_dma_controller_register(np, 886 886 + ret = devm_of_dma_controller_register(&pdev->dev, np, 886 887 drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate, 887 888 fsl_edma); 888 888 - if (ret) { 889 889 - dev_err(&pdev->dev, 890 890 - "Can't register Freescale eDMA of_dma. (%d)\n", ret); 891 891 - dma_async_device_unregister(&fsl_edma->dma_dev); 892 892 - return ret; 893 893 - } 889 889 + if (ret) 890 890 + return dev_err_probe(&pdev->dev, ret, 891 891 + "Can't register Freescale eDMA of_dma.\n"); 894 892 895 893 /* enable round robin arbitration */ 896 894 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) ··· 896 904 897 905 static void fsl_edma_remove(struct platform_device *pdev) 898 906 { 899 899 - struct device_node *np = pdev->dev.of_node; 900 907 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 901 908 902 909 fsl_edma_irq_exit(pdev, fsl_edma); 903 903 - of_dma_controller_free(np); 904 904 - dma_async_device_unregister(&fsl_edma->dma_dev); 905 910 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 906 911 } 907 912

+19 -28

drivers/dma/fsl-qdma.c

reviewed

··· 1127 1127 struct device_node *np = pdev->dev.of_node; 1128 1128 1129 1129 ret = of_property_read_u32(np, "dma-channels", &chans); 1130 1130 - if (ret) { 1131 1131 - dev_err(&pdev->dev, "Can't get dma-channels.\n"); 1132 1132 - return ret; 1133 1133 - } 1130 1130 + if (ret) 1131 1131 + return dev_err_probe(&pdev->dev, ret, 1132 1132 + "Can't get dma-channels.\n"); 1134 1133 1135 1134 ret = of_property_read_u32(np, "block-offset", &blk_off); 1136 1136 - if (ret) { 1137 1137 - dev_err(&pdev->dev, "Can't get block-offset.\n"); 1138 1138 - return ret; 1139 1139 - } 1135 1135 + if (ret) 1136 1136 + return dev_err_probe(&pdev->dev, ret, 1137 1137 + "Can't get block-offset.\n"); 1140 1138 1141 1139 ret = of_property_read_u32(np, "block-number", &blk_num); 1142 1142 - if (ret) { 1143 1143 - dev_err(&pdev->dev, "Can't get block-number.\n"); 1144 1144 - return ret; 1145 1145 - } 1140 1140 + if (ret) 1141 1141 + return dev_err_probe(&pdev->dev, ret, 1142 1142 + "Can't get block-number.\n"); 1146 1143 1147 1144 blk_num = min_t(int, blk_num, num_online_cpus()); 1148 1145 ··· 1164 1167 return -ENOMEM; 1165 1168 1166 1169 ret = of_property_read_u32(np, "fsl,dma-queues", &queues); 1167 1167 - if (ret) { 1168 1168 - dev_err(&pdev->dev, "Can't get queues.\n"); 1169 1169 - return ret; 1170 1170 - } 1170 1170 + if (ret) 1171 1171 + return dev_err_probe(&pdev->dev, ret, "Can't get queues.\n"); 1171 1172 1172 1173 fsl_qdma->desc_allocated = 0; 1173 1174 fsl_qdma->n_chans = chans; ··· 1226 1231 fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all; 1227 1232 1228 1233 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); 1229 1229 - if (ret) { 1230 1230 - dev_err(&pdev->dev, "dma_set_mask failure.\n"); 1231 1231 - return ret; 1232 1232 - } 1234 1234 + if (ret) 1235 1235 + return dev_err_probe(&pdev->dev, ret, "dma_set_mask failure.\n"); 1233 1236 1234 1237 platform_set_drvdata(pdev, fsl_qdma); 1235 1238 1236 1239 ret = fsl_qdma_reg_init(fsl_qdma); 1237 1237 - if (ret) { 1238 1238 - dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n"); 1239 1239 - return ret; 1240 1240 - } 1240 1240 + if (ret) 1241 1241 + return dev_err_probe(&pdev->dev, ret, 1242 1242 + "Can't Initialize the qDMA engine.\n"); 1241 1243 1242 1244 ret = fsl_qdma_irq_init(pdev, fsl_qdma); 1243 1245 if (ret) 1244 1246 return ret; 1245 1247 1246 1248 ret = dma_async_device_register(&fsl_qdma->dma_dev); 1247 1247 - if (ret) { 1248 1248 - dev_err(&pdev->dev, "Can't register NXP Layerscape qDMA engine.\n"); 1249 1249 - return ret; 1250 1250 - } 1249 1249 + if (ret) 1250 1250 + return dev_err_probe(&pdev->dev, ret, 1251 1251 + "Can't register NXP Layerscape qDMA engine.\n"); 1251 1252 1252 1253 return 0; 1253 1254 }

+15 -41

drivers/dma/imx-sdma.c

reviewed

··· 2265 2265 if (IS_ERR(sdma->regs)) 2266 2266 return PTR_ERR(sdma->regs); 2267 2267 2268 2268 - sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2268 2268 + sdma->clk_ipg = devm_clk_get_prepared(&pdev->dev, "ipg"); 2269 2269 if (IS_ERR(sdma->clk_ipg)) 2270 2270 return PTR_ERR(sdma->clk_ipg); 2271 2271 2272 2272 - sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 2272 2272 + sdma->clk_ahb = devm_clk_get_prepared(&pdev->dev, "ahb"); 2273 2273 if (IS_ERR(sdma->clk_ahb)) 2274 2274 return PTR_ERR(sdma->clk_ahb); 2275 2275 - 2276 2276 - ret = clk_prepare(sdma->clk_ipg); 2277 2277 - if (ret) 2278 2278 - return ret; 2279 2279 - 2280 2280 - ret = clk_prepare(sdma->clk_ahb); 2281 2281 - if (ret) 2282 2282 - goto err_clk; 2283 2275 2284 2276 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, 2285 2277 dev_name(&pdev->dev), sdma); 2286 2278 if (ret) 2287 2287 - goto err_irq; 2279 2279 + return ret; 2288 2280 2289 2281 sdma->irq = irq; 2290 2282 2291 2283 sdma->script_addrs = kzalloc_obj(*sdma->script_addrs); 2292 2292 - if (!sdma->script_addrs) { 2293 2293 - ret = -ENOMEM; 2294 2294 - goto err_irq; 2295 2295 - } 2284 2284 + if (!sdma->script_addrs) 2285 2285 + return -ENOMEM; 2296 2286 2297 2287 /* initially no scripts available */ 2298 2288 saddr_arr = (s32 *)sdma->script_addrs; ··· 2323 2333 2324 2334 ret = sdma_init(sdma); 2325 2335 if (ret) 2326 2326 - goto err_init; 2336 2336 + return ret; 2327 2337 2328 2338 ret = sdma_event_remap(sdma); 2329 2339 if (ret) 2330 2330 - goto err_init; 2340 2340 + return ret; 2331 2341 2332 2342 if (sdma->drvdata->script_addrs) 2333 2343 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); ··· 2353 2363 2354 2364 platform_set_drvdata(pdev, sdma); 2355 2365 2356 2356 - ret = dma_async_device_register(&sdma->dma_device); 2357 2357 - if (ret) { 2358 2358 - dev_err(&pdev->dev, "unable to register\n"); 2359 2359 - goto err_init; 2360 2360 - } 2366 2366 + ret = dmaenginem_async_device_register(&sdma->dma_device); 2367 2367 + if (ret) 2368 2368 + return dev_err_probe(&pdev->dev, ret, "unable to register\n"); 2361 2369 2362 2370 if (np) { 2363 2363 - ret = of_dma_controller_register(np, sdma_xlate, sdma); 2364 2364 - if (ret) { 2365 2365 - dev_err(&pdev->dev, "failed to register controller\n"); 2366 2366 - goto err_register; 2367 2367 - } 2371 2371 + ret = devm_of_dma_controller_register(&pdev->dev, np, 2372 2372 + sdma_xlate, sdma); 2373 2373 + if (ret) 2374 2374 + return dev_err_probe(&pdev->dev, ret, 2375 2375 + "failed to register controller\n"); 2368 2376 2369 2377 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); 2370 2378 ret = of_address_to_resource(spba_bus, 0, &spba_res); ··· 2389 2401 } 2390 2402 2391 2403 return 0; 2392 2392 - 2393 2393 - err_register: 2394 2394 - dma_async_device_unregister(&sdma->dma_device); 2395 2395 - err_init: 2396 2396 - kfree(sdma->script_addrs); 2397 2397 - err_irq: 2398 2398 - clk_unprepare(sdma->clk_ahb); 2399 2399 - err_clk: 2400 2400 - clk_unprepare(sdma->clk_ipg); 2401 2401 - return ret; 2402 2404 } 2403 2405 2404 2406 static void sdma_remove(struct platform_device *pdev) ··· 2397 2419 int i; 2398 2420 2399 2421 devm_free_irq(&pdev->dev, sdma->irq, sdma); 2400 2400 - dma_async_device_unregister(&sdma->dma_device); 2401 2401 - kfree(sdma->script_addrs); 2402 2402 - clk_unprepare(sdma->clk_ahb); 2403 2403 - clk_unprepare(sdma->clk_ipg); 2404 2422 /* Kill the tasklet */ 2405 2423 for (i = 0; i < MAX_DMA_CHANNELS; i++) { 2406 2424 struct sdma_channel *sdmac = &sdma->channel[i];

+2 -11

drivers/dma/ioat/dma.h

reviewed

··· 140 140 int prev_intr_coalesce; 141 141 }; 142 142 143 143 - struct ioat_sysfs_entry { 144 144 - struct attribute attr; 145 145 - ssize_t (*show)(struct dma_chan *, char *); 146 146 - ssize_t (*store)(struct dma_chan *, const char *, size_t); 147 147 - }; 148 148 - 149 143 /** 150 144 * struct ioat_sed_ent - wrapper around super extended hardware descriptor 151 145 * @hw: hardware SED ··· 189 195 struct ioat_sed_ent *sed; 190 196 }; 191 197 192 192 - extern const struct sysfs_ops ioat_sysfs_ops; 193 193 - extern struct ioat_sysfs_entry ioat_version_attr; 194 194 - extern struct ioat_sysfs_entry ioat_cap_attr; 195 198 extern int ioat_pending_level; 196 196 - extern struct kobj_type ioat_ktype; 199 199 + extern const struct kobj_type ioat_ktype; 197 200 extern struct kmem_cache *ioat_cache; 198 201 extern struct kmem_cache *ioat_sed_cache; 199 202 ··· 393 402 /* IOAT Init functions */ 394 403 bool is_bwd_ioat(struct pci_dev *pdev); 395 404 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); 396 396 - void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type); 405 405 + void ioat_kobject_add(struct ioatdma_device *ioat_dma, const struct kobj_type *type); 397 406 void ioat_kobject_del(struct ioatdma_device *ioat_dma); 398 407 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma); 399 408 void ioat_stop(struct ioatdma_chan *ioat_chan);

+19 -13

drivers/dma/ioat/sysfs.c

reviewed

··· 14 14 15 15 #include "../dmaengine.h" 16 16 17 17 + struct ioat_sysfs_entry { 18 18 + struct attribute attr; 19 19 + ssize_t (*show)(struct dma_chan *, char *); 20 20 + ssize_t (*store)(struct dma_chan *, const char *, size_t); 21 21 + }; 22 22 + 17 23 static ssize_t cap_show(struct dma_chan *c, char *page) 18 24 { 19 25 struct dma_device *dma = c->device; ··· 32 26 dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : ""); 33 27 34 28 } 35 35 - struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap); 29 29 + static const struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap); 36 30 37 31 static ssize_t version_show(struct dma_chan *c, char *page) 38 32 { ··· 42 36 return sprintf(page, "%d.%d\n", 43 37 ioat_dma->version >> 4, ioat_dma->version & 0xf); 44 38 } 45 45 - struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version); 39 39 + static const struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version); 46 40 47 41 static ssize_t 48 42 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page) 49 43 { 50 50 - struct ioat_sysfs_entry *entry; 44 44 + const struct ioat_sysfs_entry *entry; 51 45 struct ioatdma_chan *ioat_chan; 52 46 53 53 - entry = container_of(attr, struct ioat_sysfs_entry, attr); 47 47 + entry = container_of_const(attr, struct ioat_sysfs_entry, attr); 54 48 ioat_chan = container_of(kobj, struct ioatdma_chan, kobj); 55 49 56 50 if (!entry->show) ··· 62 56 ioat_attr_store(struct kobject *kobj, struct attribute *attr, 63 57 const char *page, size_t count) 64 58 { 65 65 - struct ioat_sysfs_entry *entry; 59 59 + const struct ioat_sysfs_entry *entry; 66 60 struct ioatdma_chan *ioat_chan; 67 61 68 68 - entry = container_of(attr, struct ioat_sysfs_entry, attr); 62 62 + entry = container_of_const(attr, struct ioat_sysfs_entry, attr); 69 63 ioat_chan = container_of(kobj, struct ioatdma_chan, kobj); 70 64 71 65 if (!entry->store) ··· 73 67 return entry->store(&ioat_chan->dma_chan, page, count); 74 68 } 75 69 76 76 - const struct sysfs_ops ioat_sysfs_ops = { 70 70 + static const struct sysfs_ops ioat_sysfs_ops = { 77 71 .show = ioat_attr_show, 78 72 .store = ioat_attr_store, 79 73 }; 80 74 81 81 - void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type) 75 75 + void ioat_kobject_add(struct ioatdma_device *ioat_dma, const struct kobj_type *type) 82 76 { 83 77 struct dma_device *dma = &ioat_dma->dma_dev; 84 78 struct dma_chan *c; ··· 120 114 121 115 return sprintf(page, "%d\n", (1 << ioat_chan->alloc_order) & ~1); 122 116 } 123 123 - static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); 117 117 + static const struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size); 124 118 125 119 static ssize_t ring_active_show(struct dma_chan *c, char *page) 126 120 { ··· 129 123 /* ...taken outside the lock, no need to be precise */ 130 124 return sprintf(page, "%d\n", ioat_ring_active(ioat_chan)); 131 125 } 132 132 - static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); 126 126 + static const struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active); 133 127 134 128 static ssize_t intr_coalesce_show(struct dma_chan *c, char *page) 135 129 { ··· 154 148 return count; 155 149 } 156 150 157 157 - static struct ioat_sysfs_entry intr_coalesce_attr = __ATTR_RW(intr_coalesce); 151 151 + static const struct ioat_sysfs_entry intr_coalesce_attr = __ATTR_RW(intr_coalesce); 158 152 159 159 - static struct attribute *ioat_attrs[] = { 153 153 + static const struct attribute *const ioat_attrs[] = { 160 154 &ring_size_attr.attr, 161 155 &ring_active_attr.attr, 162 156 &ioat_cap_attr.attr, ··· 166 160 }; 167 161 ATTRIBUTE_GROUPS(ioat); 168 162 169 169 - struct kobj_type ioat_ktype = { 163 163 + const struct kobj_type ioat_ktype = { 170 164 .sysfs_ops = &ioat_sysfs_ops, 171 165 .default_groups = ioat_groups, 172 166 };

+41

drivers/dma/loongson/Kconfig

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + # 3 3 + # Loongson DMA controllers drivers 4 4 + # 5 5 + if MACH_LOONGSON32 || MACH_LOONGSON64 || COMPILE_TEST 6 6 + 7 7 + config LOONGSON1_APB_DMA 8 8 + tristate "Loongson1 APB DMA support" 9 9 + depends on MACH_LOONGSON32 || COMPILE_TEST 10 10 + select DMA_ENGINE 11 11 + select DMA_VIRTUAL_CHANNELS 12 12 + help 13 13 + This selects support for the APB DMA controller in Loongson1 SoCs, 14 14 + which is required by Loongson1 NAND and audio support. 15 15 + 16 16 + config LOONGSON2_APB_DMA 17 17 + tristate "Loongson2 APB DMA support" 18 18 + depends on MACH_LOONGSON64 || COMPILE_TEST 19 19 + select DMA_ENGINE 20 20 + select DMA_VIRTUAL_CHANNELS 21 21 + help 22 22 + Support for the Loongson2 APB DMA controller driver. The 23 23 + DMA controller is having single DMA channel which can be 24 24 + configured for different peripherals like audio, nand, sdio 25 25 + etc which is in APB bus. 26 26 + 27 27 + This DMA controller transfers data from memory to peripheral fifo. 28 28 + It does not support memory to memory data transfer. 29 29 + 30 30 + config LOONGSON2_APB_CMC_DMA 31 31 + tristate "Loongson2 Chain Multi-Channel DMA support" 32 32 + depends on MACH_LOONGSON64 || COMPILE_TEST 33 33 + select DMA_ENGINE 34 34 + select DMA_VIRTUAL_CHANNELS 35 35 + help 36 36 + Support for the Loongson Chain Multi-Channel DMA controller driver. 37 37 + It is discovered on the Loongson-2K chip (Loongson-2K0300/Loongson-2K3000), 38 38 + which has 4/8 channels internally, enabling bidirectional data transfer 39 39 + between devices and memory. 40 40 + 41 41 + endif

+4

drivers/dma/loongson/Makefile

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o 3 3 + obj-$(CONFIG_LOONGSON2_APB_DMA) += loongson2-apb-dma.o 4 4 + obj-$(CONFIG_LOONGSON2_APB_CMC_DMA) += loongson2-apb-cmc-dma.o

+730

drivers/dma/loongson/loongson2-apb-cmc-dma.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 2 + /* 3 3 + * Loongson-2 Chain Multi-Channel DMA Controller driver 4 4 + * 5 5 + * Copyright (C) 2024-2026 Loongson Technology Corporation Limited 6 6 + */ 7 7 + 8 8 + #include <linux/acpi.h> 9 9 + #include <linux/acpi_dma.h> 10 10 + #include <linux/bitfield.h> 11 11 + #include <linux/clk.h> 12 12 + #include <linux/dma-mapping.h> 13 13 + #include <linux/dmapool.h> 14 14 + #include <linux/interrupt.h> 15 15 + #include <linux/io.h> 16 16 + #include <linux/module.h> 17 17 + #include <linux/of.h> 18 18 + #include <linux/of_dma.h> 19 19 + #include <linux/platform_device.h> 20 20 + #include <linux/slab.h> 21 21 + 22 22 + #include "../dmaengine.h" 23 23 + #include "../virt-dma.h" 24 24 + 25 25 + #define LOONGSON2_CMCDMA_ISR 0x0 /* DMA Interrupt Status Register */ 26 26 + #define LOONGSON2_CMCDMA_IFCR 0x4 /* DMA Interrupt Flag Clear Register */ 27 27 + #define LOONGSON2_CMCDMA_CCR 0x8 /* DMA Channel Configuration Register */ 28 28 + #define LOONGSON2_CMCDMA_CNDTR 0xc /* DMA Channel Transmit Count Register */ 29 29 + #define LOONGSON2_CMCDMA_CPAR 0x10 /* DMA Channel Peripheral Address Register */ 30 30 + #define LOONGSON2_CMCDMA_CMAR 0x14 /* DMA Channel Memory Address Register */ 31 31 + 32 32 + /* Bitfields of DMA interrupt status register */ 33 33 + #define LOONGSON2_CMCDMA_TCI BIT(1) /* Transfer Complete Interrupt */ 34 34 + #define LOONGSON2_CMCDMA_HTI BIT(2) /* Half Transfer Interrupt */ 35 35 + #define LOONGSON2_CMCDMA_TEI BIT(3) /* Transfer Error Interrupt */ 36 36 + 37 37 + #define LOONGSON2_CMCDMA_MASKI \ 38 38 + (LOONGSON2_CMCDMA_TCI | LOONGSON2_CMCDMA_HTI | LOONGSON2_CMCDMA_TEI) 39 39 + 40 40 + /* Bitfields of DMA channel x Configuration Register */ 41 41 + #define LOONGSON2_CMCDMA_CCR_EN BIT(0) /* Stream Enable */ 42 42 + #define LOONGSON2_CMCDMA_CCR_TCIE BIT(1) /* Transfer Complete Interrupt Enable */ 43 43 + #define LOONGSON2_CMCDMA_CCR_HTIE BIT(2) /* Half Transfer Complete Interrupt Enable */ 44 44 + #define LOONGSON2_CMCDMA_CCR_TEIE BIT(3) /* Transfer Error Interrupt Enable */ 45 45 + #define LOONGSON2_CMCDMA_CCR_DIR BIT(4) /* Data Transfer Direction */ 46 46 + #define LOONGSON2_CMCDMA_CCR_CIRC BIT(5) /* Circular mode */ 47 47 + #define LOONGSON2_CMCDMA_CCR_PINC BIT(6) /* Peripheral increment mode */ 48 48 + #define LOONGSON2_CMCDMA_CCR_MINC BIT(7) /* Memory increment mode */ 49 49 + #define LOONGSON2_CMCDMA_CCR_PSIZE_MASK GENMASK(9, 8) 50 50 + #define LOONGSON2_CMCDMA_CCR_MSIZE_MASK GENMASK(11, 10) 51 51 + #define LOONGSON2_CMCDMA_CCR_PL_MASK GENMASK(13, 12) 52 52 + #define LOONGSON2_CMCDMA_CCR_M2M BIT(14) 53 53 + 54 54 + #define LOONGSON2_CMCDMA_CCR_CFG_MASK \ 55 55 + (LOONGSON2_CMCDMA_CCR_PINC | LOONGSON2_CMCDMA_CCR_MINC | LOONGSON2_CMCDMA_CCR_PL_MASK) 56 56 + 57 57 + #define LOONGSON2_CMCDMA_CCR_IRQ_MASK \ 58 58 + (LOONGSON2_CMCDMA_CCR_TCIE | LOONGSON2_CMCDMA_CCR_HTIE | LOONGSON2_CMCDMA_CCR_TEIE) 59 59 + 60 60 + #define LOONGSON2_CMCDMA_STREAM_MASK \ 61 61 + (LOONGSON2_CMCDMA_CCR_CFG_MASK | LOONGSON2_CMCDMA_CCR_IRQ_MASK) 62 62 + 63 63 + #define LOONGSON2_CMCDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 64 64 + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 65 65 + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 66 66 + 67 67 + #define LOONSON2_CMCDMA_MAX_DATA_ITEMS SZ_64K 68 68 + 69 69 + struct loongson2_cmc_dma_chan_reg { 70 70 + u32 ccr; 71 71 + u32 cndtr; 72 72 + u32 cpar; 73 73 + u32 cmar; 74 74 + }; 75 75 + 76 76 + struct loongson2_cmc_dma_sg_req { 77 77 + u32 len; 78 78 + struct loongson2_cmc_dma_chan_reg chan_reg; 79 79 + }; 80 80 + 81 81 + struct loongson2_cmc_dma_desc { 82 82 + struct virt_dma_desc vdesc; 83 83 + bool cyclic; 84 84 + u32 num_sgs; 85 85 + struct loongson2_cmc_dma_sg_req sg_req[] __counted_by(num_sgs); 86 86 + }; 87 87 + 88 88 + struct loongson2_cmc_dma_chan { 89 89 + struct virt_dma_chan vchan; 90 90 + struct dma_slave_config dma_sconfig; 91 91 + struct loongson2_cmc_dma_desc *desc; 92 92 + u32 id; 93 93 + u32 irq; 94 94 + u32 next_sg; 95 95 + struct loongson2_cmc_dma_chan_reg chan_reg; 96 96 + }; 97 97 + 98 98 + struct loongson2_cmc_dma_dev { 99 99 + struct dma_device ddev; 100 100 + struct clk *dma_clk; 101 101 + void __iomem *base; 102 102 + u32 nr_channels; 103 103 + u32 chan_reg_offset; 104 104 + struct loongson2_cmc_dma_chan chan[] __counted_by(nr_channels); 105 105 + }; 106 106 + 107 107 + struct loongson2_cmc_dma_config { 108 108 + u32 max_channels; 109 109 + u32 chan_reg_offset; 110 110 + }; 111 111 + 112 112 + static const struct loongson2_cmc_dma_config ls2k0300_cmc_dma_config = { 113 113 + .max_channels = 8, 114 114 + .chan_reg_offset = 0x14, 115 115 + }; 116 116 + 117 117 + static const struct loongson2_cmc_dma_config ls2k3000_cmc_dma_config = { 118 118 + .max_channels = 4, 119 119 + .chan_reg_offset = 0x18, 120 120 + }; 121 121 + 122 122 + static struct loongson2_cmc_dma_dev *lmdma_get_dev(struct loongson2_cmc_dma_chan *lchan) 123 123 + { 124 124 + return container_of(lchan->vchan.chan.device, struct loongson2_cmc_dma_dev, ddev); 125 125 + } 126 126 + 127 127 + static struct loongson2_cmc_dma_chan *to_lmdma_chan(struct dma_chan *chan) 128 128 + { 129 129 + return container_of(chan, struct loongson2_cmc_dma_chan, vchan.chan); 130 130 + } 131 131 + 132 132 + static struct loongson2_cmc_dma_desc *to_lmdma_desc(struct virt_dma_desc *vdesc) 133 133 + { 134 134 + return container_of(vdesc, struct loongson2_cmc_dma_desc, vdesc); 135 135 + } 136 136 + 137 137 + static struct device *chan2dev(struct loongson2_cmc_dma_chan *lchan) 138 138 + { 139 139 + return &lchan->vchan.chan.dev->device; 140 140 + } 141 141 + 142 142 + static u32 loongson2_cmc_dma_read(struct loongson2_cmc_dma_dev *lddev, u32 reg, u32 id) 143 143 + { 144 144 + return readl(lddev->base + (reg + lddev->chan_reg_offset * id)); 145 145 + } 146 146 + 147 147 + static void loongson2_cmc_dma_write(struct loongson2_cmc_dma_dev *lddev, u32 reg, u32 id, u32 val) 148 148 + { 149 149 + writel(val, lddev->base + (reg + lddev->chan_reg_offset * id)); 150 150 + } 151 151 + 152 152 + static int loongson2_cmc_dma_get_width(enum dma_slave_buswidth width) 153 153 + { 154 154 + switch (width) { 155 155 + case DMA_SLAVE_BUSWIDTH_1_BYTE: 156 156 + case DMA_SLAVE_BUSWIDTH_2_BYTES: 157 157 + case DMA_SLAVE_BUSWIDTH_4_BYTES: 158 158 + return ffs(width) - 1; 159 159 + default: 160 160 + return -EINVAL; 161 161 + } 162 162 + } 163 163 + 164 164 + static int loongson2_cmc_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *config) 165 165 + { 166 166 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 167 167 + 168 168 + memcpy(&lchan->dma_sconfig, config, sizeof(*config)); 169 169 + 170 170 + return 0; 171 171 + } 172 172 + 173 173 + static void loongson2_cmc_dma_irq_clear(struct loongson2_cmc_dma_chan *lchan, u32 flags) 174 174 + { 175 175 + struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); 176 176 + u32 ifcr; 177 177 + 178 178 + ifcr = flags << (4 * lchan->id); 179 179 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_IFCR, 0, ifcr); 180 180 + } 181 181 + 182 182 + static void loongson2_cmc_dma_stop(struct loongson2_cmc_dma_chan *lchan) 183 183 + { 184 184 + struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); 185 185 + u32 ccr; 186 186 + 187 187 + ccr = loongson2_cmc_dma_read(lddev, LOONGSON2_CMCDMA_CCR, lchan->id); 188 188 + ccr &= ~(LOONGSON2_CMCDMA_CCR_IRQ_MASK | LOONGSON2_CMCDMA_CCR_EN); 189 189 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CCR, lchan->id, ccr); 190 190 + 191 191 + loongson2_cmc_dma_irq_clear(lchan, LOONGSON2_CMCDMA_MASKI); 192 192 + } 193 193 + 194 194 + static int loongson2_cmc_dma_terminate_all(struct dma_chan *chan) 195 195 + { 196 196 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 197 197 + 198 198 + LIST_HEAD(head); 199 199 + 200 200 + scoped_guard(spinlock_irqsave, &lchan->vchan.lock) { 201 201 + if (lchan->desc) { 202 202 + vchan_terminate_vdesc(&lchan->desc->vdesc); 203 203 + loongson2_cmc_dma_stop(lchan); 204 204 + lchan->desc = NULL; 205 205 + } 206 206 + vchan_get_all_descriptors(&lchan->vchan, &head); 207 207 + } 208 208 + 209 209 + vchan_dma_desc_free_list(&lchan->vchan, &head); 210 210 + 211 211 + return 0; 212 212 + } 213 213 + 214 214 + static void loongson2_cmc_dma_synchronize(struct dma_chan *chan) 215 215 + { 216 216 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 217 217 + 218 218 + vchan_synchronize(&lchan->vchan); 219 219 + } 220 220 + 221 221 + static void loongson2_cmc_dma_start_transfer(struct loongson2_cmc_dma_chan *lchan) 222 222 + { 223 223 + struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); 224 224 + struct loongson2_cmc_dma_sg_req *sg_req; 225 225 + struct loongson2_cmc_dma_chan_reg *reg; 226 226 + struct virt_dma_desc *vdesc; 227 227 + 228 228 + loongson2_cmc_dma_stop(lchan); 229 229 + 230 230 + if (!lchan->desc) { 231 231 + vdesc = vchan_next_desc(&lchan->vchan); 232 232 + if (!vdesc) 233 233 + return; 234 234 + 235 235 + list_del(&vdesc->node); 236 236 + lchan->desc = to_lmdma_desc(vdesc); 237 237 + lchan->next_sg = 0; 238 238 + } 239 239 + 240 240 + if (lchan->next_sg == lchan->desc->num_sgs) 241 241 + lchan->next_sg = 0; 242 242 + 243 243 + sg_req = &lchan->desc->sg_req[lchan->next_sg]; 244 244 + reg = &sg_req->chan_reg; 245 245 + 246 246 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CCR, lchan->id, reg->ccr); 247 247 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CNDTR, lchan->id, reg->cndtr); 248 248 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CPAR, lchan->id, reg->cpar); 249 249 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CMAR, lchan->id, reg->cmar); 250 250 + 251 251 + lchan->next_sg++; 252 252 + 253 253 + /* Start DMA */ 254 254 + reg->ccr |= LOONGSON2_CMCDMA_CCR_EN; 255 255 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CCR, lchan->id, reg->ccr); 256 256 + } 257 257 + 258 258 + static void loongson2_cmc_dma_configure_next_sg(struct loongson2_cmc_dma_chan *lchan) 259 259 + { 260 260 + struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); 261 261 + struct loongson2_cmc_dma_sg_req *sg_req; 262 262 + u32 ccr, id = lchan->id; 263 263 + 264 264 + if (lchan->next_sg == lchan->desc->num_sgs) 265 265 + lchan->next_sg = 0; 266 266 + 267 267 + /* Stop to update mem addr */ 268 268 + ccr = loongson2_cmc_dma_read(lddev, LOONGSON2_CMCDMA_CCR, id); 269 269 + ccr &= ~LOONGSON2_CMCDMA_CCR_EN; 270 270 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CCR, id, ccr); 271 271 + 272 272 + sg_req = &lchan->desc->sg_req[lchan->next_sg]; 273 273 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CMAR, id, sg_req->chan_reg.cmar); 274 274 + 275 275 + /* Start transition */ 276 276 + ccr |= LOONGSON2_CMCDMA_CCR_EN; 277 277 + loongson2_cmc_dma_write(lddev, LOONGSON2_CMCDMA_CCR, id, ccr); 278 278 + } 279 279 + 280 280 + static void loongson2_cmc_dma_handle_chan_done(struct loongson2_cmc_dma_chan *lchan) 281 281 + { 282 282 + if (!lchan->desc) 283 283 + return; 284 284 + 285 285 + if (lchan->desc->cyclic) { 286 286 + vchan_cyclic_callback(&lchan->desc->vdesc); 287 287 + /* LOONGSON2_CMCDMA_CCR_CIRC mode don't need update register */ 288 288 + if (lchan->desc->num_sgs == 1) 289 289 + return; 290 290 + loongson2_cmc_dma_configure_next_sg(lchan); 291 291 + lchan->next_sg++; 292 292 + } else { 293 293 + if (lchan->next_sg == lchan->desc->num_sgs) { 294 294 + vchan_cookie_complete(&lchan->desc->vdesc); 295 295 + lchan->desc = NULL; 296 296 + } 297 297 + loongson2_cmc_dma_start_transfer(lchan); 298 298 + } 299 299 + } 300 300 + 301 301 + static irqreturn_t loongson2_cmc_dma_chan_irq(int irq, void *devid) 302 302 + { 303 303 + struct loongson2_cmc_dma_chan *lchan = devid; 304 304 + struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); 305 305 + struct device *dev = chan2dev(lchan); 306 306 + u32 ists, status, ccr; 307 307 + 308 308 + scoped_guard(spinlock, &lchan->vchan.lock) { 309 309 + ccr = loongson2_cmc_dma_read(lddev, LOONGSON2_CMCDMA_CCR, lchan->id); 310 310 + ists = loongson2_cmc_dma_read(lddev, LOONGSON2_CMCDMA_ISR, 0); 311 311 + status = (ists >> (4 * lchan->id)) & LOONGSON2_CMCDMA_MASKI; 312 312 + 313 313 + loongson2_cmc_dma_irq_clear(lchan, status); 314 314 + 315 315 + if (status & LOONGSON2_CMCDMA_TCI) { 316 316 + loongson2_cmc_dma_handle_chan_done(lchan); 317 317 + status &= ~LOONGSON2_CMCDMA_TCI; 318 318 + } 319 319 + 320 320 + if (status & LOONGSON2_CMCDMA_HTI) 321 321 + status &= ~LOONGSON2_CMCDMA_HTI; 322 322 + 323 323 + if (status & LOONGSON2_CMCDMA_TEI) { 324 324 + dev_err(dev, "DMA Transform Error.\n"); 325 325 + if (!(ccr & LOONGSON2_CMCDMA_CCR_EN)) 326 326 + dev_err(dev, "Channel disabled by HW.\n"); 327 327 + } 328 328 + } 329 329 + 330 330 + return IRQ_HANDLED; 331 331 + } 332 332 + 333 333 + static void loongson2_cmc_dma_issue_pending(struct dma_chan *chan) 334 334 + { 335 335 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 336 336 + 337 337 + guard(spinlock_irqsave)(&lchan->vchan.lock); 338 338 + 339 339 + if (vchan_issue_pending(&lchan->vchan) && !lchan->desc) { 340 340 + dev_dbg(chan2dev(lchan), "vchan %pK: issued\n", &lchan->vchan); 341 341 + loongson2_cmc_dma_start_transfer(lchan); 342 342 + } 343 343 + } 344 344 + 345 345 + static int loongson2_cmc_dma_set_xfer_param(struct loongson2_cmc_dma_chan *lchan, 346 346 + enum dma_transfer_direction direction, 347 347 + enum dma_slave_buswidth *buswidth, u32 buf_len) 348 348 + { 349 349 + struct dma_slave_config sconfig = lchan->dma_sconfig; 350 350 + struct device *dev = chan2dev(lchan); 351 351 + int dev_width; 352 352 + u32 ccr; 353 353 + 354 354 + switch (direction) { 355 355 + case DMA_MEM_TO_DEV: 356 356 + dev_width = loongson2_cmc_dma_get_width(sconfig.dst_addr_width); 357 357 + if (dev_width < 0) { 358 358 + dev_err(dev, "DMA_MEM_TO_DEV bus width not supported\n"); 359 359 + return dev_width; 360 360 + } 361 361 + lchan->chan_reg.cpar = sconfig.dst_addr; 362 362 + ccr = LOONGSON2_CMCDMA_CCR_DIR; 363 363 + *buswidth = sconfig.dst_addr_width; 364 364 + break; 365 365 + case DMA_DEV_TO_MEM: 366 366 + dev_width = loongson2_cmc_dma_get_width(sconfig.src_addr_width); 367 367 + if (dev_width < 0) { 368 368 + dev_err(dev, "DMA_DEV_TO_MEM bus width not supported\n"); 369 369 + return dev_width; 370 370 + } 371 371 + lchan->chan_reg.cpar = sconfig.src_addr; 372 372 + ccr = LOONGSON2_CMCDMA_CCR_MINC; 373 373 + *buswidth = sconfig.src_addr_width; 374 374 + break; 375 375 + default: 376 376 + return -EINVAL; 377 377 + } 378 378 + 379 379 + ccr |= FIELD_PREP(LOONGSON2_CMCDMA_CCR_PSIZE_MASK, dev_width) | 380 380 + FIELD_PREP(LOONGSON2_CMCDMA_CCR_MSIZE_MASK, dev_width); 381 381 + 382 382 + /* Set DMA control register */ 383 383 + lchan->chan_reg.ccr &= ~(LOONGSON2_CMCDMA_CCR_PSIZE_MASK | LOONGSON2_CMCDMA_CCR_MSIZE_MASK); 384 384 + lchan->chan_reg.ccr |= ccr; 385 385 + 386 386 + return 0; 387 387 + } 388 388 + 389 389 + static struct dma_async_tx_descriptor * 390 390 + loongson2_cmc_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, u32 sg_len, 391 391 + enum dma_transfer_direction direction, 392 392 + unsigned long flags, void *context) 393 393 + { 394 394 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 395 395 + struct loongson2_cmc_dma_desc *desc; 396 396 + enum dma_slave_buswidth buswidth; 397 397 + struct scatterlist *sg; 398 398 + u32 num_items, i; 399 399 + int ret; 400 400 + 401 401 + desc = kzalloc_flex(*desc, sg_req, sg_len, GFP_NOWAIT); 402 402 + if (!desc) 403 403 + return ERR_PTR(-ENOMEM); 404 404 + 405 405 + for_each_sg(sgl, sg, sg_len, i) { 406 406 + ret = loongson2_cmc_dma_set_xfer_param(lchan, direction, &buswidth, sg_dma_len(sg)); 407 407 + if (ret) 408 408 + return ERR_PTR(ret); 409 409 + 410 410 + num_items = DIV_ROUND_UP(sg_dma_len(sg), buswidth); 411 411 + if (num_items >= LOONSON2_CMCDMA_MAX_DATA_ITEMS) { 412 412 + dev_err(chan2dev(lchan), "Number of items not supported\n"); 413 413 + kfree(desc); 414 414 + return ERR_PTR(-EINVAL); 415 415 + } 416 416 + 417 417 + desc->sg_req[i].len = sg_dma_len(sg); 418 418 + desc->sg_req[i].chan_reg.ccr = lchan->chan_reg.ccr; 419 419 + desc->sg_req[i].chan_reg.cpar = lchan->chan_reg.cpar; 420 420 + desc->sg_req[i].chan_reg.cmar = sg_dma_address(sg); 421 421 + desc->sg_req[i].chan_reg.cndtr = num_items; 422 422 + } 423 423 + 424 424 + desc->num_sgs = sg_len; 425 425 + desc->cyclic = false; 426 426 + 427 427 + return vchan_tx_prep(&lchan->vchan, &desc->vdesc, flags); 428 428 + } 429 429 + 430 430 + static struct dma_async_tx_descriptor * 431 431 + loongson2_cmc_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 432 432 + size_t period_len, enum dma_transfer_direction direction, 433 433 + unsigned long flags) 434 434 + { 435 435 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 436 436 + struct loongson2_cmc_dma_desc *desc; 437 437 + enum dma_slave_buswidth buswidth; 438 438 + u32 num_periods, num_items, i; 439 439 + int ret; 440 440 + 441 441 + if (unlikely(buf_len % period_len)) 442 442 + return ERR_PTR(-EINVAL); 443 443 + 444 444 + ret = loongson2_cmc_dma_set_xfer_param(lchan, direction, &buswidth, period_len); 445 445 + if (ret) 446 446 + return ERR_PTR(ret); 447 447 + 448 448 + num_items = DIV_ROUND_UP(period_len, buswidth); 449 449 + if (num_items >= LOONSON2_CMCDMA_MAX_DATA_ITEMS) { 450 450 + dev_err(chan2dev(lchan), "Number of items not supported\n"); 451 451 + return ERR_PTR(-EINVAL); 452 452 + } 453 453 + 454 454 + /* Enable Circular mode */ 455 455 + if (buf_len == period_len) 456 456 + lchan->chan_reg.ccr |= LOONGSON2_CMCDMA_CCR_CIRC; 457 457 + 458 458 + num_periods = DIV_ROUND_UP(buf_len, period_len); 459 459 + desc = kzalloc_flex(*desc, sg_req, num_periods, GFP_NOWAIT); 460 460 + if (!desc) 461 461 + return ERR_PTR(-ENOMEM); 462 462 + 463 463 + for (i = 0; i < num_periods; i++) { 464 464 + desc->sg_req[i].len = period_len; 465 465 + desc->sg_req[i].chan_reg.ccr = lchan->chan_reg.ccr; 466 466 + desc->sg_req[i].chan_reg.cpar = lchan->chan_reg.cpar; 467 467 + desc->sg_req[i].chan_reg.cmar = buf_addr; 468 468 + desc->sg_req[i].chan_reg.cndtr = num_items; 469 469 + buf_addr += period_len; 470 470 + } 471 471 + 472 472 + desc->num_sgs = num_periods; 473 473 + desc->cyclic = true; 474 474 + 475 475 + return vchan_tx_prep(&lchan->vchan, &desc->vdesc, flags); 476 476 + } 477 477 + 478 478 + static size_t loongson2_cmc_dma_desc_residue(struct loongson2_cmc_dma_chan *lchan, 479 479 + struct loongson2_cmc_dma_desc *desc, u32 next_sg) 480 480 + { 481 481 + struct loongson2_cmc_dma_dev *lddev = lmdma_get_dev(lchan); 482 482 + u32 residue, width, ndtr, ccr, i; 483 483 + 484 484 + ccr = loongson2_cmc_dma_read(lddev, LOONGSON2_CMCDMA_CCR, lchan->id); 485 485 + width = FIELD_GET(LOONGSON2_CMCDMA_CCR_PSIZE_MASK, ccr); 486 486 + 487 487 + ndtr = loongson2_cmc_dma_read(lddev, LOONGSON2_CMCDMA_CNDTR, lchan->id); 488 488 + residue = ndtr << width; 489 489 + 490 490 + if (lchan->desc->cyclic && next_sg == 0) 491 491 + return residue; 492 492 + 493 493 + for (i = next_sg; i < desc->num_sgs; i++) 494 494 + residue += desc->sg_req[i].len; 495 495 + 496 496 + return residue; 497 497 + } 498 498 + 499 499 + static enum dma_status loongson2_cmc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 500 500 + struct dma_tx_state *state) 501 501 + { 502 502 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 503 503 + struct virt_dma_desc *vdesc; 504 504 + enum dma_status status; 505 505 + 506 506 + status = dma_cookie_status(chan, cookie, state); 507 507 + if (status == DMA_COMPLETE || !state) 508 508 + return status; 509 509 + 510 510 + scoped_guard(spinlock_irqsave, &lchan->vchan.lock) { 511 511 + vdesc = vchan_find_desc(&lchan->vchan, cookie); 512 512 + if (lchan->desc && cookie == lchan->desc->vdesc.tx.cookie) 513 513 + state->residue = loongson2_cmc_dma_desc_residue(lchan, lchan->desc, 514 514 + lchan->next_sg); 515 515 + else if (vdesc) 516 516 + state->residue = loongson2_cmc_dma_desc_residue(lchan, 517 517 + to_lmdma_desc(vdesc), 0); 518 518 + } 519 519 + 520 520 + return status; 521 521 + } 522 522 + 523 523 + static void loongson2_cmc_dma_free_chan_resources(struct dma_chan *chan) 524 524 + { 525 525 + vchan_free_chan_resources(to_virt_chan(chan)); 526 526 + } 527 527 + 528 528 + static void loongson2_cmc_dma_desc_free(struct virt_dma_desc *vdesc) 529 529 + { 530 530 + kfree(to_lmdma_desc(vdesc)); 531 531 + } 532 532 + 533 533 + static bool loongson2_cmc_dma_acpi_filter(struct dma_chan *chan, void *param) 534 534 + { 535 535 + struct loongson2_cmc_dma_chan *lchan = to_lmdma_chan(chan); 536 536 + struct acpi_dma_spec *dma_spec = param; 537 537 + 538 538 + memset(&lchan->chan_reg, 0, sizeof(struct loongson2_cmc_dma_chan_reg)); 539 539 + lchan->chan_reg.ccr = dma_spec->chan_id & LOONGSON2_CMCDMA_STREAM_MASK; 540 540 + 541 541 + return true; 542 542 + } 543 543 + 544 544 + static int loongson2_cmc_dma_acpi_controller_register(struct loongson2_cmc_dma_dev *lddev) 545 545 + { 546 546 + struct device *dev = lddev->ddev.dev; 547 547 + struct acpi_dma_filter_info *info; 548 548 + 549 549 + if (!is_acpi_node(dev_fwnode(dev))) 550 550 + return 0; 551 551 + 552 552 + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 553 553 + if (!info) 554 554 + return -ENOMEM; 555 555 + 556 556 + dma_cap_zero(info->dma_cap); 557 557 + info->dma_cap = lddev->ddev.cap_mask; 558 558 + info->filter_fn = loongson2_cmc_dma_acpi_filter; 559 559 + 560 560 + return devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate, info); 561 561 + } 562 562 + 563 563 + static struct dma_chan *loongson2_cmc_dma_of_xlate(struct of_phandle_args *dma_spec, 564 564 + struct of_dma *ofdma) 565 565 + { 566 566 + struct loongson2_cmc_dma_dev *lddev = ofdma->of_dma_data; 567 567 + struct device *dev = lddev->ddev.dev; 568 568 + struct loongson2_cmc_dma_chan *lchan; 569 569 + struct dma_chan *chan; 570 570 + 571 571 + if (dma_spec->args_count < 2) 572 572 + return ERR_PTR(-EINVAL); 573 573 + 574 574 + if (dma_spec->args[0] >= lddev->nr_channels) { 575 575 + dev_err(dev, "Invalid channel id.\n"); 576 576 + return ERR_PTR(-EINVAL); 577 577 + } 578 578 + 579 579 + lchan = &lddev->chan[dma_spec->args[0]]; 580 580 + chan = dma_get_slave_channel(&lchan->vchan.chan); 581 581 + if (!chan) { 582 582 + dev_err(dev, "No more channels available.\n"); 583 583 + return ERR_PTR(-EINVAL); 584 584 + } 585 585 + 586 586 + memset(&lchan->chan_reg, 0, sizeof(struct loongson2_cmc_dma_chan_reg)); 587 587 + lchan->chan_reg.ccr = dma_spec->args[1] & LOONGSON2_CMCDMA_STREAM_MASK; 588 588 + 589 589 + return chan; 590 590 + } 591 591 + 592 592 + static int loongson2_cmc_dma_of_controller_register(struct loongson2_cmc_dma_dev *lddev) 593 593 + { 594 594 + struct device *dev = lddev->ddev.dev; 595 595 + 596 596 + if (!is_of_node(dev_fwnode(dev))) 597 597 + return 0; 598 598 + 599 599 + return of_dma_controller_register(dev->of_node, loongson2_cmc_dma_of_xlate, lddev); 600 600 + } 601 601 + 602 602 + static int loongson2_cmc_dma_probe(struct platform_device *pdev) 603 603 + { 604 604 + const struct loongson2_cmc_dma_config *config; 605 605 + struct loongson2_cmc_dma_chan *lchan; 606 606 + struct loongson2_cmc_dma_dev *lddev; 607 607 + struct device *dev = &pdev->dev; 608 608 + struct dma_device *ddev; 609 609 + u32 nr_chans, i; 610 610 + int ret; 611 611 + 612 612 + config = (const struct loongson2_cmc_dma_config *)device_get_match_data(dev); 613 613 + if (!config) 614 614 + return -EINVAL; 615 615 + 616 616 + ret = device_property_read_u32(dev, "dma-channels", &nr_chans); 617 617 + if (ret || nr_chans > config->max_channels) { 618 618 + dev_err(dev, "missing or invalid dma-channels property\n"); 619 619 + nr_chans = config->max_channels; 620 620 + } 621 621 + 622 622 + lddev = devm_kzalloc(dev, struct_size(lddev, chan, nr_chans), GFP_KERNEL); 623 623 + if (!lddev) 624 624 + return -ENOMEM; 625 625 + 626 626 + lddev->base = devm_platform_ioremap_resource(pdev, 0); 627 627 + if (IS_ERR(lddev->base)) 628 628 + return PTR_ERR(lddev->base); 629 629 + 630 630 + platform_set_drvdata(pdev, lddev); 631 631 + lddev->nr_channels = nr_chans; 632 632 + lddev->chan_reg_offset = config->chan_reg_offset; 633 633 + 634 634 + lddev->dma_clk = devm_clk_get_optional_enabled(dev, NULL); 635 635 + if (IS_ERR(lddev->dma_clk)) 636 636 + return dev_err_probe(dev, PTR_ERR(lddev->dma_clk), "Failed to get dma clock\n"); 637 637 + 638 638 + ddev = &lddev->ddev; 639 639 + ddev->dev = dev; 640 640 + 641 641 + dma_cap_zero(ddev->cap_mask); 642 642 + dma_cap_set(DMA_SLAVE, ddev->cap_mask); 643 643 + dma_cap_set(DMA_PRIVATE, ddev->cap_mask); 644 644 + dma_cap_set(DMA_CYCLIC, ddev->cap_mask); 645 645 + 646 646 + ddev->device_free_chan_resources = loongson2_cmc_dma_free_chan_resources; 647 647 + ddev->device_config = loongson2_cmc_dma_slave_config; 648 648 + ddev->device_prep_slave_sg = loongson2_cmc_dma_prep_slave_sg; 649 649 + ddev->device_prep_dma_cyclic = loongson2_cmc_dma_prep_dma_cyclic; 650 650 + ddev->device_issue_pending = loongson2_cmc_dma_issue_pending; 651 651 + ddev->device_synchronize = loongson2_cmc_dma_synchronize; 652 652 + ddev->device_tx_status = loongson2_cmc_dma_tx_status; 653 653 + ddev->device_terminate_all = loongson2_cmc_dma_terminate_all; 654 654 + 655 655 + ddev->max_sg_burst = LOONSON2_CMCDMA_MAX_DATA_ITEMS; 656 656 + ddev->src_addr_widths = LOONGSON2_CMCDMA_BUSWIDTHS; 657 657 + ddev->dst_addr_widths = LOONGSON2_CMCDMA_BUSWIDTHS; 658 658 + ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 659 659 + INIT_LIST_HEAD(&ddev->channels); 660 660 + 661 661 + for (i = 0; i < nr_chans; i++) { 662 662 + lchan = &lddev->chan[i]; 663 663 + 664 664 + lchan->id = i; 665 665 + lchan->vchan.desc_free = loongson2_cmc_dma_desc_free; 666 666 + vchan_init(&lchan->vchan, ddev); 667 667 + } 668 668 + 669 669 + ret = dmaenginem_async_device_register(ddev); 670 670 + if (ret) 671 671 + return dev_err_probe(dev, ret, "Failed to register DMA engine device.\n"); 672 672 + 673 673 + for (i = 0; i < nr_chans; i++) { 674 674 + lchan = &lddev->chan[i]; 675 675 + 676 676 + lchan->irq = platform_get_irq(pdev, i); 677 677 + if (lchan->irq < 0) 678 678 + return lchan->irq; 679 679 + 680 680 + ret = devm_request_irq(dev, lchan->irq, loongson2_cmc_dma_chan_irq, IRQF_SHARED, 681 681 + dev_name(chan2dev(lchan)), lchan); 682 682 + if (ret) 683 683 + return ret; 684 684 + } 685 685 + 686 686 + ret = loongson2_cmc_dma_acpi_controller_register(lddev); 687 687 + if (ret) 688 688 + return dev_err_probe(dev, ret, "Failed to register dma controller with ACPI.\n"); 689 689 + 690 690 + ret = loongson2_cmc_dma_of_controller_register(lddev); 691 691 + if (ret) 692 692 + return dev_err_probe(dev, ret, "Failed to register dma controller with FDT.\n"); 693 693 + 694 694 + dev_info(dev, "Loongson-2 Multi-Channel DMA Controller registered successfully.\n"); 695 695 + 696 696 + return 0; 697 697 + } 698 698 + 699 699 + static void loongson2_cmc_dma_remove(struct platform_device *pdev) 700 700 + { 701 701 + of_dma_controller_free(pdev->dev.of_node); 702 702 + } 703 703 + 704 704 + static const struct of_device_id loongson2_cmc_dma_of_match[] = { 705 705 + { .compatible = "loongson,ls2k0300-dma", .data = &ls2k0300_cmc_dma_config }, 706 706 + { .compatible = "loongson,ls2k3000-dma", .data = &ls2k3000_cmc_dma_config }, 707 707 + { /* sentinel */ } 708 708 + }; 709 709 + MODULE_DEVICE_TABLE(of, loongson2_cmc_dma_of_match); 710 710 + 711 711 + static const struct acpi_device_id loongson2_cmc_dma_acpi_match[] = { 712 712 + { "LOON0014", .driver_data = (kernel_ulong_t)&ls2k3000_cmc_dma_config }, 713 713 + { /* sentinel */ } 714 714 + }; 715 715 + MODULE_DEVICE_TABLE(acpi, loongson2_cmc_dma_acpi_match); 716 716 + 717 717 + static struct platform_driver loongson2_cmc_dma_driver = { 718 718 + .driver = { 719 719 + .name = "loongson2-apb-cmc-dma", 720 720 + .of_match_table = loongson2_cmc_dma_of_match, 721 721 + .acpi_match_table = loongson2_cmc_dma_acpi_match, 722 722 + }, 723 723 + .probe = loongson2_cmc_dma_probe, 724 724 + .remove = loongson2_cmc_dma_remove, 725 725 + }; 726 726 + module_platform_driver(loongson2_cmc_dma_driver); 727 727 + 728 728 + MODULE_DESCRIPTION("Loongson-2 Chain Multi-Channel DMA Controller driver"); 729 729 + MODULE_AUTHOR("Loongson Technology Corporation Limited"); 730 730 + MODULE_LICENSE("GPL");

+2 -2

drivers/dma/loongson1-apb-dma.c drivers/dma/loongson/loongson1-apb-dma.c

reviewed

··· 16 16 #include <linux/platform_device.h> 17 17 #include <linux/slab.h> 18 18 19 19 - #include "dmaengine.h" 20 20 - #include "virt-dma.h" 19 19 + #include "../dmaengine.h" 20 20 + #include "../virt-dma.h" 21 21 22 22 /* Loongson-1 DMA Control Register */ 23 23 #define LS1X_DMA_CTRL 0x0

+37 -56

drivers/dma/loongson2-apb-dma.c drivers/dma/loongson/loongson2-apb-dma.c

reviewed

··· 17 17 #include <linux/platform_device.h> 18 18 #include <linux/slab.h> 19 19 20 20 - #include "dmaengine.h" 21 21 - #include "virt-dma.h" 20 20 + #include "../dmaengine.h" 21 21 + #include "../virt-dma.h" 22 22 23 23 /* Global Configuration Register */ 24 24 #define LDMA_ORDER_ERG 0x0 ··· 461 461 static void ls2x_dma_issue_pending(struct dma_chan *chan) 462 462 { 463 463 struct ls2x_dma_chan *lchan = to_ldma_chan(chan); 464 464 - unsigned long flags; 465 464 466 466 - spin_lock_irqsave(&lchan->vchan.lock, flags); 465 465 + guard(spinlock_irqsave)(&lchan->vchan.lock); 466 466 + 467 467 if (vchan_issue_pending(&lchan->vchan) && !lchan->desc) 468 468 ls2x_dma_start_transfer(lchan); 469 469 - spin_unlock_irqrestore(&lchan->vchan.lock, flags); 470 469 } 471 470 472 471 /* ··· 477 478 static int ls2x_dma_terminate_all(struct dma_chan *chan) 478 479 { 479 480 struct ls2x_dma_chan *lchan = to_ldma_chan(chan); 480 480 - unsigned long flags; 481 481 LIST_HEAD(head); 482 482 483 483 - spin_lock_irqsave(&lchan->vchan.lock, flags); 484 484 - /* Setting stop cmd */ 485 485 - ls2x_dma_write_cmd(lchan, LDMA_STOP); 486 486 - if (lchan->desc) { 487 487 - vchan_terminate_vdesc(&lchan->desc->vdesc); 488 488 - lchan->desc = NULL; 489 489 - } 483 483 + scoped_guard(spinlock_irqsave, &lchan->vchan.lock) { 484 484 + /* Setting stop cmd */ 485 485 + ls2x_dma_write_cmd(lchan, LDMA_STOP); 486 486 + if (lchan->desc) { 487 487 + vchan_terminate_vdesc(&lchan->desc->vdesc); 488 488 + lchan->desc = NULL; 489 489 + } 490 490 491 491 - vchan_get_all_descriptors(&lchan->vchan, &head); 492 492 - spin_unlock_irqrestore(&lchan->vchan.lock, flags); 491 491 + vchan_get_all_descriptors(&lchan->vchan, &head); 492 492 + } 493 493 494 494 vchan_dma_desc_free_list(&lchan->vchan, &head); 495 495 return 0; ··· 509 511 static int ls2x_dma_pause(struct dma_chan *chan) 510 512 { 511 513 struct ls2x_dma_chan *lchan = to_ldma_chan(chan); 512 512 - unsigned long flags; 513 514 514 514 - spin_lock_irqsave(&lchan->vchan.lock, flags); 515 515 + guard(spinlock_irqsave)(&lchan->vchan.lock); 516 516 + 515 517 if (lchan->desc && lchan->desc->status == DMA_IN_PROGRESS) { 516 518 ls2x_dma_write_cmd(lchan, LDMA_STOP); 517 519 lchan->desc->status = DMA_PAUSED; 518 520 } 519 519 - spin_unlock_irqrestore(&lchan->vchan.lock, flags); 520 521 521 522 return 0; 522 523 } ··· 523 526 static int ls2x_dma_resume(struct dma_chan *chan) 524 527 { 525 528 struct ls2x_dma_chan *lchan = to_ldma_chan(chan); 526 526 - unsigned long flags; 527 529 528 528 - spin_lock_irqsave(&lchan->vchan.lock, flags); 530 530 + guard(spinlock_irqsave)(&lchan->vchan.lock); 531 531 + 529 532 if (lchan->desc && lchan->desc->status == DMA_PAUSED) { 530 533 lchan->desc->status = DMA_IN_PROGRESS; 531 534 ls2x_dma_write_cmd(lchan, LDMA_START); 532 535 } 533 533 - spin_unlock_irqrestore(&lchan->vchan.lock, flags); 534 536 535 537 return 0; 536 538 } ··· 546 550 struct ls2x_dma_chan *lchan = dev_id; 547 551 struct ls2x_dma_desc *desc; 548 552 549 549 - spin_lock(&lchan->vchan.lock); 550 550 - desc = lchan->desc; 551 551 - if (desc) { 552 552 - if (desc->cyclic) { 553 553 - vchan_cyclic_callback(&desc->vdesc); 554 554 - } else { 555 555 - desc->status = DMA_COMPLETE; 556 556 - vchan_cookie_complete(&desc->vdesc); 557 557 - ls2x_dma_start_transfer(lchan); 558 558 - } 553 553 + scoped_guard(spinlock, &lchan->vchan.lock) { 554 554 + desc = lchan->desc; 555 555 + if (desc) { 556 556 + if (desc->cyclic) { 557 557 + vchan_cyclic_callback(&desc->vdesc); 558 558 + } else { 559 559 + desc->status = DMA_COMPLETE; 560 560 + vchan_cookie_complete(&desc->vdesc); 561 561 + ls2x_dma_start_transfer(lchan); 562 562 + } 559 563 560 560 - /* ls2x_dma_start_transfer() updates lchan->desc */ 561 561 - if (!lchan->desc) 562 562 - ls2x_dma_write_cmd(lchan, LDMA_STOP); 564 564 + /* ls2x_dma_start_transfer() updates lchan->desc */ 565 565 + if (!lchan->desc) 566 566 + ls2x_dma_write_cmd(lchan, LDMA_STOP); 567 567 + } 563 568 } 564 564 - spin_unlock(&lchan->vchan.lock); 565 569 566 570 return IRQ_HANDLED; 567 571 } ··· 612 616 return dev_err_probe(dev, PTR_ERR(priv->regs), 613 617 "devm_platform_ioremap_resource failed.\n"); 614 618 615 615 - priv->dma_clk = devm_clk_get(&pdev->dev, NULL); 619 619 + priv->dma_clk = devm_clk_get_enabled(dev, NULL); 616 620 if (IS_ERR(priv->dma_clk)) 617 617 - return dev_err_probe(dev, PTR_ERR(priv->dma_clk), "devm_clk_get failed.\n"); 618 618 - 619 619 - ret = clk_prepare_enable(priv->dma_clk); 620 620 - if (ret) 621 621 - return dev_err_probe(dev, ret, "clk_prepare_enable failed.\n"); 621 621 + return dev_err_probe(dev, PTR_ERR(priv->dma_clk), "Couldn't start the clock.\n"); 622 622 623 623 ret = ls2x_dma_chan_init(pdev, priv); 624 624 if (ret) 625 625 - goto disable_clk; 625 625 + return ret; 626 626 627 627 ddev = &priv->ddev; 628 628 ddev->dev = dev; ··· 642 650 ddev->dst_addr_widths = LDMA_SLAVE_BUSWIDTHS; 643 651 ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 644 652 645 645 - ret = dma_async_device_register(&priv->ddev); 653 653 + ret = dmaenginem_async_device_register(&priv->ddev); 646 654 if (ret < 0) 647 647 - goto disable_clk; 655 655 + return dev_err_probe(dev, ret, "Failed to register DMA engine device.\n"); 648 656 649 657 ret = of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id, priv); 650 658 if (ret < 0) 651 651 - goto unregister_dmac; 659 659 + return dev_err_probe(dev, ret, "Failed to register dma controller.\n"); 652 660 653 661 platform_set_drvdata(pdev, priv); 654 662 655 663 dev_info(dev, "Loongson LS2X APB DMA driver registered successfully.\n"); 656 664 return 0; 657 657 - 658 658 - unregister_dmac: 659 659 - dma_async_device_unregister(&priv->ddev); 660 660 - disable_clk: 661 661 - clk_disable_unprepare(priv->dma_clk); 662 662 - 663 663 - return ret; 664 665 } 665 666 666 667 /* ··· 662 677 */ 663 678 static void ls2x_dma_remove(struct platform_device *pdev) 664 679 { 665 665 - struct ls2x_dma_priv *priv = platform_get_drvdata(pdev); 666 666 - 667 680 of_dma_controller_free(pdev->dev.of_node); 668 668 - dma_async_device_unregister(&priv->ddev); 669 669 - clk_disable_unprepare(priv->dma_clk); 670 681 } 671 682 672 683 static const struct of_device_id ls2x_dma_of_match_table[] = {

+18 -19

drivers/dma/mxs-dma.c

reviewed

··· 744 744 { 745 745 struct device_node *np = pdev->dev.of_node; 746 746 const struct mxs_dma_type *dma_type; 747 747 + struct device *dev = &pdev->dev; 747 748 struct mxs_dma_engine *mxs_dma; 748 749 int ret, i; 749 750 750 750 - mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL); 751 751 + mxs_dma = devm_kzalloc(dev, sizeof(*mxs_dma), GFP_KERNEL); 751 752 if (!mxs_dma) 752 753 return -ENOMEM; 753 754 754 755 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels); 755 755 - if (ret) { 756 756 - dev_err(&pdev->dev, "failed to read dma-channels\n"); 757 757 - return ret; 758 758 - } 756 756 + if (ret) 757 757 + return dev_err_probe(dev, ret, "failed to read dma-channels\n"); 759 758 760 760 - dma_type = (struct mxs_dma_type *)of_device_get_match_data(&pdev->dev); 759 759 + dma_type = (struct mxs_dma_type *)of_device_get_match_data(dev); 761 760 mxs_dma->type = dma_type->type; 762 761 mxs_dma->dev_id = dma_type->id; 763 762 ··· 764 765 if (IS_ERR(mxs_dma->base)) 765 766 return PTR_ERR(mxs_dma->base); 766 767 767 767 - mxs_dma->clk = devm_clk_get(&pdev->dev, NULL); 768 768 + mxs_dma->clk = devm_clk_get(dev, NULL); 768 769 if (IS_ERR(mxs_dma->clk)) 769 770 return PTR_ERR(mxs_dma->clk); 770 771 ··· 794 795 return ret; 795 796 796 797 mxs_dma->pdev = pdev; 797 797 - mxs_dma->dma_device.dev = &pdev->dev; 798 798 + mxs_dma->dma_device.dev = dev; 798 799 799 800 /* mxs_dma gets 65535 bytes maximum sg size */ 800 800 - dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES); 801 801 + dma_set_max_seg_size(dev, MAX_XFER_BYTES); 801 802 802 803 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources; 803 804 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources; ··· 814 815 mxs_dma->dma_device.device_issue_pending = mxs_dma_enable_chan; 815 816 816 817 ret = dmaenginem_async_device_register(&mxs_dma->dma_device); 817 817 - if (ret) { 818 818 - dev_err(mxs_dma->dma_device.dev, "unable to register\n"); 819 819 - return ret; 820 820 - } 818 818 + if (ret) 819 819 + return dev_err_probe(dev, ret, "unable to register\n"); 821 820 822 822 - ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma); 823 823 - if (ret) { 824 824 - dev_err(mxs_dma->dma_device.dev, 825 825 - "failed to register controller\n"); 826 826 - } 821 821 + ret = devm_of_dma_controller_register(dev, np, mxs_dma_xlate, mxs_dma); 822 822 + if (ret) 823 823 + return dev_err_probe(dev, ret, 824 824 + "failed to register controller\n"); 827 825 828 828 - dev_info(mxs_dma->dma_device.dev, "initialized\n"); 826 826 + dev_info(dev, "initialized\n"); 829 827 830 828 return 0; 831 829 } ··· 836 840 }; 837 841 838 842 builtin_platform_driver(mxs_dma_driver); 843 843 + 844 844 + MODULE_DESCRIPTION("MXS DMA driver"); 845 845 + MODULE_LICENSE("GPL");

+246 -58

drivers/dma/sh/rz-dmac.c

reviewed

··· 16 16 #include <linux/interrupt.h> 17 17 #include <linux/iopoll.h> 18 18 #include <linux/irqchip/irq-renesas-rzv2h.h> 19 19 + #include <linux/irqchip/irq-renesas-rzt2h.h> 19 20 #include <linux/list.h> 20 21 #include <linux/module.h> 21 22 #include <linux/of.h> ··· 96 95 u8 dmac_index; 97 96 }; 98 97 98 98 + struct rz_dmac_info { 99 99 + void (*icu_register_dma_req)(struct platform_device *icu_dev, 100 100 + u8 dmac_index, u8 dmac_channel, u16 req_no); 101 101 + u16 default_dma_req_no; 102 102 + }; 103 103 + 99 104 struct rz_dmac { 100 105 struct dma_device engine; 101 106 struct rz_dmac_icu icu; 107 107 + const struct rz_dmac_info *info; 102 108 struct device *dev; 103 109 struct reset_control *rstc; 104 110 void __iomem *base; ··· 113 105 114 106 unsigned int n_channels; 115 107 struct rz_dmac_chan *channels; 116 116 - 117 117 - bool has_icu; 118 108 119 109 DECLARE_BITMAP(modules, 1024); 120 110 }; ··· 124 118 * Registers 125 119 */ 126 120 121 121 + #define CRTB 0x0020 127 122 #define CHSTAT 0x0024 128 123 #define CHCTRL 0x0028 129 124 #define CHCFG 0x002c 130 125 #define NXLA 0x0038 126 126 + #define CRLA 0x003c 131 127 132 128 #define DCTRL 0x0000 133 129 ··· 140 132 #define CHANNEL_8_15_COMMON_BASE 0x0700 141 133 142 134 #define CHSTAT_ER BIT(4) 135 135 + #define CHSTAT_SUS BIT(3) 143 136 #define CHSTAT_EN BIT(0) 144 137 145 138 #define CHCTRL_CLRINTMSK BIT(17) 146 139 #define CHCTRL_CLRSUS BIT(9) 140 140 + #define CHCTRL_SETSUS BIT(8) 147 141 #define CHCTRL_CLRTC BIT(6) 148 142 #define CHCTRL_CLREND BIT(5) 149 143 #define CHCTRL_CLRRQ BIT(4) ··· 276 266 { 277 267 struct dma_chan *chan = &channel->vc.chan; 278 268 struct rz_dmac *dmac = to_rz_dmac(chan->device); 279 279 - unsigned long flags; 280 269 u32 nxla; 281 270 u32 chctrl; 282 271 u32 chstat; 283 272 284 273 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); 285 285 - 286 286 - local_irq_save(flags); 287 274 288 275 rz_dmac_lmdesc_recycle(channel); 289 276 ··· 296 289 rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1); 297 290 rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1); 298 291 } 299 299 - 300 300 - local_irq_restore(flags); 301 292 } 302 293 303 294 static void rz_dmac_disable_hw(struct rz_dmac_chan *channel) ··· 321 316 rz_dmac_ext_writel(dmac, dmars32, dmars_offset); 322 317 } 323 318 319 319 + static void rz_dmac_set_dma_req_no(struct rz_dmac *dmac, unsigned int index, 320 320 + int req_no) 321 321 + { 322 322 + if (dmac->info->icu_register_dma_req) 323 323 + dmac->info->icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, 324 324 + index, req_no); 325 325 + else 326 326 + rz_dmac_set_dmars_register(dmac, index, req_no); 327 327 + } 328 328 + 324 329 static void rz_dmac_prepare_desc_for_memcpy(struct rz_dmac_chan *channel) 325 330 { 326 331 struct dma_chan *chan = &channel->vc.chan; ··· 348 333 lmdesc->chext = 0; 349 334 lmdesc->header = HEADER_LV; 350 335 351 351 - if (dmac->has_icu) { 352 352 - rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, 353 353 - channel->index, 354 354 - RZV2H_ICU_DMAC_REQ_NO_DEFAULT); 355 355 - } else { 356 356 - rz_dmac_set_dmars_register(dmac, channel->index, 0); 357 357 - } 336 336 + rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_no); 358 337 359 338 channel->chcfg = chcfg; 360 339 channel->chctrl = CHCTRL_STG | CHCTRL_SETEN; ··· 399 390 400 391 channel->lmdesc.tail = lmdesc; 401 392 402 402 - if (dmac->has_icu) { 403 403 - rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, 404 404 - channel->index, channel->mid_rid); 405 405 - } else { 406 406 - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); 407 407 - } 393 393 + rz_dmac_set_dma_req_no(dmac, channel->index, channel->mid_rid); 408 394 409 395 channel->chctrl = CHCTRL_SETEN; 410 396 } ··· 464 460 { 465 461 struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); 466 462 struct rz_dmac *dmac = to_rz_dmac(chan->device); 467 467 - struct rz_lmdesc *lmdesc = channel->lmdesc.base; 468 463 struct rz_dmac_desc *desc, *_desc; 469 464 unsigned long flags; 470 470 - unsigned int i; 471 465 472 466 spin_lock_irqsave(&channel->vc.lock, flags); 473 467 474 474 - for (i = 0; i < DMAC_NR_LMDESC; i++) 475 475 - lmdesc[i].header = 0; 468 468 + rz_lmdesc_setup(channel, channel->lmdesc.base); 476 469 477 470 rz_dmac_disable_hw(channel); 478 471 list_splice_tail_init(&channel->ld_active, &channel->ld_free); ··· 561 560 static int rz_dmac_terminate_all(struct dma_chan *chan) 562 561 { 563 562 struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); 564 564 - struct rz_lmdesc *lmdesc = channel->lmdesc.base; 565 563 unsigned long flags; 566 566 - unsigned int i; 567 564 LIST_HEAD(head); 568 565 569 566 spin_lock_irqsave(&channel->vc.lock, flags); 570 567 rz_dmac_disable_hw(channel); 571 571 - for (i = 0; i < DMAC_NR_LMDESC; i++) 572 572 - lmdesc[i].header = 0; 568 568 + rz_lmdesc_setup(channel, channel->lmdesc.base); 573 569 574 570 list_splice_tail_init(&channel->ld_active, &channel->ld_free); 575 571 list_splice_tail_init(&channel->ld_queue, &channel->ld_free); ··· 677 679 if (ret < 0) 678 680 dev_warn(dmac->dev, "DMA Timeout"); 679 681 680 680 - if (dmac->has_icu) { 681 681 - rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, 682 682 - channel->index, 683 683 - RZV2H_ICU_DMAC_REQ_NO_DEFAULT); 684 684 - } else { 685 685 - rz_dmac_set_dmars_register(dmac, channel->index, 0); 682 682 + rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_no); 683 683 + } 684 684 + 685 685 + static struct rz_lmdesc * 686 686 + rz_dmac_get_next_lmdesc(struct rz_lmdesc *base, struct rz_lmdesc *lmdesc) 687 687 + { 688 688 + struct rz_lmdesc *next = ++lmdesc; 689 689 + 690 690 + if (next >= base + DMAC_NR_LMDESC) 691 691 + next = base; 692 692 + 693 693 + return next; 694 694 + } 695 695 + 696 696 + static u32 rz_dmac_calculate_residue_bytes_in_vd(struct rz_dmac_chan *channel, u32 crla) 697 697 + { 698 698 + struct rz_lmdesc *lmdesc = channel->lmdesc.head; 699 699 + struct dma_chan *chan = &channel->vc.chan; 700 700 + struct rz_dmac *dmac = to_rz_dmac(chan->device); 701 701 + u32 residue = 0, i = 0; 702 702 + 703 703 + while (lmdesc->nxla != crla) { 704 704 + lmdesc = rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); 705 705 + if (++i >= DMAC_NR_LMDESC) 706 706 + return 0; 686 707 } 708 708 + 709 709 + /* Calculate residue from next lmdesc to end of virtual desc */ 710 710 + while (lmdesc->chcfg & CHCFG_DEM) { 711 711 + residue += lmdesc->tb; 712 712 + lmdesc = rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); 713 713 + } 714 714 + 715 715 + dev_dbg(dmac->dev, "%s: VD residue is %u\n", __func__, residue); 716 716 + 717 717 + return residue; 718 718 + } 719 719 + 720 720 + static u32 rz_dmac_chan_get_residue(struct rz_dmac_chan *channel, 721 721 + dma_cookie_t cookie) 722 722 + { 723 723 + struct rz_dmac_desc *current_desc, *desc; 724 724 + enum dma_status status; 725 725 + u32 crla, crtb, i; 726 726 + 727 727 + /* Get current processing virtual descriptor */ 728 728 + current_desc = list_first_entry(&channel->ld_active, 729 729 + struct rz_dmac_desc, node); 730 730 + if (!current_desc) 731 731 + return 0; 732 732 + 733 733 + /* 734 734 + * If the cookie corresponds to a descriptor that has been completed 735 735 + * there is no residue. The same check has already been performed by the 736 736 + * caller but without holding the channel lock, so the descriptor could 737 737 + * now be complete. 738 738 + */ 739 739 + status = dma_cookie_status(&channel->vc.chan, cookie, NULL); 740 740 + if (status == DMA_COMPLETE) 741 741 + return 0; 742 742 + 743 743 + /* 744 744 + * If the cookie doesn't correspond to the currently processing virtual 745 745 + * descriptor then the descriptor hasn't been processed yet, and the 746 746 + * residue is equal to the full descriptor size. Also, a client driver 747 747 + * is possible to call this function before rz_dmac_irq_handler_thread() 748 748 + * runs. In this case, the running descriptor will be the next 749 749 + * descriptor, and will appear in the done list. So, if the argument 750 750 + * cookie matches the done list's cookie, we can assume the residue is 751 751 + * zero. 752 752 + */ 753 753 + if (cookie != current_desc->vd.tx.cookie) { 754 754 + list_for_each_entry(desc, &channel->ld_free, node) { 755 755 + if (cookie == desc->vd.tx.cookie) 756 756 + return 0; 757 757 + } 758 758 + 759 759 + list_for_each_entry(desc, &channel->ld_queue, node) { 760 760 + if (cookie == desc->vd.tx.cookie) 761 761 + return desc->len; 762 762 + } 763 763 + 764 764 + list_for_each_entry(desc, &channel->ld_active, node) { 765 765 + if (cookie == desc->vd.tx.cookie) 766 766 + return desc->len; 767 767 + } 768 768 + 769 769 + /* 770 770 + * No descriptor found for the cookie, there's thus no residue. 771 771 + * This shouldn't happen if the calling driver passes a correct 772 772 + * cookie value. 773 773 + */ 774 774 + WARN(1, "No descriptor for cookie!"); 775 775 + return 0; 776 776 + } 777 777 + 778 778 + /* 779 779 + * We need to read two registers. Make sure the hardware does not move 780 780 + * to next lmdesc while reading the current lmdesc. Trying it 3 times 781 781 + * should be enough: initial read, retry, retry for the paranoid. 782 782 + */ 783 783 + for (i = 0; i < 3; i++) { 784 784 + crla = rz_dmac_ch_readl(channel, CRLA, 1); 785 785 + crtb = rz_dmac_ch_readl(channel, CRTB, 1); 786 786 + /* Still the same? */ 787 787 + if (crla == rz_dmac_ch_readl(channel, CRLA, 1)) 788 788 + break; 789 789 + } 790 790 + 791 791 + WARN_ONCE(i >= 3, "residue might not be continuous!"); 792 792 + 793 793 + /* 794 794 + * Calculate number of bytes transferred in processing virtual descriptor. 795 795 + * One virtual descriptor can have many lmdesc. 796 796 + */ 797 797 + return crtb + rz_dmac_calculate_residue_bytes_in_vd(channel, crla); 798 798 + } 799 799 + 800 800 + static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, 801 801 + dma_cookie_t cookie, 802 802 + struct dma_tx_state *txstate) 803 803 + { 804 804 + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); 805 805 + enum dma_status status; 806 806 + u32 residue; 807 807 + 808 808 + status = dma_cookie_status(chan, cookie, txstate); 809 809 + if (status == DMA_COMPLETE || !txstate) 810 810 + return status; 811 811 + 812 812 + scoped_guard(spinlock_irqsave, &channel->vc.lock) { 813 813 + u32 val; 814 814 + 815 815 + residue = rz_dmac_chan_get_residue(channel, cookie); 816 816 + 817 817 + val = rz_dmac_ch_readl(channel, CHSTAT, 1); 818 818 + if (val & CHSTAT_SUS) 819 819 + status = DMA_PAUSED; 820 820 + } 821 821 + 822 822 + /* if there's no residue and no paused, the cookie is complete */ 823 823 + if (!residue && status != DMA_PAUSED) 824 824 + return DMA_COMPLETE; 825 825 + 826 826 + dma_set_residue(txstate, residue); 827 827 + 828 828 + return status; 829 829 + } 830 830 + 831 831 + static int rz_dmac_device_pause(struct dma_chan *chan) 832 832 + { 833 833 + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); 834 834 + u32 val; 835 835 + 836 836 + guard(spinlock_irqsave)(&channel->vc.lock); 837 837 + 838 838 + val = rz_dmac_ch_readl(channel, CHSTAT, 1); 839 839 + if (!(val & CHSTAT_EN)) 840 840 + return 0; 841 841 + 842 842 + rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); 843 843 + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, 844 844 + (val & CHSTAT_SUS), 1, 1024, 845 845 + false, channel, CHSTAT, 1); 846 846 + } 847 847 + 848 848 + static int rz_dmac_device_resume(struct dma_chan *chan) 849 849 + { 850 850 + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); 851 851 + u32 val; 852 852 + 853 853 + guard(spinlock_irqsave)(&channel->vc.lock); 854 854 + 855 855 + /* Do not check CHSTAT_SUS but rely on HW capabilities. */ 856 856 + 857 857 + rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); 858 858 + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, 859 859 + !(val & CHSTAT_SUS), 1, 1024, 860 860 + false, channel, CHSTAT, 1); 687 861 } 688 862 689 863 /* ··· 867 697 { 868 698 struct dma_chan *chan = &channel->vc.chan; 869 699 struct rz_dmac *dmac = to_rz_dmac(chan->device); 870 870 - u32 chstat, chctrl; 700 700 + u32 chstat; 871 701 872 702 chstat = rz_dmac_ch_readl(channel, CHSTAT, 1); 873 703 if (chstat & CHSTAT_ER) { ··· 876 706 877 707 scoped_guard(spinlock_irqsave, &channel->vc.lock) 878 708 rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); 879 879 - goto done; 709 709 + return; 880 710 } 881 711 882 882 - chctrl = rz_dmac_ch_readl(channel, CHCTRL, 1); 883 883 - rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1); 884 884 - done: 885 885 - return; 712 712 + /* 713 713 + * No need to lock. This just clears the END interrupt. Writing 714 714 + * zeros to CHCTRL is just ignored by HW. 715 715 + */ 716 716 + rz_dmac_ch_writel(channel, CHCTRL_CLREND, CHCTRL, 1); 886 717 } 887 718 888 719 static irqreturn_t rz_dmac_irq_handler(int irq, void *dev_id) ··· 1047 876 uint32_t dmac_index; 1048 877 int ret; 1049 878 1050 1050 - ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args); 1051 1051 - if (ret == -ENOENT) 879 879 + if (!dmac->info->icu_register_dma_req) 1052 880 return 0; 881 881 + 882 882 + ret = of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args); 1053 883 if (ret) 1054 884 return ret; 1055 1055 - 1056 1056 - dmac->has_icu = true; 1057 885 1058 886 dmac->icu.pdev = of_find_device_by_node(args.np); 1059 887 of_node_put(args.np); ··· 1108 938 if (!dmac) 1109 939 return -ENOMEM; 1110 940 941 941 + dmac->info = device_get_match_data(&pdev->dev); 1111 942 dmac->dev = &pdev->dev; 1112 943 platform_set_drvdata(pdev, dmac); 1113 944 ··· 1126 955 if (IS_ERR(dmac->base)) 1127 956 return PTR_ERR(dmac->base); 1128 957 1129 1129 - if (!dmac->has_icu) { 958 958 + if (!dmac->info->icu_register_dma_req) { 1130 959 dmac->ext_base = devm_platform_ioremap_resource(pdev, 1); 1131 960 if (IS_ERR(dmac->ext_base)) 1132 961 return PTR_ERR(dmac->ext_base); 1133 962 } 1134 963 1135 964 /* Register interrupt handler for error */ 1136 1136 - irq = platform_get_irq_byname(pdev, irqname); 1137 1137 - if (irq < 0) 1138 1138 - return irq; 1139 1139 - 1140 1140 - ret = devm_request_irq(&pdev->dev, irq, rz_dmac_irq_handler, 0, 1141 1141 - irqname, NULL); 1142 1142 - if (ret) { 1143 1143 - dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n", 1144 1144 - irq, ret); 1145 1145 - return ret; 965 965 + irq = platform_get_irq_byname_optional(pdev, irqname); 966 966 + if (irq > 0) { 967 967 + ret = devm_request_irq(&pdev->dev, irq, rz_dmac_irq_handler, 0, 968 968 + irqname, NULL); 969 969 + if (ret) { 970 970 + dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n", 971 971 + irq, ret); 972 972 + return ret; 973 973 + } 1146 974 } 1147 975 1148 976 /* Initialize the channels. */ ··· 1179 1009 engine = &dmac->engine; 1180 1010 dma_cap_set(DMA_SLAVE, engine->cap_mask); 1181 1011 dma_cap_set(DMA_MEMCPY, engine->cap_mask); 1012 1012 + engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1182 1013 rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); 1183 1014 rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); 1184 1015 ··· 1187 1016 1188 1017 engine->device_alloc_chan_resources = rz_dmac_alloc_chan_resources; 1189 1018 engine->device_free_chan_resources = rz_dmac_free_chan_resources; 1190 1190 - engine->device_tx_status = dma_cookie_status; 1019 1019 + engine->device_tx_status = rz_dmac_tx_status; 1191 1020 engine->device_prep_slave_sg = rz_dmac_prep_slave_sg; 1192 1021 engine->device_prep_dma_memcpy = rz_dmac_prep_dma_memcpy; 1193 1022 engine->device_config = rz_dmac_config; 1194 1023 engine->device_terminate_all = rz_dmac_terminate_all; 1195 1024 engine->device_issue_pending = rz_dmac_issue_pending; 1196 1025 engine->device_synchronize = rz_dmac_device_synchronize; 1026 1026 + engine->device_pause = rz_dmac_device_pause; 1027 1027 + engine->device_resume = rz_dmac_device_resume; 1197 1028 1198 1029 engine->copy_align = DMAENGINE_ALIGN_1_BYTE; 1199 1030 dma_set_max_seg_size(engine->dev, U32_MAX); ··· 1249 1076 pm_runtime_disable(&pdev->dev); 1250 1077 } 1251 1078 1079 1079 + static const struct rz_dmac_info rz_dmac_v2h_info = { 1080 1080 + .icu_register_dma_req = rzv2h_icu_register_dma_req, 1081 1081 + .default_dma_req_no = RZV2H_ICU_DMAC_REQ_NO_DEFAULT, 1082 1082 + }; 1083 1083 + 1084 1084 + static const struct rz_dmac_info rz_dmac_t2h_info = { 1085 1085 + .icu_register_dma_req = rzt2h_icu_register_dma_req, 1086 1086 + .default_dma_req_no = RZT2H_ICU_DMAC_REQ_NO_DEFAULT, 1087 1087 + }; 1088 1088 + 1089 1089 + static const struct rz_dmac_info rz_dmac_generic_info = { 1090 1090 + .default_dma_req_no = 0, 1091 1091 + }; 1092 1092 + 1252 1093 static const struct of_device_id of_rz_dmac_match[] = { 1253 1253 - { .compatible = "renesas,r9a09g057-dmac", }, 1254 1254 - { .compatible = "renesas,rz-dmac", }, 1094 1094 + { .compatible = "renesas,r9a09g057-dmac", .data = &rz_dmac_v2h_info }, 1095 1095 + { .compatible = "renesas,r9a09g077-dmac", .data = &rz_dmac_t2h_info }, 1096 1096 + { .compatible = "renesas,rz-dmac", .data = &rz_dmac_generic_info }, 1255 1097 { /* Sentinel */ } 1256 1098 }; 1257 1099 MODULE_DEVICE_TABLE(of, of_rz_dmac_match);

+1437

drivers/dma/switchtec_dma.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Microchip Switchtec(tm) DMA Controller Driver 4 4 + * Copyright (c) 2025, Kelvin Cao <kelvin.cao@microchip.com> 5 5 + * Copyright (c) 2025, Microchip Corporation 6 6 + */ 7 7 + 8 8 + #include <linux/bitfield.h> 9 9 + #include <linux/circ_buf.h> 10 10 + #include <linux/dmaengine.h> 11 11 + #include <linux/module.h> 12 12 + #include <linux/pci.h> 13 13 + #include <linux/delay.h> 14 14 + #include <linux/iopoll.h> 15 15 + 16 16 + #include "dmaengine.h" 17 17 + 18 18 + MODULE_DESCRIPTION("Switchtec PCIe Switch DMA Engine"); 19 19 + MODULE_LICENSE("GPL"); 20 20 + MODULE_AUTHOR("Kelvin Cao"); 21 21 + 22 22 + #define SWITCHTEC_DMAC_CHAN_CTRL_OFFSET 0x1000 23 23 + #define SWITCHTEC_DMAC_CHAN_CFG_STS_OFFSET 0x160000 24 24 + 25 25 + #define SWITCHTEC_DMA_CHAN_HW_REGS_SIZE 0x1000 26 26 + #define SWITCHTEC_DMA_CHAN_FW_REGS_SIZE 0x80 27 27 + 28 28 + #define SWITCHTEC_REG_CAP 0x80 29 29 + #define SWITCHTEC_REG_CHAN_CNT 0x84 30 30 + #define SWITCHTEC_REG_TAG_LIMIT 0x90 31 31 + #define SWITCHTEC_REG_CHAN_STS_VEC 0x94 32 32 + #define SWITCHTEC_REG_SE_BUF_CNT 0x98 33 33 + #define SWITCHTEC_REG_SE_BUF_BASE 0x9a 34 34 + 35 35 + #define SWITCHTEC_DESC_MAX_SIZE 0x100000 36 36 + 37 37 + #define SWITCHTEC_CHAN_CTRL_PAUSE BIT(0) 38 38 + #define SWITCHTEC_CHAN_CTRL_HALT BIT(1) 39 39 + #define SWITCHTEC_CHAN_CTRL_RESET BIT(2) 40 40 + #define SWITCHTEC_CHAN_CTRL_ERR_PAUSE BIT(3) 41 41 + 42 42 + #define SWITCHTEC_CHAN_STS_PAUSED BIT(9) 43 43 + #define SWITCHTEC_CHAN_STS_HALTED BIT(10) 44 44 + #define SWITCHTEC_CHAN_STS_PAUSED_MASK GENMASK(29, 13) 45 45 + 46 46 + #define SWITCHTEC_INVALID_HFID 0xffff 47 47 + 48 48 + #define SWITCHTEC_DMA_SQ_SIZE SZ_32K 49 49 + #define SWITCHTEC_DMA_CQ_SIZE SZ_32K 50 50 + 51 51 + #define SWITCHTEC_DMA_RING_SIZE SZ_32K 52 52 + 53 53 + static const char * const channel_status_str[] = { 54 54 + [13] = "received a VDM with length error status", 55 55 + [14] = "received a VDM or Cpl with Unsupported Request error status", 56 56 + [15] = "received a VDM or Cpl with Completion Abort error status", 57 57 + [16] = "received a VDM with ECRC error status", 58 58 + [17] = "received a VDM with EP error status", 59 59 + [18] = "received a VDM with Reserved Cpl error status", 60 60 + [19] = "received only part of split SE CplD", 61 61 + [20] = "the ISP_DMAC detected a Completion Time Out", 62 62 + [21] = "received a Cpl with Unsupported Request status", 63 63 + [22] = "received a Cpl with Completion Abort status", 64 64 + [23] = "received a Cpl with a reserved status", 65 65 + [24] = "received a TLP with ECRC error status in its metadata", 66 66 + [25] = "received a TLP with the EP bit set in the header", 67 67 + [26] = "the ISP_DMAC tried to process a SE with an invalid Connection ID", 68 68 + [27] = "the ISP_DMAC tried to process a SE with an invalid Remote Host interrupt", 69 69 + [28] = "a reserved opcode was detected in an SE", 70 70 + [29] = "received a SE Cpl with error status", 71 71 + }; 72 72 + 73 73 + struct chan_hw_regs { 74 74 + u16 cq_head; 75 75 + u16 rsvd1; 76 76 + u16 sq_tail; 77 77 + u16 rsvd2; 78 78 + u8 ctrl; 79 79 + u8 rsvd3[3]; 80 80 + u16 status; 81 81 + u16 rsvd4; 82 82 + }; 83 83 + 84 84 + #define PERF_BURST_SCALE_MASK GENMASK_U32(3, 2) 85 85 + #define PERF_MRRS_MASK GENMASK_U32(6, 4) 86 86 + #define PERF_INTERVAL_MASK GENMASK_U32(10, 8) 87 87 + #define PERF_BURST_SIZE_MASK GENMASK_U32(14, 12) 88 88 + #define PERF_ARB_WEIGHT_MASK GENMASK_U32(31, 24) 89 89 + 90 90 + #define SE_BUF_BASE_MASK GENMASK_U32(10, 2) 91 91 + #define SE_BUF_LEN_MASK GENMASK_U32(20, 12) 92 92 + #define SE_THRESH_MASK GENMASK_U32(31, 23) 93 93 + 94 94 + #define SWITCHTEC_CHAN_ENABLE BIT(1) 95 95 + 96 96 + struct chan_fw_regs { 97 97 + u32 valid_en_se; 98 98 + u32 cq_base_lo; 99 99 + u32 cq_base_hi; 100 100 + u16 cq_size; 101 101 + u16 rsvd1; 102 102 + u32 sq_base_lo; 103 103 + u32 sq_base_hi; 104 104 + u16 sq_size; 105 105 + u16 rsvd2; 106 106 + u32 int_vec; 107 107 + u32 perf_cfg; 108 108 + u32 rsvd3; 109 109 + u32 perf_latency_selector; 110 110 + u32 perf_fetched_se_cnt_lo; 111 111 + u32 perf_fetched_se_cnt_hi; 112 112 + u32 perf_byte_cnt_lo; 113 113 + u32 perf_byte_cnt_hi; 114 114 + u32 rsvd4; 115 115 + u16 perf_se_pending; 116 116 + u16 perf_se_buf_empty; 117 117 + u32 perf_chan_idle; 118 118 + u32 perf_lat_max; 119 119 + u32 perf_lat_min; 120 120 + u32 perf_lat_last; 121 121 + u16 sq_current; 122 122 + u16 sq_phase; 123 123 + u16 cq_current; 124 124 + u16 cq_phase; 125 125 + }; 126 126 + 127 127 + struct switchtec_dma_chan { 128 128 + struct switchtec_dma_dev *swdma_dev; 129 129 + struct dma_chan dma_chan; 130 130 + struct chan_hw_regs __iomem *mmio_chan_hw; 131 131 + struct chan_fw_regs __iomem *mmio_chan_fw; 132 132 + 133 133 + /* Serialize hardware control register access */ 134 134 + spinlock_t hw_ctrl_lock; 135 135 + 136 136 + struct tasklet_struct desc_task; 137 137 + 138 138 + /* Serialize descriptor preparation */ 139 139 + spinlock_t submit_lock; 140 140 + bool ring_active; 141 141 + int cid; 142 142 + 143 143 + /* Serialize completion processing */ 144 144 + spinlock_t complete_lock; 145 145 + bool comp_ring_active; 146 146 + 147 147 + /* channel index and irq */ 148 148 + int index; 149 149 + int irq; 150 150 + 151 151 + /* 152 152 + * In driver context, head is advanced by producer while 153 153 + * tail is advanced by consumer. 154 154 + */ 155 155 + 156 156 + /* the head and tail for both desc_ring and hw_sq */ 157 157 + int head; 158 158 + int tail; 159 159 + int phase_tag; 160 160 + struct switchtec_dma_hw_se_desc *hw_sq; 161 161 + dma_addr_t dma_addr_sq; 162 162 + 163 163 + /* the tail for hw_cq */ 164 164 + int cq_tail; 165 165 + struct switchtec_dma_hw_ce *hw_cq; 166 166 + dma_addr_t dma_addr_cq; 167 167 + 168 168 + struct list_head list; 169 169 + 170 170 + struct switchtec_dma_desc *desc_ring[SWITCHTEC_DMA_RING_SIZE]; 171 171 + }; 172 172 + 173 173 + struct switchtec_dma_dev { 174 174 + struct dma_device dma_dev; 175 175 + struct pci_dev __rcu *pdev; 176 176 + void __iomem *bar; 177 177 + 178 178 + struct switchtec_dma_chan **swdma_chans; 179 179 + int chan_cnt; 180 180 + int chan_status_irq; 181 181 + }; 182 182 + 183 183 + enum chan_op { 184 184 + ENABLE_CHAN, 185 185 + DISABLE_CHAN, 186 186 + }; 187 187 + 188 188 + enum switchtec_dma_opcode { 189 189 + SWITCHTEC_DMA_OPC_MEMCPY = 0, 190 190 + SWITCHTEC_DMA_OPC_RDIMM = 0x1, 191 191 + SWITCHTEC_DMA_OPC_WRIMM = 0x2, 192 192 + SWITCHTEC_DMA_OPC_RHI = 0x6, 193 193 + SWITCHTEC_DMA_OPC_NOP = 0x7, 194 194 + }; 195 195 + 196 196 + struct switchtec_dma_hw_se_desc { 197 197 + u8 opc; 198 198 + u8 ctrl; 199 199 + __le16 tlp_setting; 200 200 + __le16 rsvd1; 201 201 + __le16 cid; 202 202 + __le32 byte_cnt; 203 203 + __le32 addr_lo; /* SADDR_LO/WIADDR_LO */ 204 204 + __le32 addr_hi; /* SADDR_HI/WIADDR_HI */ 205 205 + __le32 daddr_lo; 206 206 + __le32 daddr_hi; 207 207 + __le16 dfid; 208 208 + __le16 sfid; 209 209 + }; 210 210 + 211 211 + #define SWITCHTEC_SE_DFM BIT(5) 212 212 + #define SWITCHTEC_SE_LIOF BIT(6) 213 213 + #define SWITCHTEC_SE_BRR BIT(7) 214 214 + #define SWITCHTEC_SE_CID_MASK GENMASK(15, 0) 215 215 + 216 216 + #define SWITCHTEC_CE_SC_LEN_ERR BIT(0) 217 217 + #define SWITCHTEC_CE_SC_UR BIT(1) 218 218 + #define SWITCHTEC_CE_SC_CA BIT(2) 219 219 + #define SWITCHTEC_CE_SC_RSVD_CPL BIT(3) 220 220 + #define SWITCHTEC_CE_SC_ECRC_ERR BIT(4) 221 221 + #define SWITCHTEC_CE_SC_EP_SET BIT(5) 222 222 + #define SWITCHTEC_CE_SC_D_RD_CTO BIT(8) 223 223 + #define SWITCHTEC_CE_SC_D_RIMM_UR BIT(9) 224 224 + #define SWITCHTEC_CE_SC_D_RIMM_CA BIT(10) 225 225 + #define SWITCHTEC_CE_SC_D_RIMM_RSVD_CPL BIT(11) 226 226 + #define SWITCHTEC_CE_SC_D_ECRC BIT(12) 227 227 + #define SWITCHTEC_CE_SC_D_EP_SET BIT(13) 228 228 + #define SWITCHTEC_CE_SC_D_BAD_CONNID BIT(14) 229 229 + #define SWITCHTEC_CE_SC_D_BAD_RHI_ADDR BIT(15) 230 230 + #define SWITCHTEC_CE_SC_D_INVD_CMD BIT(16) 231 231 + #define SWITCHTEC_CE_SC_MASK GENMASK(16, 0) 232 232 + 233 233 + struct switchtec_dma_hw_ce { 234 234 + __le32 rdimm_cpl_dw0; 235 235 + __le32 rdimm_cpl_dw1; 236 236 + __le32 rsvd1; 237 237 + __le32 cpl_byte_cnt; 238 238 + __le16 sq_head; 239 239 + __le16 rsvd2; 240 240 + __le32 rsvd3; 241 241 + __le32 sts_code; 242 242 + __le16 cid; 243 243 + __le16 phase_tag; 244 244 + }; 245 245 + 246 246 + struct switchtec_dma_desc { 247 247 + struct dma_async_tx_descriptor txd; 248 248 + struct switchtec_dma_hw_se_desc *hw; 249 249 + u32 orig_size; 250 250 + bool completed; 251 251 + }; 252 252 + 253 253 + static int wait_for_chan_status(struct chan_hw_regs __iomem *chan_hw, u32 mask, 254 254 + bool set) 255 255 + { 256 256 + u32 status; 257 257 + 258 258 + return readl_poll_timeout_atomic(&chan_hw->status, status, 259 259 + (set && (status & mask)) || 260 260 + (!set && !(status & mask)), 261 261 + 10, 100 * USEC_PER_MSEC); 262 262 + } 263 263 + 264 264 + static int halt_channel(struct switchtec_dma_chan *swdma_chan) 265 265 + { 266 266 + struct chan_hw_regs __iomem *chan_hw = swdma_chan->mmio_chan_hw; 267 267 + struct pci_dev *pdev; 268 268 + int ret; 269 269 + 270 270 + rcu_read_lock(); 271 271 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 272 272 + if (!pdev) { 273 273 + ret = -ENODEV; 274 274 + goto unlock_and_exit; 275 275 + } 276 276 + 277 277 + spin_lock(&swdma_chan->hw_ctrl_lock); 278 278 + writeb(SWITCHTEC_CHAN_CTRL_HALT, &chan_hw->ctrl); 279 279 + ret = wait_for_chan_status(chan_hw, SWITCHTEC_CHAN_STS_HALTED, true); 280 280 + spin_unlock(&swdma_chan->hw_ctrl_lock); 281 281 + 282 282 + unlock_and_exit: 283 283 + rcu_read_unlock(); 284 284 + return ret; 285 285 + } 286 286 + 287 287 + static int unhalt_channel(struct switchtec_dma_chan *swdma_chan) 288 288 + { 289 289 + struct chan_hw_regs __iomem *chan_hw = swdma_chan->mmio_chan_hw; 290 290 + struct pci_dev *pdev; 291 291 + u8 ctrl; 292 292 + int ret; 293 293 + 294 294 + rcu_read_lock(); 295 295 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 296 296 + if (!pdev) { 297 297 + ret = -ENODEV; 298 298 + goto unlock_and_exit; 299 299 + } 300 300 + 301 301 + spin_lock(&swdma_chan->hw_ctrl_lock); 302 302 + ctrl = readb(&chan_hw->ctrl); 303 303 + ctrl &= ~SWITCHTEC_CHAN_CTRL_HALT; 304 304 + writeb(ctrl, &chan_hw->ctrl); 305 305 + ret = wait_for_chan_status(chan_hw, SWITCHTEC_CHAN_STS_HALTED, false); 306 306 + spin_unlock(&swdma_chan->hw_ctrl_lock); 307 307 + 308 308 + unlock_and_exit: 309 309 + rcu_read_unlock(); 310 310 + return ret; 311 311 + } 312 312 + 313 313 + static void flush_pci_write(struct chan_hw_regs __iomem *chan_hw) 314 314 + { 315 315 + readl(&chan_hw->cq_head); 316 316 + } 317 317 + 318 318 + static int reset_channel(struct switchtec_dma_chan *swdma_chan) 319 319 + { 320 320 + struct chan_hw_regs __iomem *chan_hw = swdma_chan->mmio_chan_hw; 321 321 + struct pci_dev *pdev; 322 322 + 323 323 + rcu_read_lock(); 324 324 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 325 325 + if (!pdev) { 326 326 + rcu_read_unlock(); 327 327 + return -ENODEV; 328 328 + } 329 329 + 330 330 + spin_lock(&swdma_chan->hw_ctrl_lock); 331 331 + writel(SWITCHTEC_CHAN_CTRL_RESET | SWITCHTEC_CHAN_CTRL_ERR_PAUSE, 332 332 + &chan_hw->ctrl); 333 333 + flush_pci_write(chan_hw); 334 334 + 335 335 + udelay(1000); 336 336 + 337 337 + writel(SWITCHTEC_CHAN_CTRL_ERR_PAUSE, &chan_hw->ctrl); 338 338 + spin_unlock(&swdma_chan->hw_ctrl_lock); 339 339 + flush_pci_write(chan_hw); 340 340 + 341 341 + rcu_read_unlock(); 342 342 + return 0; 343 343 + } 344 344 + 345 345 + static int pause_reset_channel(struct switchtec_dma_chan *swdma_chan) 346 346 + { 347 347 + struct chan_hw_regs __iomem *chan_hw = swdma_chan->mmio_chan_hw; 348 348 + struct pci_dev *pdev; 349 349 + 350 350 + rcu_read_lock(); 351 351 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 352 352 + if (!pdev) { 353 353 + rcu_read_unlock(); 354 354 + return -ENODEV; 355 355 + } 356 356 + 357 357 + spin_lock(&swdma_chan->hw_ctrl_lock); 358 358 + writeb(SWITCHTEC_CHAN_CTRL_PAUSE, &chan_hw->ctrl); 359 359 + spin_unlock(&swdma_chan->hw_ctrl_lock); 360 360 + 361 361 + flush_pci_write(chan_hw); 362 362 + 363 363 + rcu_read_unlock(); 364 364 + 365 365 + /* wait 60ms to ensure no pending CEs */ 366 366 + mdelay(60); 367 367 + 368 368 + return reset_channel(swdma_chan); 369 369 + } 370 370 + 371 371 + static int channel_op(struct switchtec_dma_chan *swdma_chan, int op) 372 372 + { 373 373 + struct chan_fw_regs __iomem *chan_fw = swdma_chan->mmio_chan_fw; 374 374 + struct pci_dev *pdev; 375 375 + u32 valid_en_se; 376 376 + 377 377 + rcu_read_lock(); 378 378 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 379 379 + if (!pdev) { 380 380 + rcu_read_unlock(); 381 381 + return -ENODEV; 382 382 + } 383 383 + 384 384 + valid_en_se = readl(&chan_fw->valid_en_se); 385 385 + if (op == ENABLE_CHAN) 386 386 + valid_en_se |= SWITCHTEC_CHAN_ENABLE; 387 387 + else 388 388 + valid_en_se &= ~SWITCHTEC_CHAN_ENABLE; 389 389 + 390 390 + writel(valid_en_se, &chan_fw->valid_en_se); 391 391 + 392 392 + rcu_read_unlock(); 393 393 + return 0; 394 394 + } 395 395 + 396 396 + static int enable_channel(struct switchtec_dma_chan *swdma_chan) 397 397 + { 398 398 + return channel_op(swdma_chan, ENABLE_CHAN); 399 399 + } 400 400 + 401 401 + static int disable_channel(struct switchtec_dma_chan *swdma_chan) 402 402 + { 403 403 + return channel_op(swdma_chan, DISABLE_CHAN); 404 404 + } 405 405 + 406 406 + static void 407 407 + switchtec_dma_cleanup_completed(struct switchtec_dma_chan *swdma_chan) 408 408 + { 409 409 + struct device *chan_dev = &swdma_chan->dma_chan.dev->device; 410 410 + struct switchtec_dma_desc *desc; 411 411 + struct switchtec_dma_hw_ce *ce; 412 412 + struct dmaengine_result res; 413 413 + int tail, cid, se_idx, i; 414 414 + __le16 phase_tag; 415 415 + u32 sts_code; 416 416 + __le32 *p; 417 417 + 418 418 + do { 419 419 + spin_lock_bh(&swdma_chan->complete_lock); 420 420 + if (!swdma_chan->comp_ring_active) { 421 421 + spin_unlock_bh(&swdma_chan->complete_lock); 422 422 + break; 423 423 + } 424 424 + 425 425 + ce = &swdma_chan->hw_cq[swdma_chan->cq_tail]; 426 426 + /* 427 427 + * phase_tag is updated by hardware, ensure the value is 428 428 + * not from the cache 429 429 + */ 430 430 + phase_tag = smp_load_acquire(&ce->phase_tag); 431 431 + if (le16_to_cpu(phase_tag) == swdma_chan->phase_tag) { 432 432 + spin_unlock_bh(&swdma_chan->complete_lock); 433 433 + break; 434 434 + } 435 435 + 436 436 + cid = le16_to_cpu(ce->cid); 437 437 + se_idx = cid & (SWITCHTEC_DMA_SQ_SIZE - 1); 438 438 + desc = swdma_chan->desc_ring[se_idx]; 439 439 + 440 440 + tail = swdma_chan->tail; 441 441 + 442 442 + res.residue = desc->orig_size - le32_to_cpu(ce->cpl_byte_cnt); 443 443 + 444 444 + sts_code = le32_to_cpu(ce->sts_code); 445 445 + 446 446 + if (!(sts_code & SWITCHTEC_CE_SC_MASK)) { 447 447 + res.result = DMA_TRANS_NOERROR; 448 448 + } else { 449 449 + if (sts_code & SWITCHTEC_CE_SC_D_RD_CTO) 450 450 + res.result = DMA_TRANS_READ_FAILED; 451 451 + else 452 452 + res.result = DMA_TRANS_WRITE_FAILED; 453 453 + 454 454 + dev_err(chan_dev, "CID 0x%04x failed, SC 0x%08x\n", cid, 455 455 + (u32)(sts_code & SWITCHTEC_CE_SC_MASK)); 456 456 + 457 457 + p = (__le32 *)ce; 458 458 + for (i = 0; i < sizeof(*ce) / 4; i++) { 459 459 + dev_err(chan_dev, "CE DW%d: 0x%08x\n", i, 460 460 + le32_to_cpu(*p)); 461 461 + p++; 462 462 + } 463 463 + } 464 464 + 465 465 + desc->completed = true; 466 466 + 467 467 + swdma_chan->cq_tail++; 468 468 + swdma_chan->cq_tail &= SWITCHTEC_DMA_CQ_SIZE - 1; 469 469 + 470 470 + rcu_read_lock(); 471 471 + if (!rcu_dereference(swdma_chan->swdma_dev->pdev)) { 472 472 + rcu_read_unlock(); 473 473 + spin_unlock_bh(&swdma_chan->complete_lock); 474 474 + return; 475 475 + } 476 476 + writew(swdma_chan->cq_tail, &swdma_chan->mmio_chan_hw->cq_head); 477 477 + rcu_read_unlock(); 478 478 + 479 479 + if (swdma_chan->cq_tail == 0) 480 480 + swdma_chan->phase_tag = !swdma_chan->phase_tag; 481 481 + 482 482 + /* Out of order CE */ 483 483 + if (se_idx != tail) { 484 484 + spin_unlock_bh(&swdma_chan->complete_lock); 485 485 + continue; 486 486 + } 487 487 + 488 488 + do { 489 489 + dma_cookie_complete(&desc->txd); 490 490 + dma_descriptor_unmap(&desc->txd); 491 491 + dmaengine_desc_get_callback_invoke(&desc->txd, &res); 492 492 + desc->txd.callback = NULL; 493 493 + desc->txd.callback_result = NULL; 494 494 + desc->completed = false; 495 495 + 496 496 + tail++; 497 497 + tail &= SWITCHTEC_DMA_SQ_SIZE - 1; 498 498 + 499 499 + /* 500 500 + * Ensure the desc updates are visible before updating 501 501 + * the tail index 502 502 + */ 503 503 + smp_store_release(&swdma_chan->tail, tail); 504 504 + desc = swdma_chan->desc_ring[swdma_chan->tail]; 505 505 + if (!desc->completed) 506 506 + break; 507 507 + } while (CIRC_CNT(READ_ONCE(swdma_chan->head), swdma_chan->tail, 508 508 + SWITCHTEC_DMA_SQ_SIZE)); 509 509 + 510 510 + spin_unlock_bh(&swdma_chan->complete_lock); 511 511 + } while (1); 512 512 + } 513 513 + 514 514 + static void 515 515 + switchtec_dma_abort_desc(struct switchtec_dma_chan *swdma_chan, int force) 516 516 + { 517 517 + struct switchtec_dma_desc *desc; 518 518 + struct dmaengine_result res; 519 519 + 520 520 + if (!force) 521 521 + switchtec_dma_cleanup_completed(swdma_chan); 522 522 + 523 523 + spin_lock_bh(&swdma_chan->complete_lock); 524 524 + 525 525 + while (CIRC_CNT(swdma_chan->head, swdma_chan->tail, 526 526 + SWITCHTEC_DMA_SQ_SIZE) >= 1) { 527 527 + desc = swdma_chan->desc_ring[swdma_chan->tail]; 528 528 + 529 529 + res.residue = desc->orig_size; 530 530 + res.result = DMA_TRANS_ABORTED; 531 531 + 532 532 + dma_cookie_complete(&desc->txd); 533 533 + dma_descriptor_unmap(&desc->txd); 534 534 + if (!force) 535 535 + dmaengine_desc_get_callback_invoke(&desc->txd, &res); 536 536 + desc->txd.callback = NULL; 537 537 + desc->txd.callback_result = NULL; 538 538 + 539 539 + swdma_chan->tail++; 540 540 + swdma_chan->tail &= SWITCHTEC_DMA_SQ_SIZE - 1; 541 541 + } 542 542 + 543 543 + spin_unlock_bh(&swdma_chan->complete_lock); 544 544 + } 545 545 + 546 546 + static void switchtec_dma_chan_stop(struct switchtec_dma_chan *swdma_chan) 547 547 + { 548 548 + int rc; 549 549 + 550 550 + rc = halt_channel(swdma_chan); 551 551 + if (rc) 552 552 + return; 553 553 + 554 554 + rcu_read_lock(); 555 555 + if (!rcu_dereference(swdma_chan->swdma_dev->pdev)) { 556 556 + rcu_read_unlock(); 557 557 + return; 558 558 + } 559 559 + 560 560 + writel(0, &swdma_chan->mmio_chan_fw->sq_base_lo); 561 561 + writel(0, &swdma_chan->mmio_chan_fw->sq_base_hi); 562 562 + writel(0, &swdma_chan->mmio_chan_fw->cq_base_lo); 563 563 + writel(0, &swdma_chan->mmio_chan_fw->cq_base_hi); 564 564 + 565 565 + rcu_read_unlock(); 566 566 + } 567 567 + 568 568 + static int switchtec_dma_terminate_all(struct dma_chan *chan) 569 569 + { 570 570 + struct switchtec_dma_chan *swdma_chan = 571 571 + container_of(chan, struct switchtec_dma_chan, dma_chan); 572 572 + 573 573 + spin_lock_bh(&swdma_chan->complete_lock); 574 574 + swdma_chan->comp_ring_active = false; 575 575 + spin_unlock_bh(&swdma_chan->complete_lock); 576 576 + 577 577 + return pause_reset_channel(swdma_chan); 578 578 + } 579 579 + 580 580 + static void switchtec_dma_synchronize(struct dma_chan *chan) 581 581 + { 582 582 + struct switchtec_dma_chan *swdma_chan = 583 583 + container_of(chan, struct switchtec_dma_chan, dma_chan); 584 584 + 585 585 + int rc; 586 586 + 587 587 + switchtec_dma_abort_desc(swdma_chan, 1); 588 588 + 589 589 + rc = enable_channel(swdma_chan); 590 590 + if (rc) 591 591 + return; 592 592 + 593 593 + rc = reset_channel(swdma_chan); 594 594 + if (rc) 595 595 + return; 596 596 + 597 597 + rc = unhalt_channel(swdma_chan); 598 598 + if (rc) 599 599 + return; 600 600 + 601 601 + spin_lock_bh(&swdma_chan->submit_lock); 602 602 + swdma_chan->head = 0; 603 603 + spin_unlock_bh(&swdma_chan->submit_lock); 604 604 + 605 605 + spin_lock_bh(&swdma_chan->complete_lock); 606 606 + swdma_chan->comp_ring_active = true; 607 607 + swdma_chan->phase_tag = 0; 608 608 + swdma_chan->tail = 0; 609 609 + swdma_chan->cq_tail = 0; 610 610 + swdma_chan->cid = 0; 611 611 + dma_cookie_init(chan); 612 612 + spin_unlock_bh(&swdma_chan->complete_lock); 613 613 + } 614 614 + 615 615 + static struct dma_async_tx_descriptor * 616 616 + switchtec_dma_prep_desc(struct dma_chan *c, u16 dst_fid, dma_addr_t dma_dst, 617 617 + u16 src_fid, dma_addr_t dma_src, u64 data, 618 618 + size_t len, unsigned long flags) 619 619 + __acquires(swdma_chan->submit_lock) 620 620 + { 621 621 + struct switchtec_dma_chan *swdma_chan = 622 622 + container_of(c, struct switchtec_dma_chan, dma_chan); 623 623 + struct switchtec_dma_desc *desc; 624 624 + int head, tail; 625 625 + 626 626 + spin_lock_bh(&swdma_chan->submit_lock); 627 627 + 628 628 + if (!swdma_chan->ring_active) 629 629 + goto err_unlock; 630 630 + 631 631 + tail = READ_ONCE(swdma_chan->tail); 632 632 + head = swdma_chan->head; 633 633 + 634 634 + if (!CIRC_SPACE(head, tail, SWITCHTEC_DMA_RING_SIZE)) 635 635 + goto err_unlock; 636 636 + 637 637 + desc = swdma_chan->desc_ring[head]; 638 638 + 639 639 + if (src_fid != SWITCHTEC_INVALID_HFID && 640 640 + dst_fid != SWITCHTEC_INVALID_HFID) 641 641 + desc->hw->ctrl |= SWITCHTEC_SE_DFM; 642 642 + 643 643 + if (flags & DMA_PREP_INTERRUPT) 644 644 + desc->hw->ctrl |= SWITCHTEC_SE_LIOF; 645 645 + 646 646 + if (flags & DMA_PREP_FENCE) 647 647 + desc->hw->ctrl |= SWITCHTEC_SE_BRR; 648 648 + 649 649 + desc->txd.flags = flags; 650 650 + 651 651 + desc->completed = false; 652 652 + desc->hw->opc = SWITCHTEC_DMA_OPC_MEMCPY; 653 653 + desc->hw->addr_lo = cpu_to_le32(lower_32_bits(dma_src)); 654 654 + desc->hw->addr_hi = cpu_to_le32(upper_32_bits(dma_src)); 655 655 + desc->hw->daddr_lo = cpu_to_le32(lower_32_bits(dma_dst)); 656 656 + desc->hw->daddr_hi = cpu_to_le32(upper_32_bits(dma_dst)); 657 657 + desc->hw->byte_cnt = cpu_to_le32(len); 658 658 + desc->hw->tlp_setting = 0; 659 659 + desc->hw->dfid = cpu_to_le16(dst_fid); 660 660 + desc->hw->sfid = cpu_to_le16(src_fid); 661 661 + swdma_chan->cid &= SWITCHTEC_SE_CID_MASK; 662 662 + desc->hw->cid = cpu_to_le16(swdma_chan->cid++); 663 663 + desc->orig_size = len; 664 664 + 665 665 + /* return with the lock held, it will be released in tx_submit */ 666 666 + 667 667 + return &desc->txd; 668 668 + 669 669 + err_unlock: 670 670 + /* 671 671 + * Keep sparse happy by restoring an even lock count on 672 672 + * this lock. 673 673 + */ 674 674 + __acquire(swdma_chan->submit_lock); 675 675 + 676 676 + spin_unlock_bh(&swdma_chan->submit_lock); 677 677 + return NULL; 678 678 + } 679 679 + 680 680 + static struct dma_async_tx_descriptor * 681 681 + switchtec_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dst, 682 682 + dma_addr_t dma_src, size_t len, unsigned long flags) 683 683 + __acquires(swdma_chan->submit_lock) 684 684 + { 685 685 + if (len > SWITCHTEC_DESC_MAX_SIZE) { 686 686 + /* 687 687 + * Keep sparse happy by restoring an even lock count on 688 688 + * this lock. 689 689 + */ 690 690 + __acquire(swdma_chan->submit_lock); 691 691 + return NULL; 692 692 + } 693 693 + 694 694 + return switchtec_dma_prep_desc(c, SWITCHTEC_INVALID_HFID, dma_dst, 695 695 + SWITCHTEC_INVALID_HFID, dma_src, 0, len, 696 696 + flags); 697 697 + } 698 698 + 699 699 + static dma_cookie_t 700 700 + switchtec_dma_tx_submit(struct dma_async_tx_descriptor *desc) 701 701 + __releases(swdma_chan->submit_lock) 702 702 + { 703 703 + struct switchtec_dma_chan *swdma_chan = 704 704 + container_of(desc->chan, struct switchtec_dma_chan, dma_chan); 705 705 + dma_cookie_t cookie; 706 706 + int head; 707 707 + 708 708 + head = swdma_chan->head + 1; 709 709 + head &= SWITCHTEC_DMA_RING_SIZE - 1; 710 710 + 711 711 + /* 712 712 + * Ensure the desc updates are visible before updating the head index 713 713 + */ 714 714 + smp_store_release(&swdma_chan->head, head); 715 715 + 716 716 + cookie = dma_cookie_assign(desc); 717 717 + 718 718 + spin_unlock_bh(&swdma_chan->submit_lock); 719 719 + 720 720 + return cookie; 721 721 + } 722 722 + 723 723 + static enum dma_status switchtec_dma_tx_status(struct dma_chan *chan, 724 724 + dma_cookie_t cookie, struct dma_tx_state *txstate) 725 725 + { 726 726 + struct switchtec_dma_chan *swdma_chan = 727 727 + container_of(chan, struct switchtec_dma_chan, dma_chan); 728 728 + enum dma_status ret; 729 729 + 730 730 + ret = dma_cookie_status(chan, cookie, txstate); 731 731 + if (ret == DMA_COMPLETE) 732 732 + return ret; 733 733 + 734 734 + /* 735 735 + * For jobs where the interrupts are disabled, this is the only place 736 736 + * to process the completions returned by the hardware. Callers that 737 737 + * disable interrupts must call tx_status() to determine when a job 738 738 + * is done, so it is safe to process completions here. If a job has 739 739 + * interrupts enabled, then the completions will normally be processed 740 740 + * in the tasklet that is triggered by the interrupt and tx_status() 741 741 + * does not need to be called. 742 742 + */ 743 743 + switchtec_dma_cleanup_completed(swdma_chan); 744 744 + 745 745 + return dma_cookie_status(chan, cookie, txstate); 746 746 + } 747 747 + 748 748 + static void switchtec_dma_issue_pending(struct dma_chan *chan) 749 749 + { 750 750 + struct switchtec_dma_chan *swdma_chan = 751 751 + container_of(chan, struct switchtec_dma_chan, dma_chan); 752 752 + struct switchtec_dma_dev *swdma_dev = swdma_chan->swdma_dev; 753 753 + 754 754 + /* 755 755 + * The sq_tail register is actually for the head of the 756 756 + * submisssion queue. Chip has the opposite define of head/tail 757 757 + * to the Linux kernel. 758 758 + */ 759 759 + 760 760 + rcu_read_lock(); 761 761 + if (!rcu_dereference(swdma_dev->pdev)) { 762 762 + rcu_read_unlock(); 763 763 + return; 764 764 + } 765 765 + 766 766 + spin_lock_bh(&swdma_chan->submit_lock); 767 767 + writew(swdma_chan->head, &swdma_chan->mmio_chan_hw->sq_tail); 768 768 + spin_unlock_bh(&swdma_chan->submit_lock); 769 769 + 770 770 + rcu_read_unlock(); 771 771 + } 772 772 + 773 773 + static int switchtec_dma_pause(struct dma_chan *chan) 774 774 + { 775 775 + struct switchtec_dma_chan *swdma_chan = 776 776 + container_of(chan, struct switchtec_dma_chan, dma_chan); 777 777 + struct chan_hw_regs __iomem *chan_hw = swdma_chan->mmio_chan_hw; 778 778 + struct pci_dev *pdev; 779 779 + int ret; 780 780 + 781 781 + rcu_read_lock(); 782 782 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 783 783 + if (!pdev) { 784 784 + ret = -ENODEV; 785 785 + goto unlock_and_exit; 786 786 + } 787 787 + 788 788 + spin_lock(&swdma_chan->hw_ctrl_lock); 789 789 + writeb(SWITCHTEC_CHAN_CTRL_PAUSE, &chan_hw->ctrl); 790 790 + ret = wait_for_chan_status(chan_hw, SWITCHTEC_CHAN_STS_PAUSED, true); 791 791 + spin_unlock(&swdma_chan->hw_ctrl_lock); 792 792 + 793 793 + unlock_and_exit: 794 794 + rcu_read_unlock(); 795 795 + return ret; 796 796 + } 797 797 + 798 798 + static int switchtec_dma_resume(struct dma_chan *chan) 799 799 + { 800 800 + struct switchtec_dma_chan *swdma_chan = 801 801 + container_of(chan, struct switchtec_dma_chan, dma_chan); 802 802 + struct chan_hw_regs __iomem *chan_hw = swdma_chan->mmio_chan_hw; 803 803 + struct pci_dev *pdev; 804 804 + int ret; 805 805 + 806 806 + rcu_read_lock(); 807 807 + pdev = rcu_dereference(swdma_chan->swdma_dev->pdev); 808 808 + if (!pdev) { 809 809 + ret = -ENODEV; 810 810 + goto unlock_and_exit; 811 811 + } 812 812 + 813 813 + spin_lock(&swdma_chan->hw_ctrl_lock); 814 814 + writeb(0, &chan_hw->ctrl); 815 815 + ret = wait_for_chan_status(chan_hw, SWITCHTEC_CHAN_STS_PAUSED, false); 816 816 + spin_unlock(&swdma_chan->hw_ctrl_lock); 817 817 + 818 818 + unlock_and_exit: 819 819 + rcu_read_unlock(); 820 820 + return ret; 821 821 + } 822 822 + 823 823 + static void switchtec_dma_desc_task(unsigned long data) 824 824 + { 825 825 + struct switchtec_dma_chan *swdma_chan = (void *)data; 826 826 + 827 827 + switchtec_dma_cleanup_completed(swdma_chan); 828 828 + } 829 829 + 830 830 + static irqreturn_t switchtec_dma_isr(int irq, void *chan) 831 831 + { 832 832 + struct switchtec_dma_chan *swdma_chan = chan; 833 833 + 834 834 + if (swdma_chan->comp_ring_active) 835 835 + tasklet_schedule(&swdma_chan->desc_task); 836 836 + 837 837 + return IRQ_HANDLED; 838 838 + } 839 839 + 840 840 + static irqreturn_t switchtec_dma_chan_status_isr(int irq, void *dma) 841 841 + { 842 842 + struct switchtec_dma_dev *swdma_dev = dma; 843 843 + struct dma_device *dma_dev = &swdma_dev->dma_dev; 844 844 + struct switchtec_dma_chan *swdma_chan; 845 845 + struct chan_hw_regs __iomem *chan_hw; 846 846 + struct device *chan_dev; 847 847 + struct dma_chan *chan; 848 848 + u32 chan_status; 849 849 + int bit; 850 850 + 851 851 + list_for_each_entry(chan, &dma_dev->channels, device_node) { 852 852 + swdma_chan = container_of(chan, struct switchtec_dma_chan, 853 853 + dma_chan); 854 854 + chan_dev = &swdma_chan->dma_chan.dev->device; 855 855 + chan_hw = swdma_chan->mmio_chan_hw; 856 856 + 857 857 + rcu_read_lock(); 858 858 + if (!rcu_dereference(swdma_dev->pdev)) { 859 859 + rcu_read_unlock(); 860 860 + goto out; 861 861 + } 862 862 + 863 863 + chan_status = readl(&chan_hw->status); 864 864 + chan_status &= SWITCHTEC_CHAN_STS_PAUSED_MASK; 865 865 + rcu_read_unlock(); 866 866 + 867 867 + bit = ffs(chan_status); 868 868 + if (!bit) 869 869 + dev_dbg(chan_dev, "No pause bit set.\n"); 870 870 + else 871 871 + dev_err(chan_dev, "Paused, %s\n", 872 872 + channel_status_str[bit - 1]); 873 873 + } 874 874 + 875 875 + out: 876 876 + return IRQ_HANDLED; 877 877 + } 878 878 + 879 879 + static void switchtec_dma_free_desc(struct switchtec_dma_chan *swdma_chan) 880 880 + { 881 881 + struct switchtec_dma_dev *swdma_dev = swdma_chan->swdma_dev; 882 882 + size_t size; 883 883 + int i; 884 884 + 885 885 + size = SWITCHTEC_DMA_SQ_SIZE * sizeof(*swdma_chan->hw_sq); 886 886 + if (swdma_chan->hw_sq) 887 887 + dma_free_coherent(swdma_dev->dma_dev.dev, size, 888 888 + swdma_chan->hw_sq, swdma_chan->dma_addr_sq); 889 889 + 890 890 + size = SWITCHTEC_DMA_CQ_SIZE * sizeof(*swdma_chan->hw_cq); 891 891 + if (swdma_chan->hw_cq) 892 892 + dma_free_coherent(swdma_dev->dma_dev.dev, size, 893 893 + swdma_chan->hw_cq, swdma_chan->dma_addr_cq); 894 894 + 895 895 + for (i = 0; i < SWITCHTEC_DMA_RING_SIZE; i++) 896 896 + kfree(swdma_chan->desc_ring[i]); 897 897 + } 898 898 + 899 899 + static int switchtec_dma_alloc_desc(struct switchtec_dma_chan *swdma_chan) 900 900 + { 901 901 + struct switchtec_dma_dev *swdma_dev = swdma_chan->swdma_dev; 902 902 + struct chan_fw_regs __iomem *chan_fw = swdma_chan->mmio_chan_fw; 903 903 + struct switchtec_dma_desc *desc; 904 904 + struct pci_dev *pdev; 905 905 + size_t size; 906 906 + int rc, i; 907 907 + 908 908 + swdma_chan->head = 0; 909 909 + swdma_chan->tail = 0; 910 910 + swdma_chan->cq_tail = 0; 911 911 + 912 912 + size = SWITCHTEC_DMA_SQ_SIZE * sizeof(*swdma_chan->hw_sq); 913 913 + swdma_chan->hw_sq = dma_alloc_coherent(swdma_dev->dma_dev.dev, size, 914 914 + &swdma_chan->dma_addr_sq, 915 915 + GFP_NOWAIT); 916 916 + if (!swdma_chan->hw_sq) { 917 917 + rc = -ENOMEM; 918 918 + goto free_and_exit; 919 919 + } 920 920 + 921 921 + size = SWITCHTEC_DMA_CQ_SIZE * sizeof(*swdma_chan->hw_cq); 922 922 + swdma_chan->hw_cq = dma_alloc_coherent(swdma_dev->dma_dev.dev, size, 923 923 + &swdma_chan->dma_addr_cq, 924 924 + GFP_NOWAIT); 925 925 + if (!swdma_chan->hw_cq) { 926 926 + rc = -ENOMEM; 927 927 + goto free_and_exit; 928 928 + } 929 929 + 930 930 + /* reset host phase tag */ 931 931 + swdma_chan->phase_tag = 0; 932 932 + 933 933 + for (i = 0; i < SWITCHTEC_DMA_RING_SIZE; i++) { 934 934 + desc = kzalloc_obj(*desc, GFP_NOWAIT); 935 935 + if (!desc) { 936 936 + rc = -ENOMEM; 937 937 + goto free_and_exit; 938 938 + } 939 939 + 940 940 + dma_async_tx_descriptor_init(&desc->txd, &swdma_chan->dma_chan); 941 941 + desc->txd.tx_submit = switchtec_dma_tx_submit; 942 942 + desc->hw = &swdma_chan->hw_sq[i]; 943 943 + desc->completed = true; 944 944 + 945 945 + swdma_chan->desc_ring[i] = desc; 946 946 + } 947 947 + 948 948 + rcu_read_lock(); 949 949 + pdev = rcu_dereference(swdma_dev->pdev); 950 950 + if (!pdev) { 951 951 + rcu_read_unlock(); 952 952 + rc = -ENODEV; 953 953 + goto free_and_exit; 954 954 + } 955 955 + 956 956 + /* set sq/cq */ 957 957 + writel(lower_32_bits(swdma_chan->dma_addr_sq), &chan_fw->sq_base_lo); 958 958 + writel(upper_32_bits(swdma_chan->dma_addr_sq), &chan_fw->sq_base_hi); 959 959 + writel(lower_32_bits(swdma_chan->dma_addr_cq), &chan_fw->cq_base_lo); 960 960 + writel(upper_32_bits(swdma_chan->dma_addr_cq), &chan_fw->cq_base_hi); 961 961 + 962 962 + writew(SWITCHTEC_DMA_SQ_SIZE, &swdma_chan->mmio_chan_fw->sq_size); 963 963 + writew(SWITCHTEC_DMA_CQ_SIZE, &swdma_chan->mmio_chan_fw->cq_size); 964 964 + 965 965 + rcu_read_unlock(); 966 966 + return 0; 967 967 + 968 968 + free_and_exit: 969 969 + switchtec_dma_free_desc(swdma_chan); 970 970 + return rc; 971 971 + } 972 972 + 973 973 + static int switchtec_dma_alloc_chan_resources(struct dma_chan *chan) 974 974 + { 975 975 + struct switchtec_dma_chan *swdma_chan = 976 976 + container_of(chan, struct switchtec_dma_chan, dma_chan); 977 977 + struct switchtec_dma_dev *swdma_dev = swdma_chan->swdma_dev; 978 978 + u32 perf_cfg; 979 979 + int rc; 980 980 + 981 981 + rc = switchtec_dma_alloc_desc(swdma_chan); 982 982 + if (rc) 983 983 + return rc; 984 984 + 985 985 + rc = enable_channel(swdma_chan); 986 986 + if (rc) 987 987 + return rc; 988 988 + 989 989 + rc = reset_channel(swdma_chan); 990 990 + if (rc) 991 991 + return rc; 992 992 + 993 993 + rc = unhalt_channel(swdma_chan); 994 994 + if (rc) 995 995 + return rc; 996 996 + 997 997 + swdma_chan->ring_active = true; 998 998 + swdma_chan->comp_ring_active = true; 999 999 + swdma_chan->cid = 0; 1000 1000 + 1001 1001 + dma_cookie_init(chan); 1002 1002 + 1003 1003 + rcu_read_lock(); 1004 1004 + if (!rcu_dereference(swdma_dev->pdev)) { 1005 1005 + rcu_read_unlock(); 1006 1006 + return -ENODEV; 1007 1007 + } 1008 1008 + 1009 1009 + perf_cfg = readl(&swdma_chan->mmio_chan_fw->perf_cfg); 1010 1010 + rcu_read_unlock(); 1011 1011 + 1012 1012 + dev_dbg(&chan->dev->device, "Burst Size: 0x%x\n", 1013 1013 + FIELD_GET(PERF_BURST_SIZE_MASK, perf_cfg)); 1014 1014 + 1015 1015 + dev_dbg(&chan->dev->device, "Burst Scale: 0x%x\n", 1016 1016 + FIELD_GET(PERF_BURST_SCALE_MASK, perf_cfg)); 1017 1017 + 1018 1018 + dev_dbg(&chan->dev->device, "Interval: 0x%x\n", 1019 1019 + FIELD_GET(PERF_INTERVAL_MASK, perf_cfg)); 1020 1020 + 1021 1021 + dev_dbg(&chan->dev->device, "Arb Weight: 0x%x\n", 1022 1022 + FIELD_GET(PERF_ARB_WEIGHT_MASK, perf_cfg)); 1023 1023 + 1024 1024 + dev_dbg(&chan->dev->device, "MRRS: 0x%x\n", 1025 1025 + FIELD_GET(PERF_MRRS_MASK, perf_cfg)); 1026 1026 + 1027 1027 + return SWITCHTEC_DMA_SQ_SIZE; 1028 1028 + } 1029 1029 + 1030 1030 + static void switchtec_dma_free_chan_resources(struct dma_chan *chan) 1031 1031 + { 1032 1032 + struct switchtec_dma_chan *swdma_chan = 1033 1033 + container_of(chan, struct switchtec_dma_chan, dma_chan); 1034 1034 + 1035 1035 + spin_lock_bh(&swdma_chan->submit_lock); 1036 1036 + swdma_chan->ring_active = false; 1037 1037 + spin_unlock_bh(&swdma_chan->submit_lock); 1038 1038 + 1039 1039 + spin_lock_bh(&swdma_chan->complete_lock); 1040 1040 + swdma_chan->comp_ring_active = false; 1041 1041 + spin_unlock_bh(&swdma_chan->complete_lock); 1042 1042 + 1043 1043 + switchtec_dma_chan_stop(swdma_chan); 1044 1044 + switchtec_dma_abort_desc(swdma_chan, 0); 1045 1045 + switchtec_dma_free_desc(swdma_chan); 1046 1046 + 1047 1047 + disable_channel(swdma_chan); 1048 1048 + } 1049 1049 + 1050 1050 + static int switchtec_dma_chan_init(struct switchtec_dma_dev *swdma_dev, 1051 1051 + struct pci_dev *pdev, int i) 1052 1052 + { 1053 1053 + struct dma_device *dma = &swdma_dev->dma_dev; 1054 1054 + struct switchtec_dma_chan *swdma_chan; 1055 1055 + u32 valid_en_se, thresh; 1056 1056 + int se_buf_len, irq, rc; 1057 1057 + struct dma_chan *chan; 1058 1058 + 1059 1059 + swdma_chan = kzalloc_obj(*swdma_chan, GFP_KERNEL); 1060 1060 + if (!swdma_chan) 1061 1061 + return -ENOMEM; 1062 1062 + 1063 1063 + swdma_chan->phase_tag = 0; 1064 1064 + swdma_chan->index = i; 1065 1065 + swdma_chan->swdma_dev = swdma_dev; 1066 1066 + 1067 1067 + spin_lock_init(&swdma_chan->hw_ctrl_lock); 1068 1068 + spin_lock_init(&swdma_chan->submit_lock); 1069 1069 + spin_lock_init(&swdma_chan->complete_lock); 1070 1070 + tasklet_init(&swdma_chan->desc_task, switchtec_dma_desc_task, 1071 1071 + (unsigned long)swdma_chan); 1072 1072 + 1073 1073 + swdma_chan->mmio_chan_fw = 1074 1074 + swdma_dev->bar + SWITCHTEC_DMAC_CHAN_CFG_STS_OFFSET + 1075 1075 + i * SWITCHTEC_DMA_CHAN_FW_REGS_SIZE; 1076 1076 + swdma_chan->mmio_chan_hw = 1077 1077 + swdma_dev->bar + SWITCHTEC_DMAC_CHAN_CTRL_OFFSET + 1078 1078 + i * SWITCHTEC_DMA_CHAN_HW_REGS_SIZE; 1079 1079 + 1080 1080 + swdma_dev->swdma_chans[i] = swdma_chan; 1081 1081 + 1082 1082 + rc = pause_reset_channel(swdma_chan); 1083 1083 + if (rc) 1084 1084 + goto free_and_exit; 1085 1085 + 1086 1086 + /* init perf tuner */ 1087 1087 + writel(FIELD_PREP(PERF_BURST_SCALE_MASK, 1) | 1088 1088 + FIELD_PREP(PERF_MRRS_MASK, 3) | 1089 1089 + FIELD_PREP(PERF_BURST_SIZE_MASK, 6) | 1090 1090 + FIELD_PREP(PERF_ARB_WEIGHT_MASK, 1), 1091 1091 + &swdma_chan->mmio_chan_fw->perf_cfg); 1092 1092 + 1093 1093 + valid_en_se = readl(&swdma_chan->mmio_chan_fw->valid_en_se); 1094 1094 + 1095 1095 + dev_dbg(&pdev->dev, "Channel %d: SE buffer base %d\n", i, 1096 1096 + FIELD_GET(SE_BUF_BASE_MASK, valid_en_se)); 1097 1097 + 1098 1098 + se_buf_len = FIELD_GET(SE_BUF_LEN_MASK, valid_en_se); 1099 1099 + dev_dbg(&pdev->dev, "Channel %d: SE buffer count %d\n", i, se_buf_len); 1100 1100 + 1101 1101 + thresh = se_buf_len / 2; 1102 1102 + valid_en_se |= FIELD_GET(SE_THRESH_MASK, thresh); 1103 1103 + writel(valid_en_se, &swdma_chan->mmio_chan_fw->valid_en_se); 1104 1104 + 1105 1105 + /* request irqs */ 1106 1106 + irq = readl(&swdma_chan->mmio_chan_fw->int_vec); 1107 1107 + dev_dbg(&pdev->dev, "Channel %d: CE irq vector %d\n", i, irq); 1108 1108 + 1109 1109 + rc = pci_request_irq(pdev, irq, switchtec_dma_isr, NULL, swdma_chan, 1110 1110 + KBUILD_MODNAME); 1111 1111 + if (rc) 1112 1112 + goto free_and_exit; 1113 1113 + 1114 1114 + swdma_chan->irq = irq; 1115 1115 + 1116 1116 + chan = &swdma_chan->dma_chan; 1117 1117 + chan->device = dma; 1118 1118 + dma_cookie_init(chan); 1119 1119 + 1120 1120 + list_add_tail(&chan->device_node, &dma->channels); 1121 1121 + 1122 1122 + return 0; 1123 1123 + 1124 1124 + free_and_exit: 1125 1125 + kfree(swdma_chan); 1126 1126 + return rc; 1127 1127 + } 1128 1128 + 1129 1129 + static int switchtec_dma_chan_free(struct pci_dev *pdev, 1130 1130 + struct switchtec_dma_chan *swdma_chan) 1131 1131 + { 1132 1132 + spin_lock_bh(&swdma_chan->submit_lock); 1133 1133 + swdma_chan->ring_active = false; 1134 1134 + spin_unlock_bh(&swdma_chan->submit_lock); 1135 1135 + 1136 1136 + spin_lock_bh(&swdma_chan->complete_lock); 1137 1137 + swdma_chan->comp_ring_active = false; 1138 1138 + spin_unlock_bh(&swdma_chan->complete_lock); 1139 1139 + 1140 1140 + pci_free_irq(pdev, swdma_chan->irq, swdma_chan); 1141 1141 + tasklet_kill(&swdma_chan->desc_task); 1142 1142 + 1143 1143 + switchtec_dma_chan_stop(swdma_chan); 1144 1144 + 1145 1145 + return 0; 1146 1146 + } 1147 1147 + 1148 1148 + static int switchtec_dma_chans_release(struct pci_dev *pdev, 1149 1149 + struct switchtec_dma_dev *swdma_dev) 1150 1150 + { 1151 1151 + int i; 1152 1152 + 1153 1153 + for (i = 0; i < swdma_dev->chan_cnt; i++) 1154 1154 + switchtec_dma_chan_free(pdev, swdma_dev->swdma_chans[i]); 1155 1155 + 1156 1156 + return 0; 1157 1157 + } 1158 1158 + 1159 1159 + static int switchtec_dma_chans_enumerate(struct switchtec_dma_dev *swdma_dev, 1160 1160 + struct pci_dev *pdev, int chan_cnt) 1161 1161 + { 1162 1162 + struct dma_device *dma = &swdma_dev->dma_dev; 1163 1163 + int base, cnt, rc, i; 1164 1164 + 1165 1165 + swdma_dev->swdma_chans = kcalloc(chan_cnt, sizeof(*swdma_dev->swdma_chans), 1166 1166 + GFP_KERNEL); 1167 1167 + 1168 1168 + if (!swdma_dev->swdma_chans) 1169 1169 + return -ENOMEM; 1170 1170 + 1171 1171 + base = readw(swdma_dev->bar + SWITCHTEC_REG_SE_BUF_BASE); 1172 1172 + cnt = readw(swdma_dev->bar + SWITCHTEC_REG_SE_BUF_CNT); 1173 1173 + 1174 1174 + dev_dbg(&pdev->dev, "EP SE buffer base %d\n", base); 1175 1175 + dev_dbg(&pdev->dev, "EP SE buffer count %d\n", cnt); 1176 1176 + 1177 1177 + INIT_LIST_HEAD(&dma->channels); 1178 1178 + 1179 1179 + for (i = 0; i < chan_cnt; i++) { 1180 1180 + rc = switchtec_dma_chan_init(swdma_dev, pdev, i); 1181 1181 + if (rc) { 1182 1182 + dev_err(&pdev->dev, "Channel %d: init channel failed\n", 1183 1183 + i); 1184 1184 + chan_cnt = i; 1185 1185 + goto err_exit; 1186 1186 + } 1187 1187 + } 1188 1188 + 1189 1189 + return chan_cnt; 1190 1190 + 1191 1191 + err_exit: 1192 1192 + for (i = 0; i < chan_cnt; i++) 1193 1193 + switchtec_dma_chan_free(pdev, swdma_dev->swdma_chans[i]); 1194 1194 + 1195 1195 + kfree(swdma_dev->swdma_chans); 1196 1196 + 1197 1197 + return rc; 1198 1198 + } 1199 1199 + 1200 1200 + static void switchtec_dma_release(struct dma_device *dma_dev) 1201 1201 + { 1202 1202 + struct switchtec_dma_dev *swdma_dev = 1203 1203 + container_of(dma_dev, struct switchtec_dma_dev, dma_dev); 1204 1204 + int i; 1205 1205 + 1206 1206 + for (i = 0; i < swdma_dev->chan_cnt; i++) 1207 1207 + kfree(swdma_dev->swdma_chans[i]); 1208 1208 + 1209 1209 + kfree(swdma_dev->swdma_chans); 1210 1210 + 1211 1211 + put_device(dma_dev->dev); 1212 1212 + kfree(swdma_dev); 1213 1213 + } 1214 1214 + 1215 1215 + static int switchtec_dma_create(struct pci_dev *pdev) 1216 1216 + { 1217 1217 + struct switchtec_dma_dev *swdma_dev; 1218 1218 + int chan_cnt, nr_vecs, irq, rc; 1219 1219 + struct dma_device *dma; 1220 1220 + struct dma_chan *chan; 1221 1221 + 1222 1222 + /* 1223 1223 + * Create the switchtec dma device 1224 1224 + */ 1225 1225 + swdma_dev = kzalloc_obj(*swdma_dev, GFP_KERNEL); 1226 1226 + if (!swdma_dev) 1227 1227 + return -ENOMEM; 1228 1228 + 1229 1229 + swdma_dev->bar = ioremap(pci_resource_start(pdev, 0), 1230 1230 + pci_resource_len(pdev, 0)); 1231 1231 + 1232 1232 + RCU_INIT_POINTER(swdma_dev->pdev, pdev); 1233 1233 + 1234 1234 + nr_vecs = pci_msix_vec_count(pdev); 1235 1235 + rc = pci_alloc_irq_vectors(pdev, nr_vecs, nr_vecs, PCI_IRQ_MSIX); 1236 1236 + if (rc < 0) 1237 1237 + goto err_exit; 1238 1238 + 1239 1239 + irq = readw(swdma_dev->bar + SWITCHTEC_REG_CHAN_STS_VEC); 1240 1240 + pci_dbg(pdev, "Channel pause irq vector %d\n", irq); 1241 1241 + 1242 1242 + rc = pci_request_irq(pdev, irq, NULL, switchtec_dma_chan_status_isr, 1243 1243 + swdma_dev, KBUILD_MODNAME); 1244 1244 + if (rc) 1245 1245 + goto err_exit; 1246 1246 + 1247 1247 + swdma_dev->chan_status_irq = irq; 1248 1248 + 1249 1249 + chan_cnt = readl(swdma_dev->bar + SWITCHTEC_REG_CHAN_CNT); 1250 1250 + if (!chan_cnt) { 1251 1251 + pci_err(pdev, "No channel configured.\n"); 1252 1252 + rc = -ENXIO; 1253 1253 + goto err_exit; 1254 1254 + } 1255 1255 + 1256 1256 + chan_cnt = switchtec_dma_chans_enumerate(swdma_dev, pdev, chan_cnt); 1257 1257 + if (chan_cnt < 0) { 1258 1258 + pci_err(pdev, "Failed to enumerate dma channels: %d\n", 1259 1259 + chan_cnt); 1260 1260 + rc = -ENXIO; 1261 1261 + goto err_exit; 1262 1262 + } 1263 1263 + 1264 1264 + swdma_dev->chan_cnt = chan_cnt; 1265 1265 + 1266 1266 + dma = &swdma_dev->dma_dev; 1267 1267 + dma->copy_align = DMAENGINE_ALIGN_8_BYTES; 1268 1268 + dma_cap_set(DMA_MEMCPY, dma->cap_mask); 1269 1269 + dma_cap_set(DMA_PRIVATE, dma->cap_mask); 1270 1270 + dma->dev = get_device(&pdev->dev); 1271 1271 + 1272 1272 + dma->device_alloc_chan_resources = switchtec_dma_alloc_chan_resources; 1273 1273 + dma->device_free_chan_resources = switchtec_dma_free_chan_resources; 1274 1274 + dma->device_prep_dma_memcpy = switchtec_dma_prep_memcpy; 1275 1275 + dma->device_tx_status = switchtec_dma_tx_status; 1276 1276 + dma->device_issue_pending = switchtec_dma_issue_pending; 1277 1277 + dma->device_pause = switchtec_dma_pause; 1278 1278 + dma->device_resume = switchtec_dma_resume; 1279 1279 + dma->device_terminate_all = switchtec_dma_terminate_all; 1280 1280 + dma->device_synchronize = switchtec_dma_synchronize; 1281 1281 + dma->device_release = switchtec_dma_release; 1282 1282 + 1283 1283 + rc = dma_async_device_register(dma); 1284 1284 + if (rc) { 1285 1285 + pci_err(pdev, "Failed to register dma device: %d\n", rc); 1286 1286 + goto err_chans_release_exit; 1287 1287 + } 1288 1288 + 1289 1289 + pci_dbg(pdev, "Channel count: %d\n", chan_cnt); 1290 1290 + 1291 1291 + list_for_each_entry(chan, &dma->channels, device_node) 1292 1292 + pci_dbg(pdev, "%s\n", dma_chan_name(chan)); 1293 1293 + 1294 1294 + pci_set_drvdata(pdev, swdma_dev); 1295 1295 + 1296 1296 + return 0; 1297 1297 + 1298 1298 + err_chans_release_exit: 1299 1299 + switchtec_dma_chans_release(pdev, swdma_dev); 1300 1300 + 1301 1301 + err_exit: 1302 1302 + if (swdma_dev->chan_status_irq) 1303 1303 + free_irq(swdma_dev->chan_status_irq, swdma_dev); 1304 1304 + 1305 1305 + iounmap(swdma_dev->bar); 1306 1306 + kfree(swdma_dev); 1307 1307 + return rc; 1308 1308 + } 1309 1309 + 1310 1310 + static int switchtec_dma_probe(struct pci_dev *pdev, 1311 1311 + const struct pci_device_id *id) 1312 1312 + { 1313 1313 + int rc; 1314 1314 + 1315 1315 + rc = pci_enable_device(pdev); 1316 1316 + if (rc) 1317 1317 + return rc; 1318 1318 + 1319 1319 + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1320 1320 + 1321 1321 + rc = pci_request_mem_regions(pdev, KBUILD_MODNAME); 1322 1322 + if (rc) 1323 1323 + goto err_disable; 1324 1324 + 1325 1325 + pci_set_master(pdev); 1326 1326 + 1327 1327 + rc = switchtec_dma_create(pdev); 1328 1328 + if (rc) 1329 1329 + goto err_free; 1330 1330 + 1331 1331 + return 0; 1332 1332 + 1333 1333 + err_free: 1334 1334 + pci_free_irq_vectors(pdev); 1335 1335 + pci_release_mem_regions(pdev); 1336 1336 + 1337 1337 + err_disable: 1338 1338 + pci_disable_device(pdev); 1339 1339 + 1340 1340 + return rc; 1341 1341 + } 1342 1342 + 1343 1343 + static void switchtec_dma_remove(struct pci_dev *pdev) 1344 1344 + { 1345 1345 + struct switchtec_dma_dev *swdma_dev = pci_get_drvdata(pdev); 1346 1346 + 1347 1347 + switchtec_dma_chans_release(pdev, swdma_dev); 1348 1348 + 1349 1349 + rcu_assign_pointer(swdma_dev->pdev, NULL); 1350 1350 + synchronize_rcu(); 1351 1351 + 1352 1352 + pci_free_irq(pdev, swdma_dev->chan_status_irq, swdma_dev); 1353 1353 + 1354 1354 + pci_free_irq_vectors(pdev); 1355 1355 + 1356 1356 + dma_async_device_unregister(&swdma_dev->dma_dev); 1357 1357 + 1358 1358 + iounmap(swdma_dev->bar); 1359 1359 + pci_release_mem_regions(pdev); 1360 1360 + pci_disable_device(pdev); 1361 1361 + } 1362 1362 + 1363 1363 + /* 1364 1364 + * Also use the class code to identify the devices, as some of the 1365 1365 + * device IDs are also used for other devices with other classes by 1366 1366 + * Microsemi. 1367 1367 + */ 1368 1368 + #define SW_ID(vendor_id, device_id) \ 1369 1369 + { \ 1370 1370 + .vendor = vendor_id, \ 1371 1371 + .device = device_id, \ 1372 1372 + .subvendor = PCI_ANY_ID, \ 1373 1373 + .subdevice = PCI_ANY_ID, \ 1374 1374 + .class = PCI_CLASS_SYSTEM_OTHER << 8, \ 1375 1375 + .class_mask = 0xffffffff, \ 1376 1376 + } 1377 1377 + 1378 1378 + static const struct pci_device_id switchtec_dma_pci_tbl[] = { 1379 1379 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4000), /* PFX 100XG4 */ 1380 1380 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4084), /* PFX 84XG4 */ 1381 1381 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4068), /* PFX 68XG4 */ 1382 1382 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4052), /* PFX 52XG4 */ 1383 1383 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4036), /* PFX 36XG4 */ 1384 1384 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4028), /* PFX 28XG4 */ 1385 1385 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4100), /* PSX 100XG4 */ 1386 1386 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4184), /* PSX 84XG4 */ 1387 1387 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4168), /* PSX 68XG4 */ 1388 1388 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4152), /* PSX 52XG4 */ 1389 1389 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4136), /* PSX 36XG4 */ 1390 1390 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4128), /* PSX 28XG4 */ 1391 1391 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4352), /* PFXA 52XG4 */ 1392 1392 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4336), /* PFXA 36XG4 */ 1393 1393 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4328), /* PFXA 28XG4 */ 1394 1394 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4452), /* PSXA 52XG4 */ 1395 1395 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4436), /* PSXA 36XG4 */ 1396 1396 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x4428), /* PSXA 28XG4 */ 1397 1397 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5000), /* PFX 100XG5 */ 1398 1398 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5084), /* PFX 84XG5 */ 1399 1399 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5068), /* PFX 68XG5 */ 1400 1400 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5052), /* PFX 52XG5 */ 1401 1401 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5036), /* PFX 36XG5 */ 1402 1402 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5028), /* PFX 28XG5 */ 1403 1403 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5100), /* PSX 100XG5 */ 1404 1404 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5184), /* PSX 84XG5 */ 1405 1405 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5168), /* PSX 68XG5 */ 1406 1406 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5152), /* PSX 52XG5 */ 1407 1407 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5136), /* PSX 36XG5 */ 1408 1408 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5128), /* PSX 28XG5 */ 1409 1409 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5300), /* PFXA 100XG5 */ 1410 1410 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5384), /* PFXA 84XG5 */ 1411 1411 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5368), /* PFXA 68XG5 */ 1412 1412 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5352), /* PFXA 52XG5 */ 1413 1413 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5336), /* PFXA 36XG5 */ 1414 1414 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5328), /* PFXA 28XG5 */ 1415 1415 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5400), /* PSXA 100XG5 */ 1416 1416 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5484), /* PSXA 84XG5 */ 1417 1417 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5468), /* PSXA 68XG5 */ 1418 1418 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5452), /* PSXA 52XG5 */ 1419 1419 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5436), /* PSXA 36XG5 */ 1420 1420 + SW_ID(PCI_VENDOR_ID_MICROSEMI, 0x5428), /* PSXA 28XG5 */ 1421 1421 + SW_ID(PCI_VENDOR_ID_EFAR, 0x1001), /* PCI1001 16XG4 */ 1422 1422 + SW_ID(PCI_VENDOR_ID_EFAR, 0x1002), /* PCI1002 16XG4 */ 1423 1423 + SW_ID(PCI_VENDOR_ID_EFAR, 0x1003), /* PCI1003 16XG4 */ 1424 1424 + SW_ID(PCI_VENDOR_ID_EFAR, 0x1004), /* PCI1004 16XG4 */ 1425 1425 + SW_ID(PCI_VENDOR_ID_EFAR, 0x1005), /* PCI1005 16XG4 */ 1426 1426 + SW_ID(PCI_VENDOR_ID_EFAR, 0x1006), /* PCI1006 16XG4 */ 1427 1427 + {0} 1428 1428 + }; 1429 1429 + MODULE_DEVICE_TABLE(pci, switchtec_dma_pci_tbl); 1430 1430 + 1431 1431 + static struct pci_driver switchtec_dma_pci_driver = { 1432 1432 + .name = KBUILD_MODNAME, 1433 1433 + .id_table = switchtec_dma_pci_tbl, 1434 1434 + .probe = switchtec_dma_probe, 1435 1435 + .remove = switchtec_dma_remove, 1436 1436 + }; 1437 1437 + module_pci_driver(switchtec_dma_pci_driver);

+2

drivers/dma/xilinx/xdma.c

reviewed

··· 61 61 * @dir: Transferring direction of the channel 62 62 * @cfg: Transferring config of the channel 63 63 * @irq: IRQ assigned to the channel 64 64 + * @last_interrupt: task for comppleting last interrupt 65 65 + * @stop_requested: stop request flag 64 66 */ 65 67 struct xdma_chan { 66 68 struct virt_dma_chan vchan;

+3 -5

drivers/dma/xilinx/xilinx_dma.c

reviewed

··· 3194 3194 = axivdma_clk_init; 3195 3195 struct device_node *node = pdev->dev.of_node; 3196 3196 struct xilinx_dma_device *xdev; 3197 3197 - struct device_node *child, *np = pdev->dev.of_node; 3197 3197 + struct device_node *np = pdev->dev.of_node; 3198 3198 u32 num_frames, addr_width = XILINX_DMA_DFAULT_ADDRWIDTH, len_width; 3199 3199 int i, err; 3200 3200 ··· 3334 3334 platform_set_drvdata(pdev, xdev); 3335 3335 3336 3336 /* Initialize the channels */ 3337 3337 - for_each_child_of_node(node, child) { 3337 3337 + for_each_child_of_node_scoped(node, child) { 3338 3338 err = xilinx_dma_child_probe(xdev, child); 3339 3339 - if (err < 0) { 3340 3340 - of_node_put(child); 3339 3339 + if (err < 0) 3341 3340 goto error; 3342 3342 - } 3343 3341 } 3344 3342 3345 3343 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {

+7

include/linux/dma/edma.h

reviewed

··· 73 73 * @ll_region_rd: DMA descriptor link list memory for read channel 74 74 * @dt_region_wr: DMA data memory for write channel 75 75 * @dt_region_rd: DMA data memory for read channel 76 76 + * @db_irq: Virtual IRQ dedicated to interrupt emulation 77 77 + * @db_offset: Offset from DMA register base 76 78 * @mf: DMA register map format 77 79 * @dw: struct dw_edma that is filled by dw_edma_probe() 78 80 */ ··· 96 94 struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH]; 97 95 struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH]; 98 96 97 97 + /* interrupt emulation */ 98 98 + int db_irq; 99 99 + resource_size_t db_offset; 100 100 + 99 101 enum dw_edma_map_format mf; 100 102 101 103 struct dw_edma *dw; 104 104 + bool cfg_non_ll; 102 105 }; 103 106 104 107 /* Export to the platform drivers */

+4 -1

include/linux/dma/qcom-gpi-dma.h

reviewed

··· 8 8 9 9 /** 10 10 * enum spi_transfer_cmd - spi transfer commands 11 11 + * @SPI_TX: SPI peripheral TX command 12 12 + * @SPI_RX: SPI peripheral RX command 13 13 + * @SPI_DUPLEX: SPI peripheral Duplex command 11 14 */ 12 15 enum spi_transfer_cmd { 13 16 SPI_TX = 1, ··· 67 64 * @set_config: set peripheral config 68 65 * @rx_len: receive length for buffer 69 66 * @op: i2c cmd 70 70 - * @muli-msg: is part of multi i2c r-w msgs 67 67 + * @multi_msg: is part of multi i2c r-w msgs 71 68 */ 72 69 struct gpi_i2c_config { 73 70 u8 set_config;

+33 -20

include/linux/dma/ti-cppi5.h

reviewed

··· 16 16 * struct cppi5_desc_hdr_t - Descriptor header, present in all types of 17 17 * descriptors 18 18 * @pkt_info0: Packet info word 0 (n/a in Buffer desc) 19 19 - * @pkt_info0: Packet info word 1 (n/a in Buffer desc) 20 20 - * @pkt_info0: Packet info word 2 (n/a in Buffer desc) 19 19 + * @pkt_info1: Packet info word 1 (n/a in Buffer desc) 20 20 + * @pkt_info2: Packet info word 2 (n/a in Buffer desc) 21 21 * @src_dst_tag: Packet info word 3 (n/a in Buffer desc) 22 22 */ 23 23 struct cppi5_desc_hdr_t { ··· 35 35 * @buf_info1: word 8: Buffer valid data length 36 36 * @org_buf_len: word 9: Original buffer length 37 37 * @org_buf_ptr: word 10/11: Original buffer pointer 38 38 - * @epib[0]: Extended Packet Info Data (optional, 4 words), and/or 38 38 + * @epib: Extended Packet Info Data (optional, 4 words), and/or 39 39 * Protocol Specific Data (optional, 0-128 bytes in 40 40 * multiples of 4), and/or 41 41 * Other Software Data (0-N bytes, optional) ··· 132 132 /** 133 133 * struct cppi5_monolithic_desc_t - Monolithic-mode packet descriptor 134 134 * @hdr: Descriptor header 135 135 - * @epib[0]: Extended Packet Info Data (optional, 4 words), and/or 135 135 + * @epib: Extended Packet Info Data (optional, 4 words), and/or 136 136 * Protocol Specific Data (optional, 0-128 bytes in 137 137 * multiples of 4), and/or 138 138 * Other Software Data (0-N bytes, optional) ··· 179 179 * cppi5_desc_is_tdcm - check if the paddr indicates Teardown Complete Message 180 180 * @paddr: Physical address of the packet popped from the ring 181 181 * 182 182 - * Returns true if the address indicates TDCM 182 182 + * Returns: true if the address indicates TDCM 183 183 */ 184 184 static inline bool cppi5_desc_is_tdcm(dma_addr_t paddr) 185 185 { ··· 190 190 * cppi5_desc_get_type - get descriptor type 191 191 * @desc_hdr: packet descriptor/TR header 192 192 * 193 193 - * Returns descriptor type: 193 193 + * Returns: descriptor type: 194 194 * CPPI5_INFO0_DESC_TYPE_VAL_HOST 195 195 * CPPI5_INFO0_DESC_TYPE_VAL_MONO 196 196 * CPPI5_INFO0_DESC_TYPE_VAL_TR ··· 205 205 * cppi5_desc_get_errflags - get Error Flags from Desc 206 206 * @desc_hdr: packet/TR descriptor header 207 207 * 208 208 - * Returns Error Flags from Packet/TR Descriptor 208 208 + * Returns: Error Flags from Packet/TR Descriptor 209 209 */ 210 210 static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr) 211 211 { ··· 307 307 * @psdata_size: PSDATA size 308 308 * @sw_data_size: SWDATA size 309 309 * 310 310 - * Returns required Host Packet Descriptor size 310 310 + * Returns: required Host Packet Descriptor size 311 311 * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE 312 312 */ 313 313 static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size, ··· 381 381 /** 382 382 * cppi5_hdesc_get_psdata_size - get PSdata size in bytes 383 383 * @desc: Host packet descriptor 384 384 + * 385 385 + * Returns: PSdata size in bytes 384 386 */ 385 387 static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc) 386 388 { ··· 400 398 * cppi5_hdesc_get_pktlen - get Packet Length from HDesc 401 399 * @desc: Host packet descriptor 402 400 * 403 403 - * Returns Packet Length from Host Packet Descriptor 401 401 + * Returns: Packet Length from Host Packet Descriptor 404 402 */ 405 403 static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc) 406 404 { ··· 410 408 /** 411 409 * cppi5_hdesc_set_pktlen - set Packet Length in HDesc 412 410 * @desc: Host packet descriptor 411 411 + * @pkt_len: Packet length to set 413 412 */ 414 413 static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc, 415 414 u32 pkt_len) ··· 423 420 * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc 424 421 * @desc: Host packet descriptor 425 422 * 426 426 - * Returns Protocol Specific Flags from Host Packet Descriptor 423 423 + * Returns: Protocol Specific Flags from Host Packet Descriptor 427 424 */ 428 425 static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc) 429 426 { ··· 434 431 /** 435 432 * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc 436 433 * @desc: Host packet descriptor 434 434 + * @ps_flags: Protocol Specific flags to set 437 435 */ 438 436 static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc, 439 437 u32 ps_flags) ··· 446 442 } 447 443 448 444 /** 449 449 - * cppi5_hdesc_get_errflags - get Packet Type from HDesc 445 445 + * cppi5_hdesc_get_pkttype - get Packet Type from HDesc 450 446 * @desc: Host packet descriptor 447 447 + * 448 448 + * Returns: Packet type 451 449 */ 452 450 static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc) 453 451 { ··· 458 452 } 459 453 460 454 /** 461 461 - * cppi5_hdesc_get_errflags - set Packet Type in HDesc 455 455 + * cppi5_hdesc_set_pkttype - set Packet Type in HDesc 462 456 * @desc: Host packet descriptor 463 457 * @pkt_type: Packet Type 464 458 */ ··· 507 501 /** 508 502 * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc 509 503 * @desc: Host Packet Descriptor 510 510 - * @buf_desc: Host Buffer Descriptor physical address 504 504 + * @hbuf_desc: Host Buffer Descriptor physical address 511 505 * 512 506 * add and link Host Buffer Descriptor to HDesc 513 507 */ ··· 533 527 * cppi5_hdesc_epib_present - check if EPIB present 534 528 * @desc_hdr: packet descriptor/TR header 535 529 * 536 536 - * Returns true if EPIB present in the packet 530 530 + * Returns: true if EPIB present in the packet 537 531 */ 538 532 static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr) 539 533 { ··· 544 538 * cppi5_hdesc_get_psdata - Get pointer on PSDATA 545 539 * @desc: Host packet descriptor 546 540 * 547 547 - * Returns pointer on PSDATA in HDesc. 541 541 + * Returns: pointer on PSDATA in HDesc. 548 542 * NULL - if ps_data placed at the start of data buffer. 549 543 */ 550 544 static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc) ··· 574 568 * cppi5_hdesc_get_swdata - Get pointer on swdata 575 569 * @desc: Host packet descriptor 576 570 * 577 577 - * Returns pointer on SWDATA in HDesc. 571 571 + * Returns: pointer on SWDATA in HDesc. 578 572 * NOTE. It's caller responsibility to be sure hdesc actually has swdata. 579 573 */ 580 574 static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc) ··· 654 648 CPPI5_TR_TYPE11, 655 649 /* type12-14: Reserved */ 656 650 CPPI5_TR_TYPE15 = 15, 651 651 + /* private: */ 657 652 CPPI5_TR_TYPE_MAX 658 653 }; 659 654 ··· 680 673 CPPI5_TR_EVENT_SIZE_ICNT1_DEC, 681 674 CPPI5_TR_EVENT_SIZE_ICNT2_DEC, 682 675 CPPI5_TR_EVENT_SIZE_ICNT3_DEC, 676 676 + /* private: */ 683 677 CPPI5_TR_EVENT_SIZE_MAX 684 678 }; 685 679 ··· 698 690 CPPI5_TR_TRIGGER_GLOBAL0, 699 691 CPPI5_TR_TRIGGER_GLOBAL1, 700 692 CPPI5_TR_TRIGGER_LOCAL_EVENT, 693 693 + /* private: */ 701 694 CPPI5_TR_TRIGGER_MAX 702 695 }; 703 696 ··· 720 711 CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC, 721 712 CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC, 722 713 CPPI5_TR_TRIGGER_TYPE_ALL, 714 714 + /* private: */ 723 715 CPPI5_TR_TRIGGER_TYPE_MAX 724 716 }; 725 717 ··· 825 815 * destination 826 816 * @dicnt1: Total loop iteration count for level 1 for destination 827 817 * @dicnt2: Total loop iteration count for level 2 for destination 828 828 - * @sicnt3: Total loop iteration count for level 3 (outermost) for 818 818 + * @dicnt3: Total loop iteration count for level 3 (outermost) for 829 819 * destination 830 820 */ 831 821 struct cppi5_tr_type15_t { ··· 897 887 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR, 898 888 CPPI5_TR_RESPONSE_STATUS_TRANSFER_EXCEPTION, 899 889 CPPI5_TR_RESPONSE_STATUS__TEARDOWN_FLUSH, 890 890 + /* private: */ 900 891 CPPI5_TR_RESPONSE_STATUS_MAX 901 892 }; 902 893 ··· 914 903 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0, 915 904 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL, 916 905 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN, 906 906 + /* private: */ 917 907 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX 918 908 }; 919 909 ··· 943 931 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT, 944 932 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR, 945 933 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC, 934 934 + /* private: */ 946 935 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX 947 936 }; 948 937 ··· 952 939 * @tr_count: number of TR records 953 940 * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128] 954 941 * 955 955 - * Returns required TR Descriptor size 942 942 + * Returns: required TR Descriptor size 956 943 */ 957 944 static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size) 958 945 { ··· 968 955 969 956 /** 970 957 * cppi5_trdesc_init - Init TR Descriptor 971 971 - * @desc: TR Descriptor 958 958 + * @desc_hdr: TR Descriptor 972 959 * @tr_count: number of TR records 973 960 * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128] 974 961 * @reload_idx: Absolute index to jump to on the 2nd and following passes ··· 1057 1044 } 1058 1045 1059 1046 /** 1060 1060 - * cppi5_tr_cflag_set - Update the Configuration specific flags 1047 1047 + * cppi5_tr_csf_set - Update the Configuration specific flags 1061 1048 * @flags: Pointer to the TR's flags 1062 1049 * @csf: Configuration specific flags 1063 1050 *

+2 -1

include/linux/dmaengine.h

reviewed

··· 996 996 * @vecs: The array of DMA vectors that should be transferred 997 997 * @nents: The number of DMA vectors in the array 998 998 * @dir: Specifies the direction of the data transfer 999 999 - * @flags: DMA engine flags 999 999 + * @flags: DMA engine flags - DMA_PREP_REPEAT can be used to mark a cyclic 1000 1000 + * DMA transfer 1000 1001 */ 1001 1002 static inline struct dma_async_tx_descriptor *dmaengine_prep_peripheral_dma_vec( 1002 1003 struct dma_chan *chan, const struct dma_vec *vecs, size_t nents,

+29

include/linux/of_dma.h

reviewed

··· 38 38 void *data); 39 39 extern void of_dma_controller_free(struct device_node *np); 40 40 41 41 + static void __of_dma_controller_free(void *np) 42 42 + { 43 43 + of_dma_controller_free(np); 44 44 + } 45 45 + 46 46 + static inline int 47 47 + devm_of_dma_controller_register(struct device *dev, struct device_node *np, 48 48 + struct dma_chan *(*of_dma_xlate) 49 49 + (struct of_phandle_args *, struct of_dma *), 50 50 + void *data) 51 51 + { 52 52 + int ret; 53 53 + 54 54 + ret = of_dma_controller_register(np, of_dma_xlate, data); 55 55 + if (ret) 56 56 + return ret; 57 57 + 58 58 + return devm_add_action_or_reset(dev, __of_dma_controller_free, np); 59 59 + } 60 60 + 41 61 extern int of_dma_router_register(struct device_node *np, 42 62 void *(*of_dma_route_allocate) 43 63 (struct of_phandle_args *, struct of_dma *), ··· 82 62 83 63 static inline void of_dma_controller_free(struct device_node *np) 84 64 { 65 65 + } 66 66 + 67 67 + static inline int 68 68 + devm_of_dma_controller_register(struct device *dev, struct device_node *np, 69 69 + struct dma_chan *(*of_dma_xlate) 70 70 + (struct of_phandle_args *, struct of_dma *), 71 71 + void *data) 72 72 + { 73 73 + return -ENODEV; 85 74 } 86 75 87 76 static inline int of_dma_router_register(struct device_node *np,

+3 -2

include/linux/platform_data/dma-mcf-edma.h

reviewed

··· 26 26 /** 27 27 * struct mcf_edma_platform_data - platform specific data for eDMA engine 28 28 * 29 29 - * @ver The eDMA module version. 30 30 - * @dma_channels The number of eDMA channels. 29 29 + * @dma_channels: The number of eDMA channels. 30 30 + * @slave_map: Slave device map 31 31 + * @slavecnt: Number of entries in @slave_map 31 32 */ 32 33 struct mcf_edma_platform_data { 33 34 int dma_channels;