Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
- bugfixes for uniphier, i801, and xiic drivers
- ID removal (never produced) for imx
- one MAINTAINER addition
* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: xiic: Record xilinx i2c with Zynq fragment
i2c: xiic: Make the start and the byte count write atomic
i2c: i801: fix DNV's SMBCTRL register offset
i2c: imx-lpi2c: Remove mx8dv compatible entry
dt-bindings: imx-lpi2c: Remove mx8dv compatible entry
i2c: uniphier-f: issue STOP only for last message or I2C_M_STOP
i2c: uniphier: issue STOP only for last message or I2C_M_STOP
+16
-14
+1
-2
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
+1
-2
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
···
3
3
Required properties:
4
4
- compatible :
5
5
- "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc
6
-
- "fsl,imx8dv-lpi2c" for LPI2C compatible with the one integrated on i.MX8DV soc
7
6
- reg : address and length of the lpi2c master registers
8
7
- interrupts : lpi2c interrupt
9
8
- clocks : lpi2c clock specifier
···
10
11
Examples:
11
12
12
13
lpi2c7: lpi2c7@40a50000 {
13
-
compatible = "fsl,imx8dv-lpi2c";
14
+
compatible = "fsl,imx7ulp-lpi2c";
14
15
reg = <0x40A50000 0x10000>;
15
16
interrupt-parent = <&intc>;
16
17
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+1
MAINTAINERS
+1
MAINTAINERS
+6
-1
drivers/i2c/busses/i2c-i801.c
+6
-1
drivers/i2c/busses/i2c-i801.c
···
140
140
141
141
#define SBREG_BAR 0x10
142
142
#define SBREG_SMBCTRL 0xc6000c
143
+
#define SBREG_SMBCTRL_DNV 0xcf000c
143
144
144
145
/* Host status bits for SMBPCISTS */
145
146
#define SMBPCISTS_INTS BIT(3)
···
1400
1399
spin_unlock(&p2sb_spinlock);
1401
1400
1402
1401
res = &tco_res[ICH_RES_MEM_OFF];
1403
-
res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1402
+
if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1403
+
res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1404
+
else
1405
+
res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1406
+
1404
1407
res->end = res->start + 3;
1405
1408
res->flags = IORESOURCE_MEM;
1406
1409
-1
drivers/i2c/busses/i2c-imx-lpi2c.c
-1
drivers/i2c/busses/i2c-imx-lpi2c.c
+2
-5
drivers/i2c/busses/i2c-uniphier-f.c
+2
-5
drivers/i2c/busses/i2c-uniphier-f.c
···
401
401
return ret;
402
402
403
403
for (msg = msgs; msg < emsg; msg++) {
404
-
/* If next message is read, skip the stop condition */
405
-
bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
406
-
/* but, force it if I2C_M_STOP is set */
407
-
if (msg->flags & I2C_M_STOP)
408
-
stop = true;
404
+
/* Emit STOP if it is the last message or I2C_M_STOP is set. */
405
+
bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
409
406
410
407
ret = uniphier_fi2c_master_xfer_one(adap, msg, stop);
411
408
if (ret)
+2
-5
drivers/i2c/busses/i2c-uniphier.c
+2
-5
drivers/i2c/busses/i2c-uniphier.c
···
248
248
return ret;
249
249
250
250
for (msg = msgs; msg < emsg; msg++) {
251
-
/* If next message is read, skip the stop condition */
252
-
bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
253
-
/* but, force it if I2C_M_STOP is set */
254
-
if (msg->flags & I2C_M_STOP)
255
-
stop = true;
251
+
/* Emit STOP if it is the last message or I2C_M_STOP is set. */
252
+
bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
256
253
257
254
ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
258
255
if (ret)
+4
drivers/i2c/busses/i2c-xiic.c
+4
drivers/i2c/busses/i2c-xiic.c
···
532
532
{
533
533
u8 rx_watermark;
534
534
struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
535
+
unsigned long flags;
535
536
536
537
/* Clear and enable Rx full interrupt. */
537
538
xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
···
548
547
rx_watermark = IIC_RX_FIFO_DEPTH;
549
548
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
550
549
550
+
local_irq_save(flags);
551
551
if (!(msg->flags & I2C_M_NOSTART))
552
552
/* write the address */
553
553
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
···
558
556
559
557
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
560
558
msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
559
+
local_irq_restore(flags);
560
+
561
561
if (i2c->nmsgs == 1)
562
562
/* very last, enable bus not busy as well */
563
563
xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);