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clk: microchip: mpfs: convert periph_clk to clk_gate

With the reset code moved to the recently added reset controller, there
is no need for custom ops any longer. Remove the custom ops and the
custom struct by converting to a clk_gate.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-14-conor.dooley@microchip.com

authored by

Conor Dooley and committed by
Claudiu Beznea d8155697 4da2404b

+6 -66
+6 -66
drivers/clk/microchip/clk-mpfs.c
··· 56 56 u32 reg_offset; 57 57 }; 58 58 59 - struct mpfs_periph_clock { 60 - void __iomem *reg; 61 - u8 shift; 62 - }; 63 - 64 59 struct mpfs_periph_hw_clock { 65 - struct mpfs_periph_clock periph; 66 - struct clk_hw hw; 60 + struct clk_gate periph; 67 61 unsigned int id; 68 62 }; 69 - 70 - #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 71 63 72 64 /* 73 65 * mpfs_clk_lock prevents anything else from writing to the ··· 268 276 * peripheral clocks - devices connected to axi or ahb buses. 269 277 */ 270 278 271 - static int mpfs_periph_clk_enable(struct clk_hw *hw) 272 - { 273 - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 274 - struct mpfs_periph_clock *periph = &periph_hw->periph; 275 - u32 reg, val; 276 - unsigned long flags; 277 - 278 - spin_lock_irqsave(&mpfs_clk_lock, flags); 279 - 280 - reg = readl_relaxed(periph->reg); 281 - val = reg | (1u << periph->shift); 282 - writel_relaxed(val, periph->reg); 283 - 284 - spin_unlock_irqrestore(&mpfs_clk_lock, flags); 285 - 286 - return 0; 287 - } 288 - 289 - static void mpfs_periph_clk_disable(struct clk_hw *hw) 290 - { 291 - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 292 - struct mpfs_periph_clock *periph = &periph_hw->periph; 293 - u32 reg, val; 294 - unsigned long flags; 295 - 296 - spin_lock_irqsave(&mpfs_clk_lock, flags); 297 - 298 - reg = readl_relaxed(periph->reg); 299 - val = reg & ~(1u << periph->shift); 300 - writel_relaxed(val, periph->reg); 301 - 302 - spin_unlock_irqrestore(&mpfs_clk_lock, flags); 303 - } 304 - 305 - static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 306 - { 307 - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 308 - struct mpfs_periph_clock *periph = &periph_hw->periph; 309 - u32 reg; 310 - 311 - reg = readl_relaxed(periph->reg); 312 - if (reg & (1u << periph->shift)) 313 - return 1; 314 - 315 - return 0; 316 - } 317 - 318 - static const struct clk_ops mpfs_periph_clk_ops = { 319 - .enable = mpfs_periph_clk_enable, 320 - .disable = mpfs_periph_clk_disable, 321 - .is_enabled = mpfs_periph_clk_is_enabled, 322 - }; 323 - 324 279 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 325 280 .id = _id, \ 326 - .periph.shift = _shift, \ 327 - .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 281 + .periph.bit_idx = _shift, \ 282 + .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ 328 283 _flags), \ 284 + .periph.lock = &mpfs_clk_lock, \ 329 285 } 330 286 331 287 #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) ··· 334 394 struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 335 395 336 396 periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; 337 - ret = devm_clk_hw_register(dev, &periph_hw->hw); 397 + ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); 338 398 if (ret) 339 399 return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 340 400 periph_hw->id); 341 401 342 402 id = periph_hws[i].id; 343 - data->hw_data.hws[id] = &periph_hw->hw; 403 + data->hw_data.hws[id] = &periph_hw->periph.hw; 344 404 } 345 405 346 406 return 0;